Abstract: Provided is a system on chip (SoC) capable of rapidly processing interrupts generated in various modules without causing an error. The SoC includes a processor configured to process a task, a plurality of modules on the SoC and operationally coupled to the processor through a system bus, and an interrupt proxy processing unit operationally coupled to the processor and the plurality of modules and configured to solely process an interrupt-related task from a first module of the plurality of modules.

Abstract: Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution.

Abstract: Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.

Abstract: Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element.

Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.

Abstract: In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.

Abstract: A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp.

Abstract: A method and apparatus are provided for docking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means for providing a common dock signal to modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the docking frequency required by each module. Clock pulses are applied to modules between which data is to be transferred at times consistent with the data transfer.

Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: Techniques are described for determining a temporary latency tolerance report (tLTR) value. A processing unit has to respond to a device interrupt within a duration specified by tLTR to ensure no incoming data is lost due to device buffer overflow. The tLTR value can be used to prevent the processing unit from entering too deep a sleep state when a device driver anticipates multiple sequential interrupts for a transaction.

Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.

Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC.

Abstract: System and method for handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor are described. In one embodiment, the method comprises the first processor disabling an interrupt function on the first pin; and, subsequent to the disabling, interrupting the second processor by driving the first pin to a first logic level and then releasing the first pin to a second logic level.

Abstract: An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.

Abstract: An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.

Abstract: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

Abstract: In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O) commands for which corresponding I/O completions have not been received. Deliveries of interrupts are executed on the basis of the current level and in an absence of enabling timing-triggered delivery of an interrupt.

Abstract: A memory control unit is connected to a first bus and a second bus and that controls writing and reading of data to a memory; a control unit controls the information processing apparatus; a first circuit device is connected to the first bus and outputs a data write request to the memory control unit and a notification signal; a second circuit device is connected to the first bus and outputs a data read request to the memory control unit in accordance with the notification signal and an interrupt signal to the control unit in response to the data read request; and a third circuit device is connected to the second bus and outputs a data read request stored in the memory to the memory control unit in accordance with an instruction from the control unit which has received an interrupt signal.

Abstract: A peripheral device sends an interrupt generation notification to a bus bridge. The bus bridge receives the interrupt generation notification, transfers the received interrupt generation notification to a CPU, reads an interrupt cause from the peripheral device that has sent the interrupt generation notification, and writes to a memory the interrupt cause that has been read. Upon receiving the interrupt generation notification, the CPU reads the interrupt cause from the memory which allows fast access, and begins interrupt processing corresponding to the interrupt cause. Interrupt processing time up to commencement of the interrupt processing can be reduced.

Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt signal; using the determined type to access control information indicating an action to be applied to the determined type of interrupt; and blocking, passing or remapping the interrupt signal in response to the control information. The apparatus comprises a memory, an interrupt unit and a logic circuit. The memory is adapted to store control information regarding a plurality of types of interrupt signals. The interrupt unit is adapted to receive the interrupt signal, and use the interrupt type contained in the interrupt signal to access the control information stored in the memory. The logic circuit is adapted to block, pass or remap said interrupt signal in response to the control information.

Abstract: A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of the interrupts among the processors. If so, the interrupt daemon triggers a reassignment routine that generates a new mapping of the interrupts among the processors, and if not, the interrupt daemon goes to sleep for a specified time period. If the new mapping produces a sufficient improvement in the distribution of interrupts among the processors, based on the same criteria used to detect the imbalance, the new mapping is used by the central hub for subsequent distribution of interrupts to the processors. However, if the new mapping does not provide a sufficient improvement, the original mapping continues to be used.

Abstract: In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.

Abstract: A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.

Abstract: A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.

Abstract: During a period from a time when an input coordinate is interrupted to a time when an interruption compensation period, which is set on the basis of a moving speed of the input coordinate, elapses, an example information processing apparatus determines that an operator continues an input operation, and performs coordinate complementation. Specifically, as the moving speed of the input coordinate increases, the interruption compensation period increases. Then, when the interruption compensation period elapses, the information processing apparatus determines that the operator has ended the input operation.

Abstract: An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor, The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler.

Abstract: A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Abstract: A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread.

Abstract: A method and apparatus for processing data in which a function is processed using a processor operable to perform a plurality of functions is disclosed. When an interrupt is received during processing of the function at a point during the processing at which a portion of the function has been processed then a control parameter is accessed. In response to the control parameter having a value indicting that the function has idempotence processing of the function is stopped without processing the function further, and information on progress of the function is discarded such that following completion of the interrupt the portion of the function that has already been processed is processed again.

Abstract: A method of processing J1850 requests using a scan tool having multiple processor systems is provided. The scan tool includes a first processor that processes data according to scan tool functions to assist with diagnosing and repairing a vehicle. A second processor receives data transmitted to the first processor and stores the data in a buffer. The second processor determines whether the data is complete to enable the first processor to make a determination regarding the data.

Abstract: A data processing device for detecting the abnormal operation of a CPU is provided. The data processing device comprises a CPU, an interrupt counter, and a counter-abnormal-value detection circuit. The interrupt counter increments a count value based on an interrupt start signal which is outputted in response to an interrupt signal indicative of an interrupt request to the CPU and which indicates that the interrupt request has been accepted, and decrements the count value based on an end-of-interrupt signal which indicates that processing corresponding to the interrupt has completed. The counter-abnormal-value detection circuit detects abnormalities by comparing the count value with a predetermined value.

Abstract: A data processing system is provided which comprises at least two processing units (100, 101, 102) each for executing a plurality of tasks and an interrupt handling unit (200) for receiving an interrupt to be processed by the data processing system and for distributing the interrupt to one of the at least two processing units (100, 101, 102). The processing unit (100, 101, 102) to which the interrupt is distributed stops its current execution of the task and processes the interrupt. The interrupt handling unit (200) is adapted to determine whether the processing units (100, 101, 102) are executing a critical section (CS) of the task. The interrupt handling unit (200) distributes the interrupt to one of the processing units (100, 101, 102), which is not executing a critical section (CS) of a task.

Abstract: An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.

Abstract: A network interface that connects a computing device to a network may be configured to process incoming packets and determine an action to take with respect to each packet, thus decreasing processing demands on a processor of the computing device. The action may be indicating the packet to an operating system of the computing device immediately, storing the packet in a queue of one or more queues or discarding the packet. When the processor is interrupted, multiple packets aggregated on the network interface may be indicated to the operating system all at once to increase the device's power efficiency. Hardware of the network interface may be programmed to process the packets using filter criteria specified by the operating system based on information gathered by the operating system, such as firewall rules.

Abstract: The present invention aims to provide a host controller apparatus, an information processing apparatus, and an event information output method that are capable of outputting event information to a system memory while achieving power saving. A host controller apparatus according to the present invention includes: an event controller that outputs occurred event information to a system memory; and an interruption controller that outputs an interrupt signal to a CPU executing an event recorded in the system memory, the interrupt signal requesting execution of the event output from the event controller to the system memory. The event controller outputs the occurred event information to the system memory in synchronization with a timing at which the interruption controller outputs the interrupt signal to the CPU.

Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.

Abstract: An information processing device of the present invention comprises a main CPU capable of taking at least two states which are an operating state and a sleeping state, a sub-CPU having power consumption lower than that of the main CPU and capable of taking at least two states which are an operating state and a sleeping state, and a process request determining section for determining which of the main CPU and the sub-CPU is caused to execute a process related to a request from a peripheral device. The process request determining section determines whether the main CPU is in the sleeping state or the operating state, and when the main CPU is in the sleeping state, determines whether or not the sub-CPU can be caused to execute the process, and when the main CPU is in the operating state, determines whether or not the main CPU can be caused to execute the process, and depending on a result of the determination, causes the main CPU or the sub-CPU to execute the process.

Abstract: Technologies are generally described herein for handling interrupts within a multiprocessor computing system. A priority level associated with a current task for each processor of the multiprocessor computing system can be maintained. Cache state information associated with each processor can also be maintained. Upon receiving an interrupt to the multiprocessor computing system, a cache locality score for each processor can be determined based on the maintained cache state information. A value can be computed that balances, for each processor, the priority level and the cache locality score. A processor for servicing the interrupt can be determined based on the computed value. The determined processor can be signaled to service the interrupt. Tracking state information related to processor cores can support rapid allocation of an arriving interrupt to a processor core without collecting processor core state information at interrupt time.

Abstract: An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract: A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The interrupt controller identifies a preferred CPU associated with the device based on a predetermined binding. If the preferred CPU is currently available, the interrupt is sent to the preferred CPU. If the preferred CPU is not currently available, the interrupt is sent to another CPU in the computer system that is currently available.

Abstract: The present disclosure relates to a method of processing an interrupt comprising a peripheral unit sending an interrupt, the interrupt being intended for a virtual unit executed by a processing unit, transmitting the interrupt to an interrupt control unit coupled to a processing unit, and the interrupt control unit storing the interrupt in an interrupt register. According to an embodiment of the present disclosure, the interrupt is transmitted to the interrupt control unit in association with an identifier of the virtual unit receiving the interrupt, the interrupt register in which the interrupt belonging to a set of registers is stored comprising one interrupt register per virtual unit likely to be executed by the processing unit, the interrupt being transmitted to the processing unit if the virtual unit receiving the interrupt is being executed by the processing unit.