Abstract: A direct memory access controller (DMAC) for improving data transmission efficiency in multi-media over internet protocol (MMoIP) and a method therefor are provided. The DMAC requests and obtains a bus control right by determining that a DMA request signal is generated not only when a DMA request signal of a module for processing data in MMoIP is received but also when an operation of a timer operating during a predetermined period set considering periodicity of data in MMoIP is completed. Thus, the time taken to request a bus control right in a conventional DMAC can be reduced, thereby improving data transmission efficiency in MMoIP.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H?, thereafter generating Q? and R? subject to the same constraints as was described for Q and R. Transformed variables Z and Z? are formed by multiplying Y by QH and Q?H, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and also including a distance metric.

Abstract: A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to correspond to the other devices, the channel units retaining DMA transfer instructions, and outputting number of the DMA transfer instructions retained; a plurality of priority controllers for determining priorities of the channel units on the basis of the number of the DMA transfer instructions retained in the channel units, respectively; an arbiter for selecting one of the DMA transfer instructions retained in one of the channel units on the basis of the priorities determined by the priority controller; and a data transfer processor for performing DMA transfer of data stored in the storage unit to one of the other devices in accordance with the DMA transfer instruction selected by the arbiter.

Abstract: The disk array apparatus includes a controller having a communication control unit for accepting a data input/output request, a disk controller unit for controlling a plurality of disk drives, and a cache memory for temporarily storing data transferred between the communication control unit and the disk controller unit. A plurality of cooling fans are provided for cooling the plurality of disk drives. In response to receiving a request, the controller controls the rotational speed of a first cooling fan related to a first disk drive, which is related to the request, and changes an operational mode of the first disk drive related to the request such that the rotational speed of the first cooling fan is increased before the operational mode of the first disk drive is changed.

Abstract: A request to perform an operation, such as a remote direct memory access (RDMA) write operation or a send operation that writes to memory, is sent from a sending input/output (I/O) adapter (e.g., an RDMA-capable adapter) to a receiving I/O adapter. The receiving I/O adapter receives the request and initiates performance of the operation, but delays sending an acknowledgment for the operation. The acknowledgment is delayed until the operation is complete (i.e., until the memory is updated and the data is visible to the remote processor), as determined by a read operation initiated and performed by the receiving I/O adapter transparent to the sending I/O adapter.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device.

Abstract: Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller device driver and is provided to the host controller as needed to process the queued commands. The host controller is simplified since it only stores the context of the one command being processed. The host controller generates a backoff interrupt when a command cannot be queued. The host controller generates a DMA transfer context request interrupt to request programming of the registers that store the context for the one command being processed.

Abstract: A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.

Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer construct is made accessible to one or more direct memory access (DMA) operations. Upon completion of the one or more DMA operations, the buffer construct transitions from the closed state to the open state. The region of memory represented by the buffer construct is made accessible for use with one or more cache operations when the buffer construct is in the open state, so that the one or more cache operations are not in conflict with the one or more DMA operations.

Abstract: A computer system is provided that utilizes a buffer construct to manage memory access operations to a region of memory. The buffer construct may correspond to a data item or structure that represents a region of memory. Each task may control the buffer construct exclusively of other tasks, so that the region of memory that is represented by the buffer construct is only available to the controlling task. Another task that requires access to the region of memory must wait until the controlling task makes the buffer construct available. The controlling task makes the buffer construct available only when DMA or other memory access operations that are in progress become complete. In this way, the buffer construct acts as a token that synchronizes each of the concurrent tasks execution and ensures mutually exclusive access to the common region of memory.

Abstract: Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Abstract: An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.

Abstract: An architecture and associated methods and devices are described in which a first selectable data path may be associated with a first port operating at a first data rate, a second selectable data path may be associated with a second port operating at a second data rate, and a third selectable data path may be associated with a third port operating at a third data rate that is higher than the first data rate and the second data rate. A plurality of security engines may be included which may be configurable to provide cipher key-based security for data associated with the first port and the second port using the first selectable path and the second selectable path, respectively, and configurable to provide cipher key-based security of data associated with the third port using the third selectable data path.

Abstract: A system for enforcing a storage allocation usage right(s) for an application may include a controllable storage and a storage manager to control the access of the application to the storage according to an associated storage allocation usage right. A SIM card for enforcing a storage allocation usage right for an application may include an application register to store an access rule of the storage allocation usage right(s) and an APREC module to identify the application and thereby an access rule to enable controlling of the access of the application to storage according to the storage allocation usage right. A high-capacity SIM card for enforcing a storage allocation usage right for an application may include a storage; a storage manager to control the access of an application to the storage according to an associated access rule of the storage allocation usage right; and an APREC module.

Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-blocking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.

Abstract: An apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit of the apparatus includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.

Abstract: Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.

Abstract: Virtualizing a host USB adapter in a virtualized environment maintained by a hypervisor, the hypervisor administering one or more logical partitions, where virtualizing includes receiving, by the hypervisor from a logical partition via a logical USB adapter, a USB Input/Output (‘I/O’) request, the logical USB adapter associated with a USB device coupled to the host USB adapter; placing, by the hypervisor, a work queue element (‘WQE’) in a queue of a queue pair associated with the logical USB adapter; and administering, by an interface device in dependence upon the WQE, USB data communications among the logical partition and the USB device including retrieving, with direct memory access (‘DMA’), USB data originating at the USB device from the host USB adapter into a dedicated memory region for the logical USB adapter.

Abstract: An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator is defined to consider a different portion of the multiple requestors when selecting a requestor to be serviced by the master to which the arbitrator is assigned. Each arbitrator is further defined to select a requestor from the different portion of the multiple requestors, such that selection of a particular requestor is not duplicated among the plurality of arbitrators. Additionally, requestor selection by each of the plurality of arbitrators is performed in a same clock cycle.

Abstract: A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined to select a different one of the multiple requestors to be serviced by the master to which the arbitrator is assigned. Also, the plurality of arbitrators is defined to make their requestor selections in the same clock cycle. Additionally, the plurality of arbitrators is defined to make their requestor selections such that selection of a particular requestor is not duplicated among the plurality of arbitrators.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.

Abstract: A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus, and a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus. The addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus. The monitor circuit compares the address transferred on the first bus with a preset monitor target address. The CPU acquires the comparison results by the monitor circuit. If the comparison results show an address match, then the CPU accesses the first memory. The CPU can in this way access the first memory at a correct timing.

Abstract: A Content-Terminated Direct Memory Access (CT-DMA) circuit autonomously transfers data of an unknown length from a source to a destination, terminating the transfer based on the content of the data. Filter criteria are provided to the CT-DMA prior to the data transfer. The filter criteria include pattern data that are compared to transfer data, and transfer termination rules for interpreting the comparison results. Data are written to the destination until the filter criteria are met. Representative filter criteria may include that one or more units of transfer data match pattern data; that one or more units of transfer data fail to match pattern data; or that one or more units of transfer data match pattern data a predetermined number of times.

Abstract: A storage system includes a host computer coupled to a device to transfer a DMA descriptor between the host and the device. An integrity manager manages the integrity of the DMA descriptor between the host computer and the device. The integrity manager embeds a host-side DMA descriptor integrity value in the DMA descriptor and the device transfers the DMA descriptor to a device memory. The device generates a device-side DMA descriptor integrity value and compares it to the host-side DMA descriptor integrity value to determine if the descriptor is corrupted.

Abstract: Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a predetermined voltage signal is received from the transmitting device, then the receiving device is transferred to a state for a second type of transmitting device.

Abstract: A system and method are disclosed which may include providing a processor operable to request an ongoing processor operation DMA communication task; providing at least one data transfer device operable to request a defined-content DMA communication task; providing a memory operable to conduct DMA communication with the processor and the at least one data transfer device over at least one data bus, the DMA communication having a bandwidth; and allocating the DMA communication bandwidth between the processor operation DMA communication task and the defined-content DMA communication task.

Abstract: A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting patterns of the appearances preceding a qualifying quiet period on the data bus; a qualifying quiet period being a time interval having a duration greater than a predetermined duration with no traffic on the data bus; (c) employing the patterns to determine probability of occurrence of a qualifying quiet period following at least one pattern; and (d) permitting the second bus controller to control operation of the data bus during a respective qualifying quiet period when the probability of occurrence for the respective qualifying quiet period is greater than a predetermined value.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Abstract: A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a memory access request requires multiple data bursts on the memory bus, the SDRAM controller stores the data from the multiple data bursts in respective buffers. Data is then retrieved from the buffers such that data is read from a part of the first buffer, then from the other buffers, and finally from the remaining part of the first buffer. Storing the required data in the remaining part of the first buffer avoids the need to occupy the memory bus with a new data burst.

Abstract: A buffer availability manager ensures that buffers are available before processes write thereto. The buffer availability manager maintains a plurality of register sets corresponding to the plurality of buffers. Each register set comprises a status indicator and a generation counter. Prior to writing to a buffer, the corresponding register set is read. Data is written to an individual buffer only if the status indicator indicates that the buffer is not busy, and the current value of the generation counter is not equal to a stored value from a prior register set read. The buffer availability manager detects writing of data to the buffer, and in response updates the status indicator to indicate that the buffer is busy. After processing the data in the buffer, the buffer availability manager updates the status indicator to not busy, and updates the value of the generation counter.

Abstract: A protection register array in which the lock status of the protection register is stored outside of the array. An initial verify function is used to read lock status.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

Abstract: A memory allocation method for a direct memory access controller (DMAC) in a limited-memory-size computer system includes the steps of allocating a memory space having continuous memory addresses to form a buffer of the DMAC; dividing the memory space successively into a plurality of first memory blocks and a second memory block, wherein the size of the second memory block is equal to a maximum frame size possibly accessed by the DMAC; and assigning the plurality of first memory blocks and the second memory block to a plurality of descriptors in order, wherein each of the plurality of descriptors is utilized for recording a memory address of a corresponding memory block as a pointers for the corresponding memory block.

Abstract: A data transfer device includes: a plurality of storage devices (10) including a plurality of transfer sources (TS) of which storage regions are different from each other and setting registers (40) of which number is equal to the number of the transfer sources (TS). The setting registers (40) stores for the transfer sources (TS) DMA transfer settings of the transfer sources (TS), and a DMA control section (20) performs data transfer control on the basis of the set values of the setting registers (40).

Abstract: An IO adapter for guaranteeing the data transfer bandwidth on each capsule interface when multiple capsule interfaces jointly share the DMA engine of the IO adapter. An IO driver containing a capsule interface information table including bandwidth information and for setting the forming status of a pair of capsule interfaces and, during data transfer subdivides the descriptors for the capsule interfaces into multiple groups for each data buffer size satisfying the preset bandwidth information and, copies one group at each fixed sample time set by the descriptor registration means, into the descriptor ring and performs DMA transfer. To control this copy information, the IO driver contains a ring scheduler information table for managing the number of descriptor entries for the capsule interface cycle time and, a ring scheduler cancel means for renewing the entries in the ring scheduler information table each time one transmission of the descriptor group ends.

Abstract: A direct memory access (DMA) transfer apparatus configured to sequentially read, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA transfer processing based on the read transfer setting value includes a unit configured to receive a No Operation (NOP) designation for designating no performance of DMA transfer as the transfer setting value, and a unit configured to generate, if the NOP designation has been performed with the transfer setting value read into the register, an NOP interrupt signal to end transfer processing without performing the DMA transfer.

Abstract: Embodiments may comprise logic such as hardware and/or code within a heterogeneous multi-core processor or the like to coordinate reading from and writing to buffers substantially simultaneously. Many embodiments include multi-buffering logic for implementing a procedure for a processing unit of a specialized processing element. The multi-buffering logic may instruct a direct memory access controller of the specialized processing element to read data from some memory location and store the data in a first buffer. The specialized processing element can then process data in the second buffer and, thereafter, the multi-buffering logic can block read access to the first buffer until the direct memory access controller indicates that the read from the memory location is complete. In such embodiments, the multi-buffering logic may then instruct the direct memory access controller to write the processed data to other memory.

Abstract: A method and system for enabling personal digital assistants (PDAs) and protecting stored private data. Specifically, one embodiment in accordance with the present invention includes a removable expansion card about the size of a postage stamp which plugs into a slot of a personal digital assistant. The removable expansion card, referred to as a personality card, is capable of storing all of a user's private information and data which is used within their personal digital assistant. By removing the personality card from the personal digital assistant, all of the user's private information and data may be removed from the personal digital assistant. Furthermore, the personal digital assistant may also be rendered totally or partially useless once the personality card is removed from it. There are several advantages associated with a personality card system in accordance with the present invention.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals received from each of a plurality of ports. The apparatus generally provides dynamic priority arbitration for the plurality of ports.

Abstract: A method for evaluating performance of DMA-based algorithmic tasks on a target multi-core processing system includes the steps of: inputting a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; evaluating performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and providing results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.