Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: An apparatus includes a controller and a plurality of disk drives. The controller has a communication control unit for accepting a data input/output request, a disk controller unit for controlling a disk drive, and a cache memory for temporarily storing data transferred between the communication control unit and the disk controller unit. The plurality of disk drives has different communication interfaces and connected to the disk controller unit to communicate with the disk controller unit.

Abstract: Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.

Abstract: According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller directed to a source unit, the read command including an identifier which matches the identifier in the write command, the source unit transmitting read data on a split transaction bus, the read data including the identifier of the read command, and receiving the read data at the destination unit via the split transaction bus if the identifier of the read data matches the identifier of the write command.

Abstract: A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.

Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.

Abstract: Peripheral interface(s), a receiving apparatus and a data communication method using the same are disclosed. According to an embodiment of the present invention, a peripheral interface comprises one or more pins for multiplexing at least two types of interfaces, wherein the pins transmit interface signals corresponding to an interface type and type-associated operating mode which are selected from those multiplexed by the pins. According to another embodiment, a receiving apparatus comprises: a peripheral interface for multiplexing at least two types of interfaces; a receiving module for receiving an instruction signal; a selecting module for selecting an interface type and type-associated operating mode which corresponds to an external device to be connected, based on the instruction signal; a controlling module for controlling the peripheral interface to communicate with the external device via at least one interface signal corresponding to the selected interface type and type-associated operating mode.

Abstract: Provided is a computer system including a plurality of data storage apparatus and manages a bandwidth of a data storage apparatus according to an attribute of a storage volume. A storage system includes an interface for processing access to the storage volume from a host computer, and a control unit for controlling allocation of the storage volume to the host computer. A management computer transmits a request of setting a bandwidth to be accessed by the host computer via the interface in the storage volume to the storage system. The control unit sets the bandwidth corresponding to a ratio of processing access to each storage volume in the storage system based on the request from the management computer, and allocates the storage volume having the bandwidth requested by the host computer set therein to the host computer to be accessed by the host computer to the allocated storage volume.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques.

Abstract: A memory system includes a memory and a memory controller coupled to the memory and configured to be connected to an advanced technology attachment (ATA) host, the memory controller including a memory interface configured to access to the memory and configured to control an access cycle to the memory by the memory interface in accordance with date rate information for the ATA host. The data rate information may include an ATA transmission mode of the ATA host.

Abstract: A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data.

Abstract: A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept. The first is a method of managing a common data path among a plethora of facilities with a decentralized distributed management scheme. The second concept is a method for managing a shared data buffer or group of buffers between multitudes of facilities. By employing the concepts discussed in this invention, one can contemplate a complex dataflow consisting of a multiplicity of resources and data paths, whereby virtually any combination of sharing is possible. A single data path can be shared among multiple sources or sinks.

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain metadata therefrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

Abstract: A method for allocating data write credits for a storage device includes gathering requests for the data write credits from a plurality of data sources and assembling the plurality of data sources in a prioritized list. The method also includes removing lowest priority data sources one by one from the prioritized list until a total of the requests made by all data sources remaining in the prioritized list are within a number of available data write credits, and granting the requests for all the data sources remaining in the prioritized list.

Abstract: A method and system for protecting portable computer data from unauthorized transfer or using portable computers to download unauthorized data. The invention is applicable to any computer capable of transferring data, but in one embodiment a portable computer is described. Authorization is enabled by an interface permitting synchronization of the portable computer with a host computer by authentication of the particular portable computer identity. For instance, in one embodiment, when a portable computer is docked with a compatible interface connected to a host desktop computer, it is sensed and identified by the interface. If the particular portable computer identity is authenticated as authorized for that desktop, then synchronization will be enabled by the interface. The computers may then transfer data. However, if the identity is not an authorized one, then authentication will not occur, synchronization is correspondingly disabled, and data transfer is prevented.

Abstract: A method, system, application programming interface, computer system, and computer program product to provide locks for controlling access to data by nodes in a multi-node environment while minimizing messages sent between nodes. Based upon knowledge of lock usage in the multi-node environment, a multi-node knowledge agent can determine when no other node is accessing data protected by a given lock, as well as when an event has occurred that precedes a request by another node to access data protected by the given lock. When no other node is accessing data and no such event has occurred, the multi-node knowledge agent can designate that given lock as “masterless.” A lock agent on the node hosting the multi-node knowledge agent is authorized to subsequently grant access to the data protected by the masterless lock to clients on that node without communicating with a lock master, which may reside at another node.

Abstract: The present invention is a DMA controller that accesses a transfer source and a transfer destination of a DMA transfer via a bus, that chains a plurality of data segments in the transfer source according to an instruction by an external initiator, and that performs burst-transfer to the transfer destination, and when a boundary data, that is a remaining data after dividing in the bus width units and data less than the bus width, is generated, the boundary data is stored in a boundary data buffer in the DMA controller, the data to be read from the transfer source by the next DMA command and the previously stored boundary data are merged, and the data is burst-transferred to the transfer destination.

Abstract: The present invention suppresses the generation of redundant I/O and improves the response to the host during data migration. When migrating data from the migration source volume to the migration destination volume, the access destination of the host is switched to the second storage device. When data requested by the host has not yet been migrated, data is read from the first storage device. When the frequency of access to the non-migrated area reaches a prescribed value, the target IP address is changed and discovery is implemented so as to switch the access destination of the host to the first storage device. When the frequency of access to the migrated area in the first storage device reaches a prescribed value, the access destination of the host is switched to the second storage device. The access destination of the host is controlled based on the data migration state and access state, and the generation of redundant I/O can be suppressed.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous log-in (steps S210 and S212). In the case of an affirmative answer, the management agent ME1 reads an ordinal number of precedence ‘n’ allocated to a GUID of the initiator of interest from a queue (step S213) and reads a time constant mapped to the input ordinal number of precedence ‘n’ from a time constant table (step S214). The management agent ME1 subsequently sends a status packet, which includes a log-in error status and the time constant, to the initiator of interest (step S216). The initiator of interest receives the status packet, reads the time constant included in the input status packet, and outputs another request of log-in to the target T1 at a timing specified by the time constant.

Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data.

Abstract: Remotely obtaining exclusive control of a device by remotely establishing communication with the device over a network, requesting to obtain remote exclusive control of the device's capabilities, and determining whether remote exclusive control of the device's capabilities can be obtained based on whether or not another user already has exclusive control of the device's capabilities. In a first case where it is determined that remote exclusive control can be obtained, authenticating a user requesting to obtain remote exclusive control of the device's capabilities, providing the user remote exclusive control of the device's capabilities after the user has been authenticated, and temporarily deferring requests by users other than the user who has obtained remote exclusive control to perform operations utilizing the device's capabilities during a period in which the user maintains remote exclusive control of the device's capabilities.

Abstract: A system, method and computer program product for analyzing file I/O activity on local attached storage devices within a computer network is provided. In an embodiment, a software agent executes on one or more servers within the network, and monitors the I/O activity on the network's local attached storage (e.g., SAN, NAS, and IDE and SCSI disks). A management interface is also provided for monitoring I/O activity-related data and for receiving reports on such I/O activity. In an embodiment, collected I/O-related data and any predefined I/O metrics are stored in a central repository (e.g., a relational database). The system, method and computer program product provide accurate metrics to assists system administrators in deciding, justifying and validating resource purchases for and allocations within the network.

Abstract: Methods and apparatus for producing an electronic ID number include modifying at least one physical bit element from among each of at least first and second groups of physical bit elements, each physical bit element of each group having a first physical state in which it is operable to produce a signal having a first electrical state, and being capable of permanent modification to a second physical state in which it is operable to produce a signal having a second electrical state; and producing (i) one bit of an identification (ID) number from the respective signals issuing from each of the respective at least first and second groups of physical bit elements, and (ii) a validity signal indicative of whether the one bit of the ID number is valid.

Abstract: A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data into the first storage, a data transfer of the said image data from the first storage to the second storage, based on a rate of data transfer and writing of the image data into the first storage and rate of data transfer and writing of the image data into the second storage from the first storage.

Abstract: A scheduler configured to schedule multiple channels of a Direct Memory Access (DMA) device includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also includes a weight that is determined based on these multiple fields. The scheduler also includes a comparison-logic circuit that is configured to then sort the entries based on their respective weights.

Abstract: Techniques for utilizing a time-to-live timeout on a logical connection to a resource (e.g., a database) from a cache are provided. When a logical connection to the resource is obtained, a timeout is set specifying the amount of time the logical connection can be utilized. If the timeout expires, the logical connection is closed and the underlying physical connection can be returned to the cache.

Abstract: Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be implemented in software and/or hardware, monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

Abstract: An address region of an internal bus wherein a burst access can be utilized in an external bus is set in an address table. A DMA control unit determines whether or not a burst access can be utilized in the external bus by comparing an address in an access to the internal bus with an address region set in the address table. Then, the DMA control unit carries out a direct memory access transfer by utilizing a burst access when it is determined that the burst access can be utilized in the external bus. Accordingly, the DMA control unit can carry out a DMA transfer by using a burst access without the intervention of a FIFO memory and it becomes possible to carry out a high speed DMA transfer.

Abstract: A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.

Abstract: In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.

Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.

Abstract: The integrated circuit comprises, in addition to a first bus and a first DMA controller, a second bus and a second DMA controller that mutually connects the first bus and the second bus. A main memory is connected to the first bus, and a frame memory is connected to the second bus. By the construction, a possible conflict in data transfer as “urgent processing” and as “normal processing” can be avoided. The data transfer as “urgent processing” includes transferring image data between the frame memory and an image input device or an image display device; while the data transfer as “normal processing” includes transferring image data between the main memory and the frame memory.

Abstract: DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is operable to receive an analog input signal and convert discrete samples thereof at a predetermined sampling rate to a digital representations thereof as a plurality of digital words. A memory stores the digital words generated by the data conversion circuit. A processor is included on the integrated circuit and operable to access the memory to output select ones of the digital words for processing thereof in accordance with a predetermined processing algorithm. A memory access controller controls access to the memory by the data conversion circuit and the processor.

Abstract: A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.

Abstract: A load balancing mechanism and technique that monitors a memory interface associated with a processor resource in a processor pool associated with at least one node of a computer network. The monitoring determines the actual load activity executed by the processor during a specified period of time. The mechanism comprises a hardware access monitor configured to determine the true activity of each processor resource. The access monitor tracks certain memory requests over the memory interface and stores the requests in a counter assigned to each processor. The access monitor then collects statistics from each processor resource of the pool and provides those statistics to a central load balancing resource for use when determining assignment of loads (tasks) to the various processor resources.

Abstract: A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage device controller, calculating a bit transfer period by the storage device controller based on the time duration of the data rate synchronization pulse, serially driving a plurality of bits from the drive controller at a rate based on the bit transfer period, and sampling at the rate based on the bit transfer period to receive the plurality of bits by the storage device controller.

Abstract: A DMA controller comprises an arbitration unit for arbitrating among a plurality of channels so as to select a DMA request from among a plurality of DMA requests accepted by way of the plurality of channels according to priorities assigned to the plurality of channels in advance, and a trace buffer for storing trace data associated with the DMA request selected by the arbitration unit. The DMA controller can also include a write control unit for enabling or disabling writing of the trace data associated with the DMA request selected by the arbitration unit in the trace buffer.

Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Abstract: A control system includes a programmable controller having a CPU unit that carries out cyclic operations of processes. An additional temporary user memory is provided in addition to a regular user memory. When an on-line editing of a user program is to be carried out, the program is stored in both memories and the program stored in the temporary memory is called by an instruction execution engine to be executed. After the on-line editing is completed on the user program stored in the user memory, the program execution is based on the edited user program stored in the user memory.

Abstract: A System for providing data security in a first device driver operably installed in a computer operating system having a layered plurality of device drivers (81, 82, 83, 84) for accessing data in a data storage device. The first device driver detects an I/O request, and determines whether the first device driver is functionally uppermost in the layered plurality of device drivers. If the first device driver is functionally uppermost in the layered plurality of device drivers, the method performs the I/O request (80) in the first device driver. If the device driver is not functionally uppermost in the layered plurality of device drivers, the method denies the I/O request in the first device driver, and allows the I/O request to be performed by the next lowest-level driver in the layered plurality of device drivers.

Abstract: A distributed data system may include a plurality of nodes one or more of which may include at least one multi-threaded process operable to access portions of distributed data. A lock mechanism may grant locks to the multi-threaded processes for portions of the distributed data. Only a process holding a lock may access a portion corresponding to the lock. Threads of other processes may not access the portion. A process may include a lock management thread pool dedicated to managing locks for portions of the distributed data for access by other threads of the process. Each lock management thread of the lock management thread pool may request a lock for a portion of distributed data on behalf of the process. The process may hold one or more locks for portions of distributed data corresponding to one or more lock management threads of the lock management thread pool.

Abstract: A method for accessing I/O devices in embedded control environments is provided, wherein said I/O devices are remotely attached to an embedded microprocessor. By mapping said I/O devices' resources to said microprocessor's address or memory address space, existing device drivers can be reused and the time-to-market capability is greatly improved.

Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

Abstract: A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous log-in (steps S210 and S212). In the case of an affirmative answer, the management agent ME1 reads an ordinal number of precedence ‘n’ allocated to a GUID of the initiator of interest from a queue (step S213) and reads a time constant mapped to the input ordinal number of precedence ‘n’ from a time constant table (step S214). The management agent ME1 subsequently sends a status packet, which includes a log-in error status and the time constant, to the initiator of interest (step S216). The initiator of interest receives the status packet, reads the time constant included in the input status packet, and outputs another request of log-in to the target T1 at a timing specified by the time constant.

Abstract: A method and system for tracking data packets that utilizes a tree data structure with a recursive pruning algorithm that collapses the branches of the tree that represent contiguous ranges or regions to maintain a minimally optimum memory size. Each contiguous region is identified by a node, which includes the start and end range of packets. Each node further includes left and right pointer elements, which point to adjacent lower and higher nodes, respectively. When a packet sequence number is not contiguous with any other sequence numbers previously received, a new node is created that contains only a single value range. When a new packet is received that has a contiguous sequence number (i.e., immediately preceding or succeeding sequence number), the original node is updated so as to reflect the new contiguous range. Additionally, if this new contiguous range is contiguous with another node's range, the two nodes are “collapsed” into a new single node containing the new expanded contiguous range.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first deice when it is determined that the first device should release the bus.