Abstract: Methods and apparatus apparatuses to transfer data between a first device and a second device are disclosed. In various embodiments, an apparatus includes a first device and a second device. The first device includes at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device includes at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel. Other methods and apparatuses are disclosed.

Abstract: A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However, there may not be any unallocated MSI resource remaining in the PHB. Instead, a hypervisor may request to borrow MSI resources assigned to other PCI functions in the system. For example, the PCI function requesting the additional MSI resources may ask for a certain number of MSI resources for a certain period of time—e.g., a lease. The hypervisor then determines which of the other PCI functions (referred to as a loaning PCI functions) are willing to lend or loan their MSI resources. Once the MSI resources available for lease are known, the hypervisor informs the requesting PCI function of these resources which, in turn, binds the additional MSI resources to the I/O device.

Abstract: A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However, there may not be any unallocated MSI resource remaining in the PHB. Instead, a hypervisor may request to borrow MSI resources assigned to other PCI functions in the system. For example, the PCI function requesting the additional MSI resources may ask for a certain number of MSI resources for a certain period of time—e.g., a lease. The hypervisor then determines which of the other PCI functions (referred to as a loaning PCI functions) are willing to lend or loan their MSI resources. Once the MSI resources available for lease are known, the hypervisor informs the requesting PCI function of these resources which, in turn, binds the additional MSI resources to the I/O device.

Abstract: An method of configuring an electronic device having a plurality of serial ports, each of which is configurable to act in either a host port or a slave port mode, includes entering a port configuration state at the device, and, in this port configuration state detecting a trigger event and configuring each of the serial ports of the device in a defined one of its host port or slave port modes. The trigger event may be the proximity of one of the serial ports of the electronic device to a port of another external device in its slave mode. In response, the proximate serial port of the electronic device may assume its host port mode, and the remaining serial ports of said electronic device may assume the slave port mode.

Abstract: Virtualizing a host USB adapter in a virtualized environment maintained by a hypervisor, the hypervisor administering one or more logical partitions, where virtualizing includes receiving, by the hypervisor from a logical partition via a logical USB adapter, a USB Input/Output (‘I/O’) request, the logical USB adapter associated with a USB device coupled to the host USB adapter; placing, by the hypervisor, a work queue element (‘WQE’) in a queue of a queue pair associated with the logical USB adapter; and administering, by an interface device in dependence upon the WQE, USB data communications among the logical partition and the USB device including retrieving, with direct memory access (‘DMA’), USB data originating at the USB device from the host USB adapter into a dedicated memory region for the logical USB adapter.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: To provide a semiconductor device and a mobile terminal device capable of operating with stability. A semiconductor device includes an HSIC physical layer circuit fixedly connected to another semiconductor device through a bus line, a USB link control unit that operates with either a USB host function or a USB device function, and link-connects to the another semiconductor device, a nonvolatile storage unit that stores selection data, the selection data being used to select the USB function with which the USB link control unit operates, and a semiconductor substrate on which the HSCI physical control unit, the USB link control unit, and the nonvolatile storage unit are formed.

Abstract: A method and apparatus for communicating USB data. In one embodiment, the method comprises receiving, by an optimizer executing on a computer and communicatively coupled between a USB storage driver (USBSD) and a USB hub controller driver (UHCD), an SCSI command; transmitting, by the optimizer in response to receiving the SCSI command, the SCSI command to the UHCD; generating, by the optimizer, an SCSI command completion; transmitting, by the optimizer, the SCSI command completion to the USBSD; receiving, by the optimizer, SCSI data associated with the SCSI command completion; transmitting, by the optimizer in response to receiving the SCSI data, the SCSI data to the UHCD; generating, by the optimizer after transmitting the SCSI data, an optimized SCSI status message; transmitting, by the optimizer, the optimized SCSI status message to the UHCD; and transmitting, by the optimizer responsive to an SCSI status completion, the SCSI Status completion to the USBSD.

Abstract: A system for optimizing communication paths between two given network ports. More specifically, the system for optimizing communication paths identifies an optimal port between a multi-ported target node and a multi-ported initiator node and then couples the multi-ported target node and the multi-ported initiator node using an optimal path corresponding to the identified optimal port.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: Methods and structure for coordinating between Redundant Array of Independent Disks (RAID) storage controllers are provided. An exemplary system includes a RAID controller. The RAID controller includes a Peripheral Component Interconnect Express (PCIe) interface, a Serial Attached Small Computer System Interface (SAS) port operable to communicate with another RAID controller, and a command unit. The command unit is able to direct the interface to contact another PCIe interface at the other controller, to acquire an identifier of the other controller stored in a PCIe Inbound Map (PIM) for the other interface, and to activate a feature for the controller that enables cooperative management of storage devices between the controller and the other controller, if the identifier of the other controller matches discovery information maintained at the controller.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: A system for sharing a USB Key by multiple virtual machines located at different hosts including at least two virtual machine managers, each virtual machine manager including a virtual machine transceiver module which is configured to receive a request for accessing a USB Key from a virtual machine within its host; a storage module which is configured to store an association relationship between a USB Key and the virtual machine authenticated by the USB Key; a verification module which is configured to, in response to judging that the virtual machine of the received request can access the USB Key, transmit the request for accessing the USB Key to a USB Key transceiver module of a virtual machine manager of the host where the USB Key is located; and a USB Key transceiver module which is configured to receive a request for accessing a USB Key, and to transmit an access request to a connected USB Key.

Abstract: A universal serial interface (USI) includes two transceivers configured to separately support a plurality of serial communication standards; a buffer configured to store received data and data to be transmitted; and a transceiver controller configured to connect one of the two transceivers to the buffer based on a configuration signal received from outside of the USI.

Abstract: A communication control system includes a first computer and a second computer, wherein the first computer includes a communication interface device and a first processor configured to control the communication interface device to transmit first data and first feature information indicating a feature of the first data to the second computer, and the second computer includes a memory that has a storage area allocated to store second data received from the first computer, and a second processor configured to determine whether the first feature information received from the first computer matches second feature information, indicating a feature of and calculated based on the second data stored in the storage area, and control the memory to release the storage area when the second feature information does not match the received first feature information.

Abstract: One or more techniques and/or systems are provided for detecting misalignment between a virtual data format and an underlying data format. A virtual data object, such as a virtual machine, may be stored within a storage device using an underlying data format. The virtual data object may comprise one or more virtual data structures, such as a virtual partition. The virtual partition may be stored within the virtual data object according to a virtual data format. The virtual data format may be compared with the underlying data format to determine whether the virtual data structure is misaligned within the storage device. Such misalignment may lead to virtual data blocks of the virtual data structure overlapping underlying data blocks, which may degrade (e.g., I/O) performance. Accordingly, one or more misaligned virtual data structures may be realigned within the storage device to address misalignment and/or improve performance.

Abstract: This invention is directed to reducing power consumption even when there is a great amount of power consumed by a root complex in a printing apparatus that employs a PCI Express architecture. To accomplish this, a printing apparatus that includes a controller capable of switching between a root complex and an endpoint and an accelerator controller serving as a root complex performs the following processing. More specifically, in the power saving mode, the power source of the accelerator controller is turned off and the controller is set as a root complex. Power consumption in the power saving mode can be greatly reduced, and a return sequence from the power saving mode can be executed.

Abstract: A method is provided for use in a system that includes a host computing machine configured to implement a virtualization intermediary and that includes a physical storage adapter, the configures a virtual machine (VM) and a virtual function (VF) to support IO operations to physical storage through a direct IOV path to the VF of the physical storage adapter, the method comprises: creating by the virtualization intermediary mapping information that includes a first mapping between virtual disks and physical regions of physical storage and that includes a second mapping between virtual disks and virtual disk addresses; transmitting the mapping information from the virtualization intermediary over the physical storage adapter from a physical function (PF) of the physical storage adapter to the VF; associating a virtual port with the mapping information within the virtualization intermediary; binding the virtual port to the VF; communicating virtual disk addresses indicated within the second mapping within the tra

Abstract: Methods, systems, and devices are disclosed for wireless communication over unlicensed spectrum using a femto cell. In an implementation of the system, a dualmode mobile device adapted to communicate over a licensed frequency spectrum and over an unlicensed frequency spectrum is provided. The dual-mode mobile device detects the presence of a femto cell communicating over an unlicensed spectrum and in response, initiates a communication connection with the unlicensed spectrum femto cell. Subsequently, the connection over a license spectrum may be disconnected upon successful establishment of the connection over the unlicensed spectrum. In yet another implementation, a femto cell communicating over an unlicensed spectrum may be adapted to communicate with a mobile switching center and/or with a voice over IP switch.

Abstract: A control circuit (comprising, for example, a part of a charging hub for a portable electronic communications device) that is not configured to support USB On-The-Go-compatible Host Negotiation Protocol is operably coupled to a USB-ID connector and is configured to transmit an identifier via that USB-ID connector to prompt a USB device in function mode to serve as a USB host. A locally-available power supply can then serve to provide power to that USB device notwithstanding the latter's role as the host.

Abstract: A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.

Abstract: An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage.

Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Abstract: Methods and apparatus that enable and optimize the simultaneous operation of several wireless femtocells having overlapping coverage areas. In one embodiment of the invention, a resource allocation (e.g., time-frequency grid for an OFDM or TDMA based wireless network) governs the simultaneous operation of several femtocells with overlapping coverage areas by specifying uses for resources. A resource allocation unit (RAU) entity is disclosed for managing and modifying resource allocations for femtocells. The community of femtocells can flexibly share resources according to the time-frequency grid, thereby maximizing spectral efficiency without requiring substantial network overhead.

Abstract: Methods and apparatus for integrating ARM-based IPs in computer system employing PCI-based fabrics. An PCI-based fabric is operatively coupled to an ARM-based ecosystem employing an ARM-based fabric such as OCP, AHB, or BVCI via a corresponding fabric-to-fabric bridge. Transactions between IP operatively coupled to the PCI-based fabric and IP in the ARM-based ecosystem are facilitated by applying applicable ordering and conversions operations via the fabric-to-fabric bridge and/or fabrics. For example, posted writes originating from IP coupled to the PCI-based fabric are converted to non-posted writes and serialized via the fabric-to-fabric bridge and forwarded to the ARM-based ecosystem.

Abstract: Methods and systems are disclosed herein for providing a universal PCIe port. The same port can be configured to accept a PCIe component as a host or an endpoint (device) symmetrically. The PCIe port can be connected to the host interface or the root complex interface if the PCIe connection is to be configured as a host or an endpoint, respectively. A virtual topology can be provided for a host that associates the host with corresponding endpoints. A mapping between virtual addresses of the corresponding endpoints in the virtual topology and local addresses of the corresponding endpoints is provided.

Abstract: A computing system can include a memory controller and a first storage device. The first storage device is to receive a serially encoded request and forward the serially encoded request to a second storage device before deserializing the serially encoded request. The first storage device is also to return a training sequence from the target storage device to the memory controller. The first storage device is additionally to return a response from the target storage device to the memory controller.

Abstract: A method for selecting an internal circuit according to a USB interface status includes: connecting a first pin of a USB interface of a terminal to a power supply through a pull-up resistor, where the first pin is a D? or D+ pin; when detecting that an external USB device is inserted into the USB interface, detecting whether the level status of the first pin is high or low; if the level status is low, connecting the D? and D+ pins to corresponding pins of a USB data communication module of the terminal and controlling charging of the terminal according to a first policy; if the level status is high, determining whether the level statuses of the D? and D+ pins are consistent, and if consistent, controlling charging of the terminal according to a second policy; if inconsistent, controlling charging of the terminal according to a third policy.

Abstract: A method for preconfiguring an appliance having a configuration memory configured to have information written to it when the appliance is in a deactivated state, wherein the appliance is configured to make contact with at least one further appliance during operation, includes capturing a data record from the appliance, wherein the data record contains at least identification data from the appliance. The method further includes determining a piece of configuration information from the appliance by using the data record and at least one data record from the at least one further appliance, and writing the configuration information to the configuration memory of the appliance in order to preconfigure the appliance.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency.

Abstract: A MicroTCA system is disclosed that includes an MCH, a clock card connected with the MCH, and multiple AMCs. The clock card includes a clock selecting unit, configured to select and output a clock source and a phase-lock unit, configured to generate a system synchronization clock according to the clock source selected by the clock selecting unit of the clock card. The MCH includes a clock drive unit, configured to drive the system synchronization clock generated by the clock card to multiple AMCs connected with the MCH. A clock card, a cascaded MicroTCA carrier, and a method for providing a clock are also provided. In this way, the implementation of the MicroTCA clock system is simplified, and the whole configuration cost of multiple cascaded MicroTCA carriers is reduced.

Abstract: A computer system includes USB class protocol-aware modules for USB devices as part of a xHCI host controller. The protocol-aware modules serve as accelerators by implementing critical portions of the device class protocols, which includes fetching higher level protocol data directly from client buffers for transmission and delivering decoded data to client buffers on receipt; and emulating a register-based interface for the benefit of system software on the host computer.

Abstract: Management of data communication between a peripheral device and host computer system is provided. A peripheral device exposes to a host computer system multiple interfaces for data communication between the peripheral device and the host computer system. The multiple interfaces are exposed over a single physical interface between the peripheral device and the host computer system, for communicating data between the peripheral device and multiple applications executing on the host computer system. The multiple interfaces can include a data collection interface facilitating collection of data from the peripheral device by an application of the multiple applications executing on the host computer system.

Abstract: A method and apparatus for controlling sparse refresh of a self-refreshing display device coupled to a graphics controller are disclosed. The display device includes capabilities to drive the display based on video signals generated from a local frame buffer. The graphics controller may optimally be placed in one or more power-saving states when the display device is operating in a panel self-refresh mode. When exiting the power-saving state to update the image displayed by the display device, a fast-resume initialization routine may be run to reconfigure the GPU when operating in a sparse refresh mode, i.e., where the image being displayed on the display device is updated infrequently. In such cases, the graphics controller may be configured to receive instructions and data from a central processing unit via an alternative low-bandwidth communications path instead of the high-bandwidth communications path used in normal operation.

Abstract: The present invention discloses an Ethernet base, a network system, and a data forwarding method. The Ethernet base receives service data which is in a USB format and sent by a 3G router, and after converting the service data in the USB format into service data in an Ethernet format, sends the service data in the Ethernet format to a fixed network router. The Ethernet base further performs software configuration on its USB unit, so as to enable the USB unit to fulfill a hardware time sequence function of a USB host device. According to embodiments of the present invention, network traffic of the 3G router can be switched to the fixed network router without modifying basic architecture of the 3G router; and a USB interface of the Ethernet base supports charging the 3G router simultaneously in a process of data transmission.

Abstract: Present disclosure relates to a computer-implemented method for handling two SES sidebands using one SMBUS controller. The method includes one or more of following operations: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data from host computer for monitoring and controlling at least one drive of first and second group of drives, (c) determining address and device number of drive to which received control commands and control data are directed, (d) forwarding control commands and control data to first or second SMBUS sideband handler based on address received, (e) controlling the blinking of the LEDs of the drive by first or second SMBUS sideband handler, (f) generating responses by the first or second SMBUS sideband handler, (g) receiving responses by the SMBUS controller, and (h) sending the responses back to the host computer within a predetermined time period.

Abstract: A peripheral component interface-express (PCI-E) standard selection setting system and microserver are disclosed, in which a selection controller selects an arrangement setting in storage elements to arrange the PCI-E control chip, whereby each of the second PCI-E standard ports is or is not arranged as an upstream PCI-E standard port, so that a single PCI-E standard control chip may arrange one of the multitude of PCI-E standard ports as an upstream PCI-E standard port, so that the upstream PCI-E standard port may have a data transmission with one of the multitude of system on chips (SOCs) connected with the PCI-E standard control chip.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: Certain embodiments of the present disclosure are directed to a baseboard management controller (BMC) that includes a PCI express (PCIe) interface controller configured to provide access to a PCIe channel over a PCIe link, and firmware. The firmware includes a PCIe module being configured to access the PCIe channel through the PCIe interface controller and registered as a PCIe function. A software stack of the BMC communicates, through the PCIe module, with a PCIe device over the PCIe channel.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: An apparatus and method of emulating a hardware accelerator engine over an interconnect link such as PCI Express (PCIe) link. In one embodiment, the accelerator emulation mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The accelerator emulation mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command.

Abstract: Provided is a PLC data log module and method for storing data in the same, wherein, in a case one or more storages among a plurality of outside storages is attached, a log data is stored in the attached outside storage, the log data is stored in the storage and check is made as to whether the log data is normally stored in the attached outside storage.

Abstract: A serial transmission device includes a transmitting unit that transmits data, a receiving unit that receives the data, and a plurality of serial transmission paths that connect the transmitting unit with the receiving unit and are used to transmit data. The receiving unit includes an inter-lane skew information generation unit that generates inter-lane skew information about skew of each of the serial transmission paths and transmits the generated inter-lane skew information to the transmitting unit. The transmitting unit includes a data conversion rule generation unit that generates a conversion rule used to determine distribution of the data to each of the serial transmission paths based on the inter-lane skew information.

Abstract: The USB device (e.g. an audio class device) comprises a USB bus interface that connects to an upstream USB port and a USB logical device that provides first USB endpoints for upstream communication on a first channel. The USB host comprises a USB host controller that connects to a downstream USB port, and a USB driver that provides second USB endpoints for downstream communication on a second channel; wherein the USB host operates concurrently with the USB device. The processor is configured to communicate data between the first channel and the second channel via the first USB endpoints and the second USB endpoints, respectively.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: Described herein are embodiments of USB device control using endpoint type detection during enumeration. An apparatus configured for USB device control using endpoint type detection during enumeration may include a host controller configured to selectively disable enumeration of a USB device based at least in part on an endpoint type of the USB device. The apparatus may include a management engine configured to store in the host controller a USB lock policy defining endpoint types disallowed to be enumerated by the apparatus. Other embodiments may be described and/or claimed.

Abstract: A method for detecting a receive end, a detection circuit, an optical module, and a system are provided, and relate to the field of optical communications. The method includes: transmitting a first detection code pattern to a PCI-E receive end through optical transmission, so that after receiving the first detection code pattern, the PCI-E receive end feeds back a second detection code pattern through the optical transmission; detecting whether the second detection code pattern fed back by the PCI-E receive end through the optical transmission is received; and determining that the PCI-E receive end is in position if a detection result is that the second detection code pattern fed back by the PCI-E receive end through the optical transmission is received.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: A serial attached SCSI (SAS) system may include a host bus adaptor, a bus expander, and a multi-layer data transmission medium coupled between the host bus adaptor and the bus expander. The multi-layer data transmission medium may include a first microstrip structure located at a top surface portion of the multi-layer data transmission medium and a first stripline structure located within a first internal portion of the multi-layer data transmission medium. The microstrip structure provides, among other things, a repeaterless high-speed serial communications link between the host bus adaptor and the bus expander.