Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.

Abstract: In some embodiments a method is disclosed that includes creating a network connection status between a host device and a peripheral network device, determining characteristics of the peripheral device such as receive capacity or a quality of service classification for the transmission and flow control for performing control and data transfers. A transfer is initiated when a uniform serial bus request block (URB) is generated by a host application. The URB can have parameters that can be utilized to generate a transaction over a wireless network providing Quality of Service (QoS) guarantees. Other embodiments are also disclosed.

Abstract: A multifunctional mobile telephone handset is connected to a PC using a Universal Serial Bus. During bus enumeration, a device class descriptor is returned by the handset to the PC. The PC's operating system receives information relating to one of the functions of the handset and assigns an appropriate device driver.

Abstract: In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system.

Abstract: Various techniques are provided to facilitate the identification of devices, such as high performance data communication devices, when such devices are connected over a data communication bus. In one example, high performance devices may identify each other by providing frequency modulated signal bursts which fall within a range of frequencies associated with a data communication standard. Similarly-implemented high performance devices may recognize patterns encoded in the frequency modulations of the signal bursts and thereby identify each other. Advantageously, while providing the frequency modulated signal bursts, the high performance devices may remain compliant with the data communication standard to facilitate communication with other types of devices which may expect to receive communications in accordance with the data communication standard.

Abstract: A cable dock assembly can include a first sub-assembly including a power adapter configured to attach to a power source, a second sub-assembly including a first video display plug configured to attach to a first video display, a third sub-assembly including a universal serial bus plug configured to attach to a computing device placed on a surface, a first electrical cable attached at the first sub-assembly and the second sub-assembly, a second electrical cable attached at the second sub-assembly and the third sub-assembly, and one or more controller chips. The one or more controller chips can be fully contained within at least one of the first, second, or third sub-assemblies. Other related assemblies and methods are also provided.

Abstract: Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

Abstract: A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network.

Abstract: Embodiments disclosed herein include operating the M-PHY communications over peripheral component interconnect (PCI)-based interfaces. Related cables, connectors, systems, and methods are also disclosed. In particular, embodiments disclosed herein take the M-PHY standard compliant signals and direct them through a PCI compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having PCI connectors to communicate.

Abstract: A serial attached SCSI (SAS) system may include a host bus adaptor, a bus expander, and a multi-layer data transmission medium coupled between the host bus adaptor and the bus expander. The multi-layer data transmission medium may include a first microstrip structure located at a top surface portion of the multi-layer data transmission medium and a first stripline structure located within a first internal portion of the multi-layer data transmission medium. The microstrip structure provides, among other things, a repeaterless high-speed serial communications link between the host bus adaptor and the bus expander.

Abstract: A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.

Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.

Abstract: The present invention provides a system and method for interfacing between a terminal and a smart card embedded within smart card, and a Universal Subscriber Identification Module (USIM), and a smart card applied to the same. That is, the execution procedure of a service application in the smart card is defined using a new interface between the terminal and the smart card by providing construction of a smart card equipped with one or more service applications, executing the special service application according to the request of the terminal, providing an output value according to the execution of the special application to the terminal, and requesting a special I/O device.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

Abstract: An external storage device comprises a plurality of hard disks, a control unit, a bridging unit, a connecting port and a voltage converter circuit. The control unit is coupled to the hard disks and ingrates the hard disks into a redundant array of inexpensive disks. The bridging unit is coupled to the control unit. The connecting port is coupled to the hard disks. The voltage converter circuit is coupled to the control unit and the bridging unit. The external storage device receives a power supplied from an electronic device through a transmission line. The power through the connecting port is transmitted directly to the hard disks in order to drive the hard disks. The voltage converter circuit converts the power and supplies the power to the control unit and the bridging unit. It is convenient for user to disconnect an extra power supply apparatus and a voltage transformer.

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract: A transmission device includes a plurality of transmitting units that transmit data to an opposing device via different paths, a determining unit that compares a first speed of an operation clock for the opposing device with a second speed of an operation clock for the transmission device, and an inserting unit that inserts, when the first speed is same as the second speed, first difference absorbing data that has a predetermined data length into the data to be transmitted by the transmitting units, that inserts, when the first speed is higher, second difference absorbing data that has a data length smaller than the predetermined data length into the data, and that inserts, when the second speed is higher, third difference absorbing data that has a data length greater than the predetermined data length into the data.

Abstract: A SAS expander forms a first path coupling the SAS initiator and a first port of a SAS target together. The first SAS expander notifies the SAS initiator of a virtual expander address instead of a SAS address of the first SAS expander. The first SAS expander notifies the SAS initiator of a virtual target port address, at least instead of a SAS address of the first port of the SAS target. A second SAS expander forms a second path coupling the SAS initiator and a second port of the SAS target together. The second SAS expander notifies the SAS initiator of the virtual expander address instead of a SAS address of the second SAS expander. The second SAS expander notifies the SAS initiator of the virtual target port address, at least instead of a SAS address of the second port of the SAS target.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, causing corrupted data.

Abstract: A computer peripheral device, which is adapted to a computer system having a system-end connecting interface, includes a device-end connecting interface, an impedance unit and a control unit. The device-end connecting interface includes a power pin and a ground drain pin. The power pin electrically connects to a power source of the computer system and generates a voltage level on the ground drain pin. The impedance unit electrically connects to the power pin and ground drain pin of the device-end connecting interface respectively and decreases the voltage level of the ground drain pin optionally. The control unit electrically connects to the ground drain pin of the device-end connecting interface and determines a USB specification of the system-end connecting interface according to the voltage level of the ground drain pin.

Abstract: The present disclosure provides a host electronic device including a main operating circuit, a first peripheral bus, an interface circuit, a second peripheral bus, and a conversion device. The interface circuit is coupled between the second peripheral bus and a host computer for receiving an external command form the host computer through a transmission protocol compatible with a first interface. The conversion device is coupled between the first and the second peripheral bus including an external virtual adapter, an internal virtual adapter, and a network channel. Furthermore, the conversion device encodes and decodes the external command, and produces a decoded external command. A processor of the main operating circuit executes the decoded external command, such that the main operating circuit implements a corresponding operation.

Abstract: Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.

Abstract: Provided is a semiconductor storage device having a first interface section meeting a USB standard for connection to host equipment, a NAND memory section that is a first semiconductor memory section, a second interface section to which small memory cards can be connected, each small memory card having a second semiconductor memory section, and a controller capable of controlling the NAND memory section and the second semiconductor memory sections by one linear address.

Abstract: A system and method for extending the USB VBUS power signal. A system for extending the USB VBUS power signal includes at least one PCA board. The system includes a USB host. The USB host outputs a new power signal compliant with USB VBUS power signal requirements. The VBUS signal may be connected to a voltage converter to change the voltage level to a desired enable signal for the voltage supply at the receiving end of the system. The VBUS signal may be connected to logic to change the polarity of the enable signal. The enable signal is routed across traces on the one or more PCA boards. A voltage supply is located on a PCA board and receives the enable signal. The enable signal causes the voltage supply to output a new power signal that is compliant with USB VBUS power signal requirements.

Abstract: A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability.

Abstract: Physical monitoring systems are disclosed which may include a platform interface between a platform device and a monitoring module. The platform interface may allow physiological information from a patient such as sensor signal data, physiological trend data, other suitable data, or combinations thereof to be communicated from the monitoring module to the platform device. The platform interface may include a connector with pins configured to receive UART communications, transmit UART communications, communicate diagnostic information, be coupled to a ground, be coupled to a serial clock, receive serial data, transmit serial data, be coupled to a regulated power supply, be coupled to an unregulated power supply, communicate using USB standard, communicate using any other suitable standards, perform any other suitable functions, or any combinations thereof.

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract: A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.

Abstract: A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.

Abstract: A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic.

Abstract: Methods, apparatus, and systems for enhancing communication between compute resources and networks in a micro-server environment. Micro-server modules configured to be installed in a server chassis include a plurality of processor subsystems coupled in communication to a shared Network Interface Controller (NIC) via PCIe links. The shared NIC includes at least one Ethernet port and a PCIe block including a shared PCIe interface having a first number of lanes. The PCIe lines between the processor sub-systems and the shared PCIe interface employ a number of lanes that is less than the first number of lanes, and during operation of the micro-server module, the shared NIC is configured to enable each processor sub-system to access the at least one Ethernet port using the PCIe link between that processor sub-system and the shared PCIe block on the shared NIC.

Abstract: A peripheral component interconnect express (PCI-E) system has a reconfigurable link architecture. The system comprises a system slot adapted to receive a PCI-E compatible system controller, a plurality of peripheral slots adapted to receive a plurality of peripheral modules, and a reconfigurable switch fabric configured to create a variable number of PCI-E links between the system slot and the plurality of peripheral slots.

Abstract: An RS-485 bus is directly connected to transportation refrigeration unit sensors for transmitting information from the sensors to a remote location and for controlling sensor parameters from the remote location. The GENSET associated with the transportation refrigeration unit also utilizes the RS-485 bus, in which the bus is directly connected to the GENSET sensors for bi-directional communication therewith.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: An expansion module including a first expansion device and at least one second expansion device is provided. The first expansion device includes a first expansion bus interface, a second expansion bus interface and at least one first peripheral device. The first expansion device is coupled to a mobile electronic device via the first expansion bus interface. The first expansion bus interface provides the first peripheral device to the mobile electronic device for use. Each of the second expansion devices includes a third expansion bus interface and at least one second peripheral device. The second peripheral device is coupled to the third expansion bus interface and coupled to the second expansion bus interface in a daisy chain via the third expansion bus interface. The first expansion bus interface and the second expansion bus interface provide the second peripheral device to the mobile electronic device via the third expansion bus interface.

Abstract: An electrical and electronic system having a control unit connected to a remotely located electrical center by way of a data bus. The electrical center includes a bus interface unit and a main printed circuit board having a plurality of control devices such as relays, which selectively activate vehicle electrical circuits based on instructions from the control unit. The bus interface unit is that of a daughter board configured to be plugged into the main board of the electrical center, such as a Local Interconnect Network (LIN) interface board, and the data bus may be a LIN bus.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit.

Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.

Abstract: Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.

Abstract: The present invention relates to a composite data transmission interface and a judgment method thereof which is based on metal contacts shared by a smart card and a universal series bus and comprise steps as follows: link a composite pin to a socket; electrical conductivity is completed with a socket linking a composite pin; a controller connected to the composite pin is activated by electricity; a smart card's or a universal series bus's electrical conductivity mode is enabled by the controller by means of the smart card's or the universal series bus's electrical connection mode.

Abstract: A data transfer device includes a serial interface including plural transmission paths and carrying out a data transfer operation with plural operating frequencies, transfer requesting units issuing a data transfer request to the serial interface, a request monitoring unit, a condition setting unit setting a set transmission path condition including at least one of a number of the transmission paths and an operating frequency used when the data transfer requests are issued to switch statuses of the data transfer requests to statuses of switching data transfer requests, a use transmission path condition determining unit determining the set transmission path condition corresponding to the status of the switching data transfer request as a use transmission path condition when the status of switching data transfer request corresponds to the status of data transfer request by comparing the statuses, and a switching unit switching to the use transmission path condition.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.

Abstract: A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Further, the system includes an embedded Universal Serial Bus (USB) host configured for receiving data transfer commands from the processor, and transferring data at high speed between a USB device on the processor and the memory medium. Moreover, a data path is provided between the embedded USB host and the first port.

Abstract: A communication connector is described that provides an increase in the number and type of communication circuits available on an electronic device without increasing the number and type of physical connectors. The communication connector electrically includes a set of inputs to couple to both a USB 2.0 connector and a HDMI connector. A set of outputs from the communication connector provides a third connector with a pin out specification compatible with a USB 3.0 connector or a PCIe connector.

Abstract: A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.