Abstract: Processing efficiency of a computer using a volume and processing efficiency of another computer using another volume corresponding to the volume can be maintained at high levels. In a computer system, a storage apparatus is able to provide a certain volume to a computer, and another storage apparatus provides data to the computer by causing a virtualization function to point to another volume from the certain volume and copying data from the other volume to the certain volume. An upper limit on the number of pages copiable from the other volume to the certain volume of the storage apparatus is set. A CPU of the other storage apparatus copies data in an amount equal to or smaller than the upper limit from a page among multiple pages of the other volume to a storage region corresponding to a page forming the certain volume of the storage apparatus.

Abstract: A method and apparatus of a network element that processes control plane data in a network element is described. In an exemplary embodiment, the network element receives network data and determines a class of the network data. The network element additionally determines that this class of the network data is to be processed. The network element further marks the network data based on at least on an existence of an indication of whether the network element had previously processed other data in the same class as the class of the network data. Furthermore, the network element queues the network data.

Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

Abstract: An information system connected to hosts and an information processing system manages a second ALU connected to the hosts via a second logical path, and second SLUs for receiving I/O requests from the hosts via the second logical path. A processor manages a first ALU connected to the hosts via a first logical path and first SLUs that receive I/O requests from the hosts via the first logical path, and builds up a first group including the first SLUs. A first SLU and a second SLU compose an HA pair, and the HA pair is provided to the hosts as one volume. The processor evaluates the state of the first logical path based on the pair state of the first SLU that composes the HA pair included in the first group so priorities with which the hosts issue I/Os to the first logical path can be determined.

Abstract: A layer 2 load balancing system includes server devices that provide virtual machines that each share a virtual Media Access Control (MAC) address. A switch device is coupled to each of the server devices via respective ports on the switch device. The switch device receives the virtual MAC address during a time period via each of the respective ports connected to the server devices and, in response, identifies a server device cluster that shares the virtual MAC address. When the switch device receive packets that are part of a packet flow and that are directed to the virtual MAC address, it then directs each of the packets that are part of the packet flow to one of the virtual machines that is provided on one of the server devices in the server device cluster.

Abstract: A driver apparatus for a differential bus is provided, having a first transistor and a fourth transistor which are connected in order to drive the bus to a dominant state, and a second transistor and a third transistor which are connected in order to drive the bus to a recessive state. The driver apparatus also comprises a collision detection circuit which is set up to detect a collision state on the bus on the basis of measurements of currents through at least one transistor of the first, second, third and fourth transistors.

Abstract: A connection device connected to an image display unit that is head-mounted includes a connector to which an image signal is input; and a connector to which an image signal is input and which is capable of outputting sensor data. The connection device further includes a setting unit that sets a selection between the image signals; and an output control unit that selects the connector for outputting the image signal by a connection unit according to the setting. The setting unit sets the image signal to be output from the connection unit when the image signal is input.

Abstract: An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

Abstract: A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.

Abstract: A method for managing traffic of a plurality of packets in a plurality of packet flows transmitted using a time-slotted interface. The packet flows traverse a plurality of switches of a transport network according to an assigned path from a source node to a destination node. The method comprises determining (202) an end-to-end latency of a plurality of packets traversing a current switch in packet flows and assigning (204) priority to packets to the packets traversing the current switch, wherein a priority value of a packet depends on the determined end-to-end latency of said packets. The method further comprises allocating (206) a time slot in an output interface of the current switch to the packet having the highest priority value among the packets competing for said time slot.

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: Embodiments of the present application provide a method, apparatus and system for processing data, the method is applicable to an electronic device, wherein the electronic device is connected to a memory card that has been formatted in a proprietary manner in advance and the memory card includes at least one cold data area. The method includes: obtaining the number CR of reads for data stored in a target cold data area C stored locally; determining whether the number CR of reads reaches a preset threshold TCR for reading failure of cold data; if the number CR of reads reaches a preset threshold TCR for reading failure of cold data, transmitting a start address and a end address of the data stored in the target cold data area C to a controller of the memory card, and initializing the number CR of reads for processing the stored data by the controller according to the start address and the end address.

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.

Abstract: At least some embodiments of invention provide a method, device and system for link management in a Virtual Machine (VM) environment. The method includes: a heartbeat handshake link is established with a VM. After the heartbeat handshake link is successfully established, Link Aggregation Control Protocol (LACP) state information of a Physical Function (PF) of a plurality of a Network Interface Cards (NICs) is acquired. The LACP state information is sent to the VM through the heartbeat handshake link.

Abstract: Embodiments for managing High-Definition Multimedia Interface (HDMI) data are provided. HDMI data is received at an HDMI connector of an HDMI device. The HDMI data received at the HDMI connector is transmitted to another HDMI connector of the HDMI device. The transmission of the HDMI data received at the HDMI connector to the other HDMI connector of the HDMI device is ceased during the receiving of the HDMI data at the HDMI connector of the HDMI device.

Abstract: A method and system for configuring a USB3 input/output port in a camera are disclosed. The method comprises responsive to an indication that a peripheral device is a non-USB3 device, remapping pins of the USB3 input/output port to a first predefined port configuration associated with an I2C protocol by remapping a RX1? pin to communicate a first I2C signal and remapping a RX1+ pin to communicate a second I2C signal, and responsive to successful authentication between the camera and the peripheral device via the I2C protocol, enabling communication with the peripheral device and remapping the pins of the USB3 input/output port to a second predefined port configuration compatible with operation of the authenticated peripheral device by remapping a TX2+ pin to communicate a first general purpose input/output signal and remapping a TX2? pin to communicate a second general purpose input/output signal.

Abstract: A server system and a method for detecting a transmission mode of the server system are provided. The storage system includes a control device and a storage back plane. The storage back plane includes a non-volatile memory module having mode information. When the control device is plugged into the storage back plane, the control device obtains the mode information of the storage back plane, determines whether the transmission mode of the control device matches the mode information, and decides whether to send a first prompt signal according to whether the transmission mode of the control device matches the mode information.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.

Abstract: A bus arrangement includes a coordinator that has a non-volatile memory; a first node that has a first serial number; a second node that has a second serial number; and a bus. The bus includes a first signal line, which couples the first node and the coordinator; a second signal line, which connects the second node to the first node; and at least one bus line, which connects the coordinator to the first and the second nodes. The coordinator is configured such that, in a configuration phase, it establishes a connection to the first node, queries the first serial number, and stores the first serial number in the non-volatile memory, and establishes a connection to the second node, queries the second serial number, and stores the second serial number in the non-volatile memory.

Abstract: Methods, systems and computer program products for automatic adjustment of video orientation are provided. A computer-implemented method may include receiving a video comprising a plurality of image frames, determining that shaking of a mobile device has occurred during recording of the video, determining a baseline alignment for the video, adjusting the video in view of the baseline alignment, and providing a user interface comprising the video player to present a preview of the adjusted video to a user on the mobile device.

Abstract: The disclosure discloses a mobile terminal, a DC-charging power source adaptor, and a charging method, where the mobile terminal detects whether two communication pins of a USB interface thereof are shorted, and if an inserted external device is a power source adaptor, then the mobile terminal communicates with the power source adaptor, so that the mobile terminal identifies automatically the type of the externally connected charging device. Also a specialized rapid charging mode is designed for a DC-charging power adaptor, so that a battery being charged routinely is DC-charged at large current using charging voltage output by the DC-charging power source adaptor, and a volt value of the charging voltage is adjusted dynamically to the varying voltage of the battery core.

Abstract: A system on-chip includes a central processing unit and a memory controller. The memory controller receives initialization information indicating an initialization address range and an initialization value from the central processing unit, determines an initialization target memory and a local initialization address range of the initialization target memory based on the initialization information, and transmits initialization data including the initialization value to the initialization target memory by a predetermined unit to initialize the local initialization address range of the initialization target memory.

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract: A storage network element discovery method and an apparatus, where the method includes broadcasting or multicasting, by a control network element, a heartbeat message to at least one storage network element, where the heartbeat message includes address information of the control network element, receiving, by the control network element, a response message returned by at least one storage network element according to the heartbeat message, and determining an accessible storage network element according to the response message, where the response message includes network parameter information of the corresponding storage network element. Therefore, in a storage array, by broadcasting or multicasting a heartbeat message and according to a reply from a storage network element, a control network element may determine a storage network element that can be accessed by the control network element.

Abstract: An embodiment of the invention may include a method, computer program product, and system for improving I/O performance in a heterogeneous storage environment. The embodiment may include storage devices of different storage device types having different I/O performances. Each of the storage devices is accessible via a SAS interface. The embodiment may include identifying a plurality of storage devices of the heterogeneous storage environment. The embodiment may include creating a table including information about identifiable storage devices and attributes. The embodiment may include separating a block I/O data stream into storage device type classes. The embodiment may include routing I/O requests of corresponding device type classes to their assigned physical lanes using the information included in the table, thereby improving the I/O performance of the heterogeneous storage environment.

Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.

Abstract: A universal serial bus (USB) hub includes an upstream port configured to be communicatively coupled to a USB host, a downstream port, and a USB hub core circuit. The circuit is configured to determine a detachment from the downstream port, determine whether a USB element has reattached to the downstream port in USB mode, and, based on a determination that the USB element has reattached to the downstream port in USB host mode, perform USB multi-host bridging for the USB host and the USB element.

Abstract: According to one embodiment, an electronic device includes a USB Type-C connector connected to a second electronic device, a processor connected to the USB Type-C connector and including four terminals outputting an image signal, and a USB controller connected to the USB Type-C connector and including two terminals outputting USB 3.x signal. The USB Type-C connector includes two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX1, RX1, TX2 and RX2 defined under the USB Type-C standard. The image signal and the USB 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX1, RX1, TX2 and RX2.

Abstract: A method of configuring a controller for communication with at least one instrument module includes electrically connecting an interface of the at least one instrument module to an interface of the controller, receiving with the controller an identification signal from the interface of the at least one instrument module through a portion of the interface of the controller, and executing with the controller a configuration program that corresponds to the identification signal to enable communication between the at least one instrument module and the controller.

Abstract: The present invention provides method and associated interface circuit for mitigating interference due to signaling of a bus between two electronic apparatuses. The method may include: via the bus mechanically compliant to a bus specification, communicating and transporting data at a nonstandard speed which is not compliant to the bus specification. The method may further include: before communicating and transporting data at the nonstandard speed, signaling via the bus at a standard speed to configure a speed switching from the standard speed to the nonstandard speed, with the standard speed compliant to the bus specification. For example, the bus specification may be USB specification, the standard speed may be 5 Gbps (SuperSpeed of USB 3.0 specification), and the nonstandard speed may be lower than the standard speed, e.g., 2.5 Gbps, which forms a spectrum notch at a frequency of wireless connection, e.g., 2.4 GHz of Wi-Fi.

Abstract: A wireless communication terminal has: a wireless module part which transmits a radio frame signal; a transmission loss information detection part which detects transmission loss information representing whether or not the radio frame signal transmitted by the wireless module part has reached a transmission destination; a collision information detection part which detects collision information representing an aspect of collision between the radio frame signal transmitted by the wireless module part and another radio frame signal; and a transmission control part which controls a transmission process executed by the wireless module part, on a basis of the transmission loss information and the collision information.

Abstract: A first set of signal carriers of a plurality of signal carriers may be determined to be faulty. The first set of signal carriers may be for transmitting a first set of respective lane signals of a plurality of lane signals. A second set of signal carriers of the plurality of signal carriers may be identified as not faulty. The second set of signal carriers may be for transmitting a second set of lane signals of the plurality of lane signals. Based on the determining and identifying, one or more of the first set of lane signals may be routed from the first set of signal carriers through a first subset of the second set of signal carriers, the routing of the one or more of the first set of lane signals may cause a bandwidth capacity to increase to a highest available bandwidth.

Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics including at least a first PCIe subfabric and a second PCIe subfabric. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit. The first PCIe subfabric is configured to enable multipath communication between a first element coupled to the first PCIe subfabric and a second element coupled to the second PCIe subfabric.

Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. Each of the plurality of PCIe subfabrics includes a managing central processing unit and a PCIe fabric switch. One or more communication paths is configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.

Abstract: Systems and methods for managing name assignments in a Fiber Channel (FC) storage arrays are provided. One example method includes receiving a port name for a slot of a controller of the FC storage array. The slot of the controller is configured to receive an FC card for providing communication between the FC storage array and an FC fabric. The method includes binding the port name to the slot of the controller, and the port name is saved to a database managed by the controller. The method further includes assigning the port name to the FC card when installed in the slot. The FC card is swappable with other FC cards, and thus other FC card will also maintain the port name of the slot.

Abstract: A processor initiates an execution of a network driver in a first node comprising a master node of a plurality of nodes in a switchless network. The network driver configures the plurality of nodes and service level in the switchless network by transmitting management datagrams from the master node, wherein the management datagrams include an attribute that allows the management datagrams to be propagated among the plurality of nodes of the switchless network without being terminated at host channel adapters of the plurality of nodes.

Abstract: A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.

Abstract: A data transfer device of a display equipment and a data transfer method are provided. The data transfer device of the display equipment includes a display panel, a first transfer connector, a second transfer connector, a configuration switch and a control unit. The first and the second transfer connector are in line with a universal serial bus (USB) protocol including a plurality of data paths. When a first electronic device is connected to the first transfer connector, the control unit separates the data paths of the first transfer connector into at least one video data path and at least one data-transferring data path dynamically. A video signal of the first electronic device is transferred to the display panel through the video data path, and the first electronic device and the second electronic device transfer data to each other through the data-transferring data path.

Abstract: There is provided a peripheral device including a multi-pole plug inserted into a jack of a jack device, the jack device including the jack, a conversion unit that converts a physical amount into an electrical signal or converts an electrical signal into a physical amount, a detection unit that detects whether the jack device is a corresponding device capable of handling multiplexed data obtained by multiplexing the electrical signal input and output to and from the conversion unit, a transmission and reception processing unit that transmits or receives the multiplexed data via a predetermined terminal of the multi-pole plug when the jack device is a corresponding device, and a function switching unit that performs assignment of an electrical function of a terminal other than the predetermined terminal of the multi-pole plug.

Abstract: A switch includes a chassis, a drive bay including a plurality of downlink switch ports that are configured to be connected to a plurality of storage devices, a plurality of uplink switch ports, and an embedded circuit for providing signal switching between the plurality of uplink switch ports and the plurality of downlink switch ports. The drive bay is disposed on a first side of the chassis, and the plurality of uplink switch ports are disposed on a second side of the chassis that is opposite to the first side of the chassis. The plurality of downlink switch ports is embedded in the drive bay.

Abstract: The present invention discloses a portable device and a method of controlling HDMI signal output therein. The portable device comprises: a microcontroller unit, a USB Type-C interface, and a plurality of analog switches. Each of the analog switches is arranged between a HDMI signal output pin of the microcontroller unit and a corresponding pin of the USB Type-C interface. The microcontroller unit is configured to detect a positive or reverse insertion direction of the USB Type-C interface, and output a corresponding control signal to the analog switch according to the difference of the insertion direction. The analog switch is configured to shift a switching direction according to the control signal so that the HDMI signal is output through a corresponding pin of the USB Type-C interface.

Abstract: A camera includes an input/out system and one or more input/output ports. The camera configures the pins of the input/output port according to a default pin configuration. The camera detects a peripheral device is connected the input/output ports and receives an identifier from the peripheral device indicating whether the peripheral device is a USB3 device or a non-USB3 device. If the peripheral device is a non-USB3 device, the camera remaps the pins to a first configuration. The camera authenticates with the peripheral device to determine if the peripheral device meets a criteria for an approved device. If the authentication is successful, the camera enables communication with the peripheral device and remaps the pins to a second configuration. If the authentication is unsuccessful, the camera disables communication with the peripheral device and remaps the pins of the input/output port to the default configuration.

Abstract: A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB PHY-layer circuit; a first switch circuit for communicating data with an upstream port through the first USB PHY-layer circuit; a second switch circuit for communicating data with a downstream port through the second USB PHY-layer circuit; a control signal transmission interface; a signal repeater circuit; and a control unit configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples the upstream MAC-layer circuit or the signal repeater circuit with the first USB PHY-layer circuit, while the second switch circuit selectively couples the downstream MAC-layer circuit or the signal repeater circuit with the second USB PHY-layer circuit.

Abstract: Example embodiments disclosed herein relate to configuring a flexible port. The configuration of a computing device is detected based on a coupling of an interface to a flexible input/output port. The flexible input/output port is configured based on the detected configuration of the computing device.

Abstract: A multiple-antenna positioning system with a single drive element, providing reduced weight and complexity over systems that have a drive element for each antenna. In certain examples, each antenna can be coupled with a rotating spindle, with each antenna spindle being coupled with a pair of link arms. By driving a single drive spindle, each of the antenna spindles in the system can be rotated by the associated pair of link arms. The link arms can have an adjustable length, such as through a turnbuckle mechanism, to reduce backlash in the system, and in some examples can apply a preload to the system. By reducing backlash, the multiple antenna positioning system can have improved responsiveness to a rotation of the single drive element, as well as improved stability of the positioning of each antenna when the drive element is held in a fixed position.

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.

Abstract: Embodiments of the present disclosure provide a method and apparatus of maintaining data consistency by receiving, when a first storage processor is in a Ready state, a request for configuration information of a storage object from a second storage processor; in response to receiving the request, setting the first storage processor to an Updating-Peer state, and sending the configuration information to the second storage processor to maintain consistency of the configuration information in the first and second storage processors; and in response to the configuration information being sent, setting the first storage processor back to the Ready state.