Abstract: Systems and methodologies for automatic quality of service (QoS) management for data network devices are provided herein. As described herein, active versus inactive interaction between a user and a network device can be identified, based on which an appropriate QoS level can be applied to the device. For example, a level of input/output (I/O) activity associated with a device can be inferred by monitoring mouse movement, touch input activity, display output activity, voice I/O activity, or the like, and a QoS configuration can be automatically selected for the device based on the inferred level of activity. As further provided herein, I/O activity monitoring and a corresponding QoS assignment can be related to an activity timer, such that a high-priority QoS setting is applied to devices for which I/O activity is identified within the timer and a low-priority QoS setting is applied to devices for which such activity is not identified.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: A Direct Memory Access (DMA) device includes a first buffer which holds a first transfer information required for a first transfer request, and a second buffer which holds a second transfer information required for a second transfer request, and a transfer request comparison circuit which determines whether or not a current transfer request, which is newly inputted, matches with the first transfer request or the second transfer request.

Abstract: A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request blocks and Arrival Times (ATs) of the DMA request signals, counting the number of priority changes of each of DMA request blocks whose priority is changed in the priority granting process, and if a DMA request signal is received from a new DMA request block, determining priorities of the DMA request blocks based on the counted the number of priority changes.

Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: Computer program products and methods for efficient handling of queued-direct input/output (QDIO) requests and completions at an adapter in communication with an I/O device are provided. A method includes accessing a queue with one or more storage block address lists (SBALs), where each SBAL includes a plurality of storage block address list entries (SBALEs) and is associated with an SLSB. The method further includes reading an SBAL count in one of the SBALEs, where the SBAL count indicates a number of the SBALs forming an I/O request to the I/O device. In response to determining that the SBAL count is greater than one, a number of the SBALs from the queue and associated SLSBs equivalent to the SBAL count are prefetched without waiting for a notification of completion of each of the SBALs forming the I/O request, and states of the associated SLSBs transition from adapter-owned to program-owned.

Abstract: A technique for user notification involves modifying a title associated with a process to include information about an event that calls for user notification. A method according to the technique may include running a process, processing an event, generating a string of characters that includes information associated with the event, and displaying the string of characters as a title associated with the process. A system constructed according to the technique may include a client, a title array, an event processing engine, and a title provisioning engine.

Abstract: A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of the plurality of IO requests. The second core may be configured to process a different one of the plurality of IO requests based on the prioritizing of the plurality of IO requests.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A system and method comprise a first buffer having a first capacity and a first threshold level adapted to store data frames having the lowest priority, a second buffer having a second capacity greater than the first capacity and a second threshold level greater than the first threshold level adapted to store data frames having a medium priority, a third buffer having a third capacity greater than the second capacity and a third threshold level greater than the second threshold level adapted to store data frames having the highest priority. The system further includes means for differentiating a data frame as having lowest, medium or highest priority and storing the data frame in the respective first, second or third buffer, and discarding the data frame in response to the first, second or third buffer reaching the respective threshold level.

Abstract: An architecture and associated methods and devices are described in which a first selectable data path may be associated with a first port operating at a first data rate, a second selectable data path may be associated with a second port operating at a second data rate, and a third selectable data path may be associated with a third port operating at a third data rate that is higher than the first data rate and the second data rate. A plurality of security engines may be included which may be configurable to provide cipher key-based security for data associated with the first port and the second port using the first selectable path and the second selectable path, respectively, and configurable to provide cipher key-based security of data associated with the third port using the third selectable data path.

Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.

Abstract: A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: A storage system including a queue corresponding to each priority level of command and an activation order control part. A command received from a host is accumulated in the queue corresponding to the specified priority. The activation order control part decides the number of activation object commands to be activated among accumulated commands, based on the priority corresponding to the queue. The activation order control part decides the activation order of the activation object commands, based on a activation object command number decided for each queue, so that the average value of logical response time of the activation object command may be shorter at the higher priority. The activation object command is activated in accordance with the decided activation order.

Abstract: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.

Abstract: A DMA transfer system includes a DMA controller having at least one channel coupled to a system bus, the DMA controller configured to perform a DMA transfer via the system bus according to a DMA transfer setting of the at least one channel, and a DMAC control unit coupled to the DMA controller, wherein the DMAC control unit includes a plurality of virtual channels configured to have respective DMA transfer settings made thereto, a virtual channel arbiter configured to select one of the plurality of virtual channels, and a DMA setting circuit configured to read a DMA transfer setting of the selected virtual channel to write the read DMA transfer setting to the at least one channel of the DMA controller.

Abstract: Disclosed is a printing apparatus including a priority identifier establishment unit. More particularly, the printing apparatus, processing an instruction designated by a priority identifier before another instruction, includes the priority identifier establishment unit that allows a priority identifier to be designated in various forms and methods. Since the priority identifier can be established in various forms and methods, the printing apparatus can achieve enhanced flexibility and effect in priority processing.

Abstract: A system includes disk storage to provide differentiated storage QoS for a plurality of IO classes. Each IO class has a plurality of applications to it. A QoS controller collects IO statistics for each application and each class. The QoS controller adaptively determines an IO class assignment for each application based at least in part on the collected IO statistics.

Abstract: The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel data connection, the microcomputer devices are coupled to one another via a standardized, serial data connection, for example, ethernet. Using functions of ethernet switches already known, a number of microcomputer devices in the system may be increased.

Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Abstract: A system and method are disclosed which may include providing a processor operable to request an ongoing processor operation DMA communication task; providing at least one data transfer device operable to request a defined-content DMA communication task; providing a memory operable to conduct DMA communication with the processor and the at least one data transfer device over at least one data bus, the DMA communication having a bandwidth; and allocating the DMA communication bandwidth between the processor operation DMA communication task and the defined-content DMA communication task.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: A cache managing unit creates a list of elements corresponding to each data block arranged based on a priority of writing data blocks to a magnetic disk apparatus, and when a group of elements corresponding to data blocks to be written to the same magnetic disk apparatus exists, provides a link connecting elements at both ends of the group. A write control unit searches, upon selecting a data block for writing, elements belonging to the list in descending order of priority, and if a link is set at an element corresponding to a data block to be written to a magnetic disk that cannot perform a writing, follows the link to search a subsequent element.

Abstract: A network apparatus is provided that is capable of requiring a reservation for an access right to a peripheral device that is not yet connected to the network apparatus from one of the terminals on a network. A server (network apparatus) may receive a reservation command and a sender identifier (ID) from one of the terminals on the network that requests to reserve an access right for a peripheral device that is not yet connected to the server. In a case where a new connection of a peripheral device is detected, the server allows the terminal identified by the sender ID that accompanied the reservation command to access the peripheral device. While the reservation is established, access to the detected peripheral device from senders other than the identified terminal is rejected.

Abstract: A data transfer control device in accordance with an exemplary aspect of the present invention includes a first communication unit that processes data transfer with a peripheral device, and a second communication unit that processes data transfer with a host device, wherein one of the first and second communication units serves as a preferential communication unit whose data transfer should have a high priority, and another of the first and second communication units serves as a non-preferential communication unit, when the data transfer is being performed in the preferential communication unit, the preferential communication unit notifies the non-preferential communication unit that the data transfer is being performed, and when the non-preferential communication unit is being notified that the data transfer is being performed from the preferential communication unit, the non-preferential communication unit puts the data transfer in the non-preferential communication unit on hold.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: A computer system with dual hosts is provided. The computer system includes a body, a first host, a second host and multiple peripheral devices. The first host and the second host are configured in the body, and the peripheral devices are coupled to the first host and the second host. When the first host starts, the peripheral devices are controlled by the first host. When the second host starts and the first host does not start, the peripheral devices are controlled by the second host.

Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

Abstract: A resending control circuit for controlling resending of data to be sent to a sending destination, includes: a writing unit for writing resending information generated corresponding to each of data to be resent and including the resending point-in-time of the data in memory; a reading unit for reading out the resending information from the memory; and a control unit for comparing resending point-in-time included in the oldest resending information of resending information stored in the memory with current point-in-time, and executing resending processing of data corresponding to the resending information according to the comparison result.

Abstract: Provided is an information processing system that communicates with a storage apparatus through a plurality of paths Pi (i=1 to n, where n is a total number of the paths), and that issues an I/O to the storage apparatus through one of the paths Pi. The information processing system sets weights Wi for the respective paths Pi; obtains an I/O issue interval di of each of the paths Pi by dividing a sum total ?Wi of the weights Wi by the weight Wi set for the path Pi; obtains I/O issue timings ti(m)of each of the paths Pi by using the following equation: ti(m)=di/C+m·di (m=0, 1, 2, . . . ) (where C is a constant); and issues the I/Os to the paths Pi in an order corresponding to the an order of the I/O issue timings ti(m) chronologically arranged.

Abstract: Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

Abstract: The invention relates to management of a plurality of I/O requests in a storage system. The host interface module is configured to receive a plurality of I/O request which includes an associated priority; create an I/O request queue for each associated priority; define a threshold value for the queue length for each of the plurality of I/O request queues; and determine if the queue length for one of the plurality of the I/O request queue corresponding to the associated priority is less than the defined threshold value for the queue length for the one of the plurality of the I/O request queues. If the queue length of the one of the plurality of I/O request queues is more than the defined threshold value for the queue then the host interface module is further configured to rejecting the I/O request and sending a queue full message; wherein the threshold value for the queue length is based on the processing rate of the I/O requests in the plurality of the I/O request queues.

Abstract: A data transfer device arranged in a node for connection in compliance with a communication standard. The data transfer device includes a request signal generation circuit for generating request signals defined by the communication standard with different levels of priority. A determination circuit determines the request signal having the highest level of priority. Priority is given to the transfer of data corresponding to the request signal determined to have the highest level of priority by the determination circuit. A top priority request signal generation unit generates a top priority request signal that differs from the request signals defined by the communication standard. The determination circuit includes a priority determination table in which the uppermost priority request signal is set to have a level of priority that is higher than the levels of priority of the plurality of existing request signals.

Abstract: A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A precharge period detecting block detects the states of precharge of the banks. A register stores data required to determine the order of priorities (data indicating whether the banks are in a precharge period, data indicating whether data communication request signals are presented). This enables the arbiter to exclude FIFO memories that are associated with banks that are not allowed to perform data communication. Efficient data communication is thus implemented between the FIFO memories and the synchronous DRAM.

Abstract: In one embodiment, the present invention includes a host controller having a cache memory to store entries each including, at least, a command header (CH) portion having data associated with a command from the host controller to one of multiple devices coupled to a port multiplier, and a physical region descriptor (PRD) portion to store address information associated with a next address for data transfer with regard to the command. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and article of manufacture for using priority to determine whether to queue an Input/Output (I/O) request directed to storage. A maximum number of concurrent requests directed to a storage is measured. The measured maximum number of concurrent requests is used to determine a threshold for a specified priority. Subsequent requests of the specified priority directed to the storage are allowed to proceed in response to determining that a current number of concurrent requests for the specified priority does not exceed the determined threshold for the specified priority. Subsequent requests directed to the storage having a priority greater than the specified priority are allowed to proceed. Subsequent requests directed to the storage having the specified priority are queued in a queue in response to determining that the current number of concurrent requests for the specified priority exceeds the overall threshold.

Abstract: Apparatus and method for command queue management of back watered requests. A selected request is released from a command queue, and further release of requests from the queue is interrupted when a total number of subsequently completed requests reaches a predetermined threshold.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of the plurality of IO requests. The second core may be configured to process a different one of the plurality of IO requests based on the prioritizing of the plurality of IO requests.

Abstract: Audio files for an audio piece are stored in cross-scene optimized manner, so that when reading out audio files for a scene entailing high utilization of a wave field synthesis system, very short memory access times are achieved, whereas for scenes not entailing such a high utilization of the wave field synthesis system, longer memory access times in turn are accepted.

Abstract: There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first and second bus. The transfer apparatus controls a transfer sequence of transaction transfers by the bridge and data transfers by the data transfer unit, in which transaction transfers by the bridge are based on bus sequencing rules and data transfers by the data transfer unit are based on a data transfer activation condition.

Abstract: A computer includes a priority storage part to store priority information which includes priority, the priority being set in advance per each of plural paths connecting a plurality of virtual servers and one or more storage devices, and per each kind of input/output command issued to the storage device by the virtual server, and a path management unit which selects a path out of the plural paths to destination of the input/output command on the basis of the kind of input/output command and the priority information and issues the input/output command to the selected path.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals received from each of a plurality of ports. The apparatus generally provides dynamic priority arbitration for the plurality of ports.

Abstract: A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.

Abstract: A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/output operation. The hurry up command can be employed in the Direct Access File System.

Abstract: A device for preventing a process collision based on plural of input signals includes an input block for receiving a first and a second input signals to thereby generates a first and a second process request signals, a collision controller for controlling the process collision in accordance with a predetermined priority, and a signal processing block for outputting a first process signal in response to the first process request signal and outputting a second process signal in response to the second process request signals. Herein, the process collision is caused one of cases when the second input signal is inputted at an activation sector of the first process signal of the first input signal, when the first input signal is inputted at an activation sector of the second process signal of the second input signal, and when the first and the second inputs are inputted concurrently.