Input/output Polling Patents (Class 710/46)
  • Patent number: 6185631
    Abstract: The present invention provides for a computer program product for use with a computer system having a main storage device in processing communication with an information transfer interface mechanism capable of coupling to a plurality of input/output devices. The computer program device comprises of a data storage element included in the main storage device having a computer usable medium with computer readable program means for receiving and retrieving data and computer readable code means for concurrently receiving multiple packets of data from said interface mechanism. It also includes computer readable code means for concurrently storing multiple packets of data concurrently in said data storage element as well as computer readable code means for storage and retrieval of multiple packets of data concurrently between said interface mechanism and said data storage element.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: February 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Daniel F. Casper, Joseph C. Elliott
  • Patent number: 6173343
    Abstract: Data processing apparatus is described comprising a processor and at least one peripheral device. The processor is arranged to service the peripheral device either in an interrupt mode in which the peripheral device is serviced in response to interrupt signals generated by the peripheral device or in a timed mode in which the peripheral device is periodically polled and serviced if required. The apparatus has a dynamic switching arrangement for switching from the interrupt mode to the timed mode depending upon conditions dynamically determined within the apparatus, at least one of said conditions being that the rate at which the peripheral device generates interrupt signals exceeds a predefined or programmable threshold frequency. The rate of polling in the timed mode is less than the threshold frequency.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: January 9, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Alexandre Delorme
  • Patent number: 6173346
    Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: January 9, 2001
    Assignee: Micron Electronics, Inc.
    Inventors: Walter August Wallach, Mehrdad Khalili, Mallikarjunan Mahalingam, John M. Reed
  • Patent number: 6161152
    Abstract: A method and apparatus for issuing a non-blocking system call to an I/O interface process, the non-blocking system call identifying a portal from an application process, and polling the portal to determine if an I/O request is complete, the I/O interface process: polling an I/O device in response to the non-blocking system call to determine if the I/O operation is complete; and indicating that the I/O operation is complete using the portal.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: December 12, 2000
    Assignee: Intel Corporation
    Inventors: Sharad K. Garg, David S. Scott, Brad R. Rullman
  • Patent number: 6122677
    Abstract: A method of configuring peer devices without the unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after a predetermined duration when the intended device fails to respond to the configuration cycle. A bit corresponding to the particular device is set in a scorecard register. The compatibility bridge responds to the configuration cycle after the watchdog time-out period.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: September 19, 2000
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 6111663
    Abstract: A closed-loop communication system includes a closed-loop communication link with a shared communication channel. A set of communication devices are connected to the closed-loop communication link. Each communication device has un-arbitrated access to the shared communication channel. A responding modem connected to the closed-loop communication link includes a modem signal detection circuit to identify a modem signal on the closed-loop communication link and respond to it by facilitating a squelch disable signal. A transmission squelch circuit squelchs all transmission signals from the responding modem except when the transmission squelch circuit is disabled in response to the squelch disable signal.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: August 29, 2000
    Assignee: Dantel, Inc.
    Inventor: Ronald J. Dean
  • Patent number: 6098142
    Abstract: A communications port adapter and method for using a communications port of a host computer in polling mode and without interrupts. The communications port adapter includes at least a converter circuit for converting an input signal from a measuring device to frequency, a switching component connected to an output of the converter circuit for transmitting a frequency output signal, and a counter circuit having an input connected to the switching component for receiving the frequency output signal of the converter circuit and an ouput coupled to the communications port of the host computer.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: August 1, 2000
    Inventors: John D. Leggett, Keith A. Wright
  • Patent number: 6094690
    Abstract: A computer system having a control system for controlling a VGA module built in the motherboard is disclosed. The operation of the internal video module is dependent on the existence of an add-on video card mounted in an expansion slot of the computer system. The control system for enabling and disabling the internal video adapter module includes an IDSEL (device identification signal line) signal masking and unmasking circuit provided at the IDSEL signal line placed between the internal video adapter module and a system bus, wherein the masking and unmasking of the IDSEL signal are responsive to a control signal fed from the computer system; and a system BIOS outputting the control signal supplied with the IDSEL signal masking and unmasking circuit through a general purpose input/output module, wherein the output of the control signal is dependent on the existence of an add-on video card mounted in an expansion slot.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: July 25, 2000
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Hyun-Kook Lee
  • Patent number: 6092140
    Abstract: A network bridge includes a processor, a common memory, a first interface to a first network and a second interface to a second network. Upon the first interface receiving a first request to transfer data from a device on the first network, the processor seeds a portion of a first buffer within the first common memory with a predetermined polling pattern. The processor polls the portion of the first buffer to determine when data has arrived into the first buffer. When the processor determines that data has arrived into the first buffer, the processor authorizes the second interface to set up a write process with a device on the second network.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: July 18, 2000
    Assignee: Hewlett-Packard Company
    Inventor: Eric Gregory Tausheck
  • Patent number: 6065073
    Abstract: A system and method for auto-polling a status register within a physical layer (PHY) interface to a local area network (LAN). The system includes a host CPU which needs to detect and service interrupts generated by a PHY device on the LAN which is coupled between a first transmission medium (such as copper or fiber cable) and a management interface to the system. The system further includes an auto-polling unit which monitors activity on the management interface of the PHY device. When the auto-polling unit detects a lack of activity on the management interface of the PHY for a predetermined interval, the auto-polling unit reads a first value from the PHY status register. This first status value is then compared to a previously stored value which corresponds to the last PHY status value read by the host CPU. If a mismatch is detected between these two values, an interrupt is generated to the CPU.
    Type: Grant
    Filed: August 17, 1998
    Date of Patent: May 16, 2000
    Assignee: Jato Technologies, Inc.
    Inventor: Bradley J. Booth
  • Patent number: 6014718
    Abstract: A computer system comprises a computer main body including a main board on which various components such as a CPU and the like are mounted and a hard disc unit; a read-only optical disc drive provided in the computer main body; a write-only optical disc drive which is constructed separately from the read-only optical disc drive, the write-only optical disc drive being provided in the computer main body; and a bus for connecting the main board, the hard disc unit, the read-only optical disc drive, and the write-only disc drive with each other, in which the hard disc unit, the write-only optical disc drive and the read-only optical disc drive are connected by means of a cascade connection.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: January 11, 2000
    Assignee: Mitsumi Electric Co. Ltd.
    Inventor: Tetsuo Kurihara
  • Patent number: 6012110
    Abstract: An apparatus for handling data at two or more ports is described. In one embodiment, the apparatus comprises an apparatus for receiving data at multiple ports, each port having a buffer capable of holding B units of received data and being serviced by a processor resource. The apparatus has software causing the processor resource to have a polling session with each port and to read unread units of data from the buffer in each port during its polling session. It also has a counter for determining the number of units of data that have been read from the buffer and circuitry responsive to said counter to assert flow control from said port based on the number of units of data read.
    Type: Grant
    Filed: December 26, 1997
    Date of Patent: January 4, 2000
    Assignee: Digi International
    Inventors: Gene H. Olson, Ralph E. Richardson
  • Patent number: 5978857
    Abstract: An enhanced multimedia device driver for personal computers includes a polling process which performs polling of the hardware devices. The device driver creates a helper thread for each hardware device which executes in the client context. Each polling process wakes up at a regular interval at which time it polls the status register of the corresponding hardware device. If there is an event pending at the status register, then the polling process signals the event pending to all of the helper threads. Each helper thread wakes up and checks the reason for the wakeup. At this point, the helper thread will initiate a data transfer using programmed I/O if called for by the reason for the wakeup. Through the use of the present invention, the DMA controller, the system interrupt controller, and the kernel interrupt handler of the kernel are not employed in data transfers and the use of DMAs and/or IRQs for data transfers is eliminated.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: November 2, 1999
    Assignee: Winnov, Inc.
    Inventor: Harry L. Graham
  • Patent number: 5958020
    Abstract: The system of the present invention comprises a system for implementing a real time capability in peripheral devices. The system of the present invention functions with a computer system including a processor, a memory, and a video controller, each coupled to a system bus. A USB (universal serial bus) controller is also coupled to the system bus for interfacing peripheral devices on a USB cable to the computer system. A first and second register are included in the USB controller for storing a controller frame number and a controller frame remaining, and a second and third register are included in the peripheral device for storing a device frame number and a device frame remaining. The peripheral device is coupled to the USB controller via a USB cable. A screen reference register is coupled to receive the controller frame number and the controller frame remaining from the USB controller and is coupled to receive a reference signal from a video controller.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: September 28, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: David R. Evoy, Lonnie Goff, Peter Chambers, Mark Eidson
  • Patent number: 5948084
    Abstract: A device for remotely controlling a computer system operable in a graphic user interface environment. The remote control device comprises a micro-computer for converting a remote control signal transmitted from a remote control transmitter into a combined key signal and controlling the operation of the computer system in response to input data and command, a device driver for instructing an operation based on the combined key signal from the micro-computer and applying data and a command to the micro-computer if the combined key signal indicates the operation of the micro-computer, and a user interface software for performing bidirectional communication with the device driver and driving an application software corresponding to the combined key signal from the micro-computer to perform the operation based on the combined key signal. According to the present invention, a remote control function can always be stably performed, and can cope flexibly with variations in hardware and software environments.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: September 7, 1999
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Ho Jin Ha
  • Patent number: 5935222
    Abstract: An arrangement wherein peripheral modules of a decentralized peripheral system connected to an automation unit can be identified. To do so, the peripheral modules of the decentralized peripheral system are equipped with a device that converts a polling signal sent to it into an identification signal during an identification mode. The arrangement can be used in decentralized peripheral systems of programmable control systems.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: August 10, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventor: Detlev Knauer