Abstract: Methods, systems, and devices for a data circuit for a low swing data bus are described. An apparatus may include a data bus that may transfer data at a first voltage different than a second voltage that is associated with one or more components of the memory array. A transistor, coupled with the data bus, may receive the second voltage and send a third voltage. A first in first out (FIFO), coupled with the transistor, may receive the third voltage from the transistor. The FIFO circuit may include one or more precharge components that drive an input voltage of the FIFO circuit to the second voltage associated with the one or more components of the memory array based on receiving the third voltage.

Abstract: A web application has a limit on the total number of concurrent users. As requests from client devices are received from users, a determination is made whether the application can accept those users. When the threshold number of users has been exceeded, new users are prevented from accessing the web application and are assigned to a queue system. A webpage may be sent to the users indicating queue status and may provide their estimated wait time. A cookie may be sent to the client for tracking the position of the user in the application queue. The users are assigned to a user bucket associated with a time interval of their initial request. When user slots become available, the users queued in the user bucket (starting from the oldest user bucket) are allowed access to the web application.

Abstract: Techniques are disclosed relating to dynamically adjusting buffering for distributing compute work in a graphics processor. In some embodiments, the graphics processor includes shader circuitry configured to process compute work from a compute kernel, multiple distributed workload parser circuits configured to send compute work to the shader circuitry, primary workload parser circuitry configured to send, via a communications fabric, compute work from the compute kernel to the distributed workload parser circuits, and buffer circuitry configured to buffer compute work received by one or more of the distributed workload parser circuits from the primary workload parser circuitry. In some embodiments, the graphics processor is configured to dynamically adjust a limit on the number of entries used in the buffer circuitry based on information indicating complexity of the compute kernel. This may advantageously maintain launch rates while reducing or avoiding workload imbalances, in some embodiments.

Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.

Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.

Abstract: A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.

Abstract: An apparatus for storing data in a non-volatile memory includes a data processing unit and a memory unit. The data processing unit is configured to acquire data blocks, terminate each data block of the data blocks with a terminating element, and assemble the terminated data blocks into a serial data stream. The memory unit is configured to sequentially write the serial data stream to the non-volatile memory. The terminating element is variable between a first code word and a second code word. The data processing unit is configured to switch between using the first code word and the second code word as the terminating element in response to the non-volatile memory having been written to completely by the memory unit.

Abstract: Methods and systems for processing data inquiries are described. In one embodiment, data from a data source can be received, a data processing request indicating a request to perform a first function can be received, and a first identifier associated with a user can be determined based on the received data. A table storing a plurality of adjudication results including a plurality of field parameters may be accessed. The plurality of adjudication results in the table can be filtered by determining which of the plurality of adjudication results includes one of the plurality of field parameters having a value that matches or corresponds to the selected field value to create a first subset of filtered adjudication results from the plurality of adjudication results. The first subset of adjudication results can be transmitted when the processor determines that at least one adjudication result of the plurality of adjudication results is within the first subset. Additional methods and systems are disclosed.

Abstract: A method for storing a packet in an application buffer of a processor node is described. A first out of order (OOO) packet within a stream of packets transmitted from a second network interface controller is received in a sequence represented by respective sequence numbers that are assigned to corresponding packets in the stream. The first OOO packet is received out of order relative to at least a first missing packet of the stream of packets. One of an OOO buffer associated with the first network interface controller or the application buffer associated with the first network interface controller is selected. The OOO buffer is configured to store OOO packets. The first network interface controller is configured to store the stream of packets in sequential order in the application buffer. The first OOO packet is stored in the selected buffer.

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.

Abstract: The techniques disclosed herein provide dynamic permissions for controlling messages directed to a presenter of a communication system. For example, during a presentation of an online meeting, a system may selectively permit private messages to be sent to a presenter from designated participants. The private messages sent from the designated participants are displayed to the presenter in a manner that does not allow the other participants to see the messages. For instance, if the presenter is sharing a screen from a computer, the system can determine a set of permitted users allowed to send messages to the presenter. The system configures permissions to cause the messages to be displayed in a manner that allows the presenter to view the messages along with their presentation content, while restricting or suppressing the display of the messages to other non-permitted users. The system restricts the non-permitted users from sending messages to the presenter.

Abstract: Systems and methods for creating a new entry in a hierarchical state data structure with object entries is disclosed. The method includes allocating a shared memory buffer for a new entry in a shared memory. A request to create the new entry for a child object in a hierarchical state data structure in the shared memory is received. The new entry is to span at least one shared memory buffer uniquely identifiable in a location of the shared memory. The child object is a logical representation of a state of a system. In response to a request for an allocation of a shared memory buffer within a region of the shared memory for the new entry, a location identifier corresponding to a location of a parent entry holding a parent object to the child object in the hierarchical state data structure of an allocated region is received. The child object is created in the shared memory buffer for the new entry, and the new entry is available for concurrent access by one or more readers of the shared memory.

Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of the data register. When the data register includes a boundary-lock pattern or a special symbol, the boundary detector outputs a starting address that the boundary-lock pattern or the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing look-ahead-staging (LAS) to accelerate data extraction from a source system to a target system. An embodiment operates receiving a data change for a data extraction from a producer job at the source system. The embodiment stores the data change in a staging area of a persistent storage together with a respective sequence identifier. The embodiment receives a request for a next package of data changes in the staging area from a consumer job at the target system. The embodiment generates the next package from the staging area. The embodiment transmits the next package to the consumer job. The embodiment receives a commit notification for the next package from the consumer job. The embodiment then removes the data changes in the next package from the staging area in response to receiving the commit notification.

Abstract: A method to prevent conflict during synchronization of medical data between a cloud repository on a cloud server and a plurality of local repositories on a plurality of local servers of healthcare facilities connected to the cloud server is provided. The plurality of local servers includes a first local server and the plurality of local repositories includes a first local repository on the first local server. The method includes, in response to a connection between the first local server and the cloud server getting disconnected, causing the first local server to: access the first local repository instead of the cloud repository, determine whether local data is associated with a shared patient registered with more than one healthcare facility among the healthcare facilities connected to the cloud server, and prohibit alteration of the local data if the local data is associated with the shared patient.

Abstract: A data transmission system includes a first memory, a second memory, a third memory; and a memory controller. The memory controller includes a first channel control module and a second channel control module. The first channel control module is coupled to the first memory and the second memory. The first channel control module transmits a first set of data between the first memory and the second memory, and transmits a switch signal after the first set of data is transmitted. The second channel control module is coupled to the first channel control module, the first memory, and the third memory. The second channel control module transmits a second set of data between the first memory and the third memory after receiving the switch signal.

Abstract: An embedded system includes a peripheral and system-on-a-chip executing virtual machines and a hypervisor. The peripheral includes a crossbar circuit receiving digital sensor signals and selectively outputting the digital sensor signals to different outputs, queue circuits each receiving a different one of the digital sensor signals from the crossbar circuit, and queue protection circuits associated with the queue circuits and selectively permitting access to one of the queue circuits by the virtual machines. The hypervisor controls the queue protection circuits to set which of the virtual machines may access which queue circuits. A sensor protection circuit selectively permits reading of the digital sensor signals from the crossbar circuit by the queue circuits. The hypervisor controls the sensor protection circuit to set which of the queue circuits may access each of the digital sensor signals from the crossbar circuit.

Abstract: An electronic device according to various embodiments of the present invention comprises: a memory for storing a database and a file which includes at least one change data for changing the database; and a processor electrically connected to the memory, wherein, when terminating the use of the database, the processor can initialize at least one data other than a first validity data, included in a header of the file, for determining the validity of the at least one change data, and, when commencing the use of the database following the termination of the use of the database, the processor can change the first validity data included in the header of the file. Other various embodiments are possible.

Abstract: The replay of events (e.g., data communications) between software entities should be deterministic and reproducible. In the disclosed framework, as events are replayed, software entities, stimulated by those events, are enqueued according to a queuing strategy and executed from the queue. Alternatively, as software entities are executed, the events, output by those software entities, are queued according to a queuing strategy and played from the queue.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves at a communications device, detecting an erroneously transmitted packet based on a communications protocol associated with the erroneously transmitted packet, and from the communication device, notifying a wired communications network of the erroneously transmitted packet.

Abstract: Example storage systems, file system interfaces, and methods provide cache commit timing management for aggregated writes. A system includes a data cache configured to aggregate data requests in buffer segments. A cache manager determines a delay threshold for each buffer based on usage values of the data cache. The cache manager monitors a commit time value, determines when the commit time value satisfies the delay threshold, and moves aggregate data elements from the buffer to persistent storage.

Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates with the storage device in accordance with a non-volatile memory host controller interface specification. The storage device stores versions of meta data sequentially in a portion of a volatile memory that is protected against power failure using a power hold-up module. In response to a sudden power loss, the power hold-up module provides sufficient energy to support operations to copy the content from the portion of the volatile memory into a non-volatile memory. During a startup process, the content is retrieved from the non-volatile memory; and a binary search is performed to locate, within the content, the latest, valid version of the meta data to continue operations interrupted by the power loss.

Abstract: A control apparatus includes a storage that stores multiple parameters, a nonvolatile memory that is rewritable, and a control circuit that writes on the nonvolatile memory a target parameter from among the parameters. The parameter includes a parameter address indicating a storage location on the storage and at least one piece of parameter data. A control bit that is 0 or 1 is arranged in a parameter address or parameter data. The control circuit writes the parameter if the control bit is 1.

Abstract: In particular embodiments, computer-implemented data processing, systems, and method configured to: receive a request to initiate a transaction between an entity and a data subject, generate (i) a consent receipt for the transaction comprising at least a unique subject identifier and a unique consent receipt key and (ii) a unique cookie to identify the data subject's transaction initiated by the data subject, store the consent receipt for the transaction and the unique cookie, receive a data subject access request from the data subject, verify an identity of the data subject based at least in part on the unique cookie process the request, process the request by identifying one or more pieces of personal data associated with the data subject, and taking one or more actions based at least in part on the data subject access request.

Abstract: Networks, systems and methods for dynamically filtering market data are disclosed. Streams of market data may be buffered or stored in a queue when inbound rates exceed distribution or publication limitations. Inclusive messages in the queue may be removed, replaced or aggregated, reducing the number of messages to be published when distribution limitations are no longer exceeded.

Abstract: An input/output process allocation control device includes: allocation unit that, in a case where a second information processing resource element different from a first information processing resource element executes an input/output-data-transmission/reception-process with an input/output device in response to an access request to the input/output device by the first information processing resource element, the first and second information processing resource elements being among a plurality of information processing resource elements included in an information processing apparatus, allocates the input/output-data-transmission/reception-process to the second information processing resource element and excluding the second information processing resource element, of the plurality of information processing resource elements, from a new allocation destination of a process including an access request to the input/output device.

Abstract: Systems and methods for an interface with a widened interface-to-fabric shoreline between semiconductor circuits and a narrower interface-to-memory controller shoreline. The interface providing transitions from a first clock of a first circuit (e.g., field-programmable gate array (FPGA)), a second clock of a second circuit (e.g., high-bandwidth memory generation 2 (HBM2) stack, and a third clock of a physical layer of the second circuit. A first transfer between the first clock and the second clock may use a first set of first-in first-outs (FIFO) buffers, such as rate-matching FIFO buffers. A second transfer between the second clock and the third clock may use a second set of FIFO buffers, such as phase compensation FIFOs.

Abstract: An electronic device includes a requester and a link interface coupled between the requester and a link. The requester is configured to send a request packet to a completer on the link via the link interface. When sending the request packet to the completer, the requester sends, to the completer via the link interface, the request packet with a tag that is not unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer before the request packet is in the internal elements of the completer, but that is unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer while the request packet is in the internal elements of the completer.

Abstract: A memory tile, in a local memory, may be considered to be a unit of memory structure that carries multiple memory elements, wherein each memory element is a one-dimensional memory structure. Multiple memory tiles make up a memory segment. By structuring the memory tiles, and a mapping matrix to the memory tiles, within a memory segment, non-blocking, concurrent write and read accesses to the local memory for multiple requestors may be achieved with relatively high throughput. The accesses may be either row-major or column-major for a two-dimensional memory array.

Abstract: A hybrid emulation system includes a hardware emulation system, a simulation system, and a co-simulation interface. The hardware emulation system emulates a first portion of a design under test (DUT) during a hybrid emulation. The emulation runs in a first time domain local to the hardware emulation system. The simulation system simulates a second portion of the DUT during the hybrid emulation. The simulation runs in a second time domain local to the simulation system. The first time domain and the second time domain are unsynchronized. The co-simulation interface is coupled to the simulation system and the hardware emulation system. The co-simulation interface communicates transactions and events between the hardware emulation system and the simulation system. For each transaction, the co-simulation interface captures a transaction time in the first time domain, and for each event, the co-simulation interface captures an event time in the first time domain.

Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.

Abstract: A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including a reorder engine and a retransmission engine may be utilized for the reliable transport of the packets. In this regard, a reorder engine includes a content addressable memory (CAM) and one or more processors in communication with the CAM. The one or more processors are configured to receive a first set of data packets when executed by the one or more processors. The one or more processors are configured to access the content addressable memory to process the first set of data packets. The one or more processors are configured to save data information of the first set of the data packets in the content addressable memory.

Abstract: A method and an apparatus for controlling a packet transmission for a split bearer to reduce latency in a wireless communication system are provided. A method by a third node for controlling a packet transmission for a split bearer connected to a first node and a second node in a wireless communication system includes obtaining information related to a buffer state of each of the first node and the second node, determining a packet arrival time at a terminal through each of the first node and the second node based on the information related to the buffer state of each of the nodes, selecting one of the first node and the second node based on a comparison of the packet arrival time corresponding to the first node with the packet arrival time corresponding to the second node, and transmitting a packet to the terminal through the selected node.

Abstract: Techniques are disclosed for systems and methods to conduct transactions using a Multi-mode Card. A Multi-mode Card may include various components of a Smart Card and be configured to interface directly with a personal electronic device (e.g., a smart phone, a tablet computer, a personal computer, and/or other personal electronic devices) to confirm presence of the Multi-mode Card in an unattended digital transaction, such as for e-commerce and Internet purchases. A transaction system may include a logic device and an interface embedded in or on the Card, a client device such as a personal electronic device, and a server configured to provide a sales interface to a user through the client device. The logic device in the Card may be configured to authorize, encrypt, and/or otherwise facilitate a transaction involving a sale and/or other type of communication between the client device and the server.

Abstract: In one embodiment, a processor includes a write combining buffer that includes a memory having a plurality of entries. The entries may be allocated to committed store operations transmitted by a load/store unit in the processor, and subsequent committed store operations may merge data with previous store memory operations in the buffer if the subsequent committed store operations are to addresses that match addresses of the previous committed store operations within a predefined granularity (e.g. the width of a cache port). The write combining buffer may be configured to retain up to N entries of committed store operations, but may also be configured to write one or more of the entries to the data cache responsive to receiving more than a threshold amount of non-merging committed store operations in the write combining buffer.

Abstract: Embodiments of the disclosure provide methods and devices for sending messages. The method can include: storing identifiers corresponding to one or more messages that are to be sent in a first message identifier queue; storing identifiers corresponding to one or more messages that are being sent in a second message identifier queue; acquiring an identifier corresponding to a message in the first message identifier queue; moving the identifier to the second message identifier queue; and sending the message according to a sending order associated with the identifier in the second message identifier queue.

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: Data processing device, in particular, for a control unit, the data processing device including at least one computing device, a memory device, a hardware security module and at least one cryptography module.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Abstract: In particular embodiments, a computer-implemented data processing method for responding to a data subject access request comprises: (A) receiving a data subject access request from a requestor comprising one or more request parameters; (B) determining that the data subject is associated with a particular geographic location; (C) verifying that the data subject is associated with the particular geographic location; (D) in response to verifying that the data subject is associated with the particular geographic location, processing the request by identifying one or more pieces of personal data associated with the data subject; and (E) taking one or more actions based at least in part on the data subject access request, the one or more actions including one or more actions related to the one or more pieces of personal data.

Abstract: A block-based storage system may implement page cache write logging. Write requests for a data volume maintained at a storage node may be received at a storage node. A page cache for may be updated in accordance with the request. A log record describing the page cache update may be stored in a page cache write log maintained in a persistent storage device. Once the write request is performed in the page cache and recorded in a log record in the page cache write log, the write request may be acknowledged. Upon recovery from a system failure where data in the page cache is lost, log records in the page cache write log may be replayed to restore to the page cache a state of the page cache prior to the system failure.

Abstract: Apparatus and method for encoding sub-primitives to improve ray tracing efficiency. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a ray tracing graphics pipeline; a sub-primitive generator to subdivide each primitive of a plurality of primitives into a plurality of sub-primitives; a sub-primitive encoder to identify a first subset of the plurality of sub-primitives as being fully transparent and to identify a second subset of the plurality of sub-primitives as being fully opaque; and wherein the first subset of the plurality of primitives identified as being fully transparent are culled prior to further processing of each respective primitive.

Abstract: An apparatus and method for creating a finite blockchain is provided. The blockchain comprises a genesis block that is the first block of the blockchain. The genesis block comprising a genesis expiry time. The method comprises the steps of creating a reincarnation block when a predefined condition is satisfied and appending it to the blockchain; determining whether the genesis expiry time has elapsed based on an expiry period; if the genesis expiry time has elapsed then identifying a first reincarnation block; if the first reincarnation block is identified then deleting all the blocks preceding the first reincarnation block including the genesis block in the block chain.

Abstract: In particular embodiments, computer-implemented data processing, systems, and method configured to: receive a request to initiate a transaction between an entity and a data subject, generate (i) a consent receipt for the transaction comprising at least a unique subject identifier and a unique consent receipt key and (ii) a unique cookie to identify the data subject's transaction initiated by the data subject, store the consent receipt for the transaction and the unique cookie, receive a data subject access request from the data subject, verify an identity of the data subject based at least in part on the unique cookie process the request, process the request by identifying one or more pieces of personal data associated with the data subject, and taking one or more actions based at least in part on the data subject access request.

Abstract: Embodiments of the present disclosure pertain to improved circuit and system architectures for identifying and managing operating statuses and faults in a system having multiple processing circuit chips. Each of the multiple processing circuit chips includes multiple signal rings, one to provide internal communications among circuitry within the circuit chip, and another with inter-chip communications circuitry to provide communications with neighboring circuit chips. One of the multiple processing circuit chips further includes external communications circuitry to provide communications with an external host.

Abstract: An example apparatus for die addressing can include an array of memory cells and a memory cache. The memory cache can be configured to store at least a portion of an address mapping table. The address mapping table can include entries that map translation units (TUs) to physical locations in the array. The entries can include data that indicate a location within the array that stores a particular TU without including data that indicates which die of the array the TU is stored in.

Abstract: An information processing apparatus includes a management unit that deletes from a first region a fax document that has been successfully transferred to a predetermined transmission destination and moves from the first region to a second region a fax document that has been unsuccessfully transferred to a transmission destination. A user is not permitted to perform an operation on the fax document stored in the first region and the user is permitted to perform an operation on the fax document stored in the second region.

Abstract: A data processing system includes a plurality of computers which include a processor and a memory, a storage device which is connected to the plurality of computers to store data, and a management computer controls the plurality of computers. The computer includes a node pool which can perform, stop, and delete one or more nodes. The node pool includes one or more first nodes which function as a data buffer. The management computer causes the node to measure a performance of data transmission between the data buffer and the storage device, determines a number of increased/decreased nodes on the basis of a measurement result of the performance, and notifies the node pool of a command of performing or deleting the first node according to the determined number of increased/decreased nodes. The node pool adjusts a number of the first nodes according to performing or deleting command.