Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

Abstract: A data storage system has a plurality of hosts that request writes of data to a relatively high-performance storage device (RHPSD) such as NVRAM, which may be one of a plurality of RHPSDs in a plurality of storage nodes. A storage management system receives the write requests and writes received data to the RHPSD. According to an allocation policy, the storage management system indicates to at least one of the hosts that it should limit its use of RHPSD and it then discards data upon indication from that host to do so. Before being discarded from the RHPSD, the data may be written to a persistent storage device.

Abstract: A low energy sensor interface for a microcontroller unit (MCU) is provided. The sensor interface may include a sequencer in operative communication with one or more on-chip peripherals, a count and compare block in communication with one or more sensors and the sequencer, and a highly configurable decoder. The sequencer, the count and compare block and the decoder may be configured to autonomously analyze and collect sensor results using the on-chip peripherals in a low energy mode of operation without intervention from an associated central processing unit (CPU).

Abstract: Techniques are disclosed relating to rendering graphics objects that require shader operations to determine visibility. In some embodiments, a graphics unit is configured to process feedback objects, which may require shading to determine whether they are visible relative to previously-processed objects, out of draw order. For example, in embodiments where a buffer is used to store fragment data for deferred rendering, the graphics unit may bypass the buffer and shade feedback objects ahead of earlier non-feedback objects whose fragment data is stored in the buffer. This may allow a determination of whether to remove occluded non-feedback fragment data from the buffer, which may reduce graphics overdraw. In disclosed two-pass techniques, data for feedback objects is first allowed to bypass the buffer for visibility shading, but is then stored in the buffer for a second pass to perform fragment shading to actually determine pixel attributes, which may further reduce overdraw.

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.

Abstract: A control unit provides a number of buffer credits, to one or more channels, in response to an initiation of a startup phase of communication between the one or more channels and the control unit, where the provided number of buffer credits when used for transferring data causes transfer ready operations but no retry operations. The control unit iteratively increases the number of buffer credits by an amount that is high enough to eliminate any transfer ready operations or cause retry operations to occur within a predetermined amount of time from the initiation of the startup phase.

Abstract: Embodiments are directed to a method of optimizing disk striping input/output (I/O) operations to an array of storage devices, by identifying an I/O request as a full stripe write request that stripes data across a plurality of storage devices of the array, converting the full stripe write request to a SCSI command block (CDB), and putting the SCSI command block in one of a stripe cache or a non-stripe cache that comprises a sorted linked list where each node of the linked list is a link to one of the plurality of storage devices.

Abstract: A communication system is provided. The communication system includes slave modules outputting collected data to a master module, and outputting data priority processing request information to the master module; and the master module connected to slave modules, collecting data from the slave modules, and processing, by priority, data from a corresponding slave module based on the data priority processing request information received from at least one slave module.

Abstract: A send buffer is allocated within a kernel of an operating system (OS) of a first node. An application of the first node includes an application buffer. A message of an application buffer is copied to the send buffer. The kernel of the first node is to aggregate a plurality of the messages stored at the send buffer into a single transfer and to output the single transfer across a network to a second node.

Abstract: A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches.

Abstract: Aspects include balancing work of tasks at a sending node of a transaction server in a network. A method can include processing a task from the top of a work queue at the sending node, where the task is an instance of a transaction which requires a transaction message to be sent from the sending node using a network connection. The transaction message is divided into chunks of partial transaction sub-messages. For each chunk, it can be dynamically determined whether a pacing response indicator is required based on metrics that monitor the activity in the work queue and a number of chunks of the transaction message already sent.

Abstract: A parallel computer includes a first node and a second node, each including a memory having a plurality of memory areas and a cache memory, and a processing unit that acquires a first group of index levels of the cache memory, the first group of index levels corresponding with addresses of first plurality of memory areas storing data accessed by a job in the first node, when continuing an execution of the job by migrating the job carried out on the first node to the second node, judges whether or not the second node has second plurality of memory areas that are a usable state corresponding to a second group of index levels that has same as or relative position relation with the first group of index levels, and relocates the data to the second plurality of memory areas when the second node has the second plurality of memory areas.

Abstract: Systems and methods of queuing data for multiple readers and writers are provided. Enqueuing operations are disclosed that can process write functionality and can determine whether ring buffers have potentially filled, and dynamically declare a new ring buffer at a multiple of capacity of the current ring. Dequeuing operations are disclosed that can process read functionality for advancing control and determining whether and when to free ring buffers from memory.

Abstract: Methods and systems for managing I/O requests in a secure storage appliance are disclosed. One method includes receiving a plurality of I/O requests at the secure storage appliance, each I/O request associated with a block of data and a volume, each volume associated with a plurality of shares stored on a plurality of physical storage devices. The method further includes storing a plurality of blocks of data in buffers of the secure storage appliance, each of the blocks of data associated with one or more of the plurality of I/O requests. The method also includes associating a state with each of the blocks of data, the state selected from a plurality of states associated with processing of an I/O request.

Abstract: Aspects include balancing work of tasks at a sending node of a transaction server in a network. A method can include processing a task from the top of a work queue at the sending node, where the task is an instance of a transaction which requires a transaction message to be sent from the sending node using a network connection. The transaction message is divided into chunks of partial transaction sub-messages. For each chunk, it can be dynamically determined whether a pacing response indicator is required based on metrics that monitor the activity in the work queue and a number of chunks of the transaction message already sent.

Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.

Abstract: A streaming media adaptive transmission method is presented, which may include determining in real time, by user equipment, a transmission rate of to-be-transmitted data, or determining a transmission rate according to a negotiation request that includes an option of a transmission rate and is provided by a base station; sending, by the user equipment, a rate guarantee request to the base station, where the rate guarantee request includes the transmission rate; and after receiving a message that is for confirming that the transmission rate is available and that is returned by the base station, requesting, by the user equipment from a data sending end, to-be-transmitted data of which an encoding rate is corresponding to the transmission rate. User equipment, a base station, and a streaming media adaptive transmission system are further disclosed.

Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.

Abstract: A data migration method includes creating, by a first control processor that controls a first cache memory storing first cache data cached from first storage data stored in a storage, first management information including information indicating a storage location of the first cache data on the first cache memory and information indicating whether or not the first storage data has been updated in accordance with an update of the first cache data for each block of a predetermined data size in the first cache memory, when a program that accesses the first cache data migrates to a different node, transmitting, by the first control processor, the first management information to a second control processor that controls a second cache memory capable of being accessed by the program after migration to the different node.

Abstract: An information push system, including a plurality of signal transmitters, a client side, and a server. The signal transmitters are configured to output a respective identification code. The client side is configured to determine a user setting, and receive the identification codes from the signal transmitters. The server is configured to receive the user setting and the identification codes from the client side, and output the push information of a received identification code according to the user setting and the received identification code. The server also includes a database, which is configured to store the user setting, and the identification code and the push information which are corresponding to each signal transmitter.

Abstract: A storage control device configured to control a storage device includes a memory and a processor coupled to the memory and configured to receive a request of writing of data from an information processing device, assign a unit memory area in the storage device in response to the request of writing, determine whether a sequential format processing is to be executed on the unit memory area based on continuity of logical addresses designated by the request of writing, and determine a timing to execute the sequential format processing on the unit memory area based on a number of commands per unit time to the storage device when the sequential format processing is determined to be executed on the unit memory area.

Abstract: As a method for migrating data of a volume adopting a snapshot function to a new storage system, in order to perform migration without depending on a method for compressing snapshot data of a migration source storage system, and without stopping transmission and reception of data between the host computer and the storage system, at first, after migrating data of a volume being the source of snapshot (PVOL), migration is performed sequentially from newer generations. At this time, migration target data of each SVOL is all the data within the migration source storage system. The SVOL data copied to a migration destination storage is compared with one-generation-newer SVOL data within the migration destination storage system, and based on the comparison result, a difference management information is created. If there is difference, a VOL allocation management table is updated, and difference data is stored in the area allocated within the pool.

Abstract: In a telecommunications network including at least a user device and a network node separated by at least a packet-switched part of the telecommunications network, the user device including a primary jitter buffer having a constant packet play-out rate, the network node including a secondary jitter buffer, incoming packets destined for the user device are received and passed through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device. The departure times of packets passing through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device are monitored. On the basis of the monitoring and one or more known characteristics of the primary jitter buffer, an estimate of a current state of the primary jitter buffer is maintained. Operation of the secondary jitter buffer is dynamically controlled according to the maintained estimate.

Abstract: The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit.

Abstract: An application sends a first request to an operating system to provide a hardware device with direct memory access to contents of a virtual memory location in an application memory of the application, wherein the virtual memory location is mapped to a physical memory location. In response to determining that the virtual memory location is to be reclaimed, the application sends a second request to the operating system to unmap the physical memory location from the virtual memory location. The second request causes the virtual memory location to be mapped to a new physical memory location. Responsive to receiving an indication from the operating system that the request to unmap the physical memory location has completed, the application then accesses the new physical memory location mapped to the virtual memory location.

Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.

Abstract: A network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyzes a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.

Abstract: A controller and a memory-access method for use in the controller are provided. The controller includes a sensor-processing system, and the sensor-processing system includes a memory, and a buffer, wherein the controller is coupled to an external memory and a sensor. The method includes the steps of: gathering the sensor data from the sensor and writing the gathered sensor data into the memory; writing information associated with the sensor data into the buffer; determining whether a fill level of the buffer has reached a predetermined threshold; and retrieving the sensor data from the memory and writing the retrieved sensor data to the external memory according to the information associated with the stored sensor data in the buffer when it is determined that the fill level has reached the predetermined threshold.

Abstract: Systems and methods for writing data are provided. A lock-free container and methods of writing to the lock-free container are disclosed. The container is associated with a tail pointer that identifies free space in the container. Threads writing to the container access the tail pointer and update an offset in the tail pointer to account for a size of a write to the container. Multiple threads can write to the same container without having to contend for a container lock.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: A system and method for efficiently relocating and initializing a block of memory of the computer system. For data initialization and data relocation, multiple registers in a processor are used for intermediate storage of data to be written into the memory. Regardless of whether the amount of data to initialize or relocate is aligned with the register data size, the processor writes the data into the destination buffer with write operations that only utilize the register data size. The write operations utilize the register data size when each of the start and the end of the destination buffer is aligned with the register width, when the start of the destination buffer is unaligned with the register width, when a source buffer and the destination buffer are unaligned with one another for a copy operation, and when the source buffer and the destination buffer overlap.

Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Abstract: A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.

Abstract: A computer-implemented method, system, and computer-readable media are disclosed herein. In embodiments, the computer-implemented method may entail receiving, by a data service, live data associated with an entity. The entity may be, for example, a customer of the data service. The method may then route the live data to a dual-queue system of the data service. The live data may be loaded into a live data queue of the dual queue system for processing. Processing may entail generating summary statistics from the live data. An alert may then be transmitted to the customer in response to detecting the occurrence of one or more alert events. In embodiments, the alert events may include events identified in the summary statistics. Additional embodiments are described and/or claimed.

Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

Abstract: Embodiments of the present invention disclose a data restoration method, including: after a transaction is submitted, saving a generated transaction log to a buffer of a current node, and backing up the transaction log to a buffer of at least one backup node except the current node; writing the transaction log saved in the buffer of the current node or the transaction log backed up in the buffer of the backup node into a transaction log file in a disk, where the transaction log file in the disk is used for restoring data of the current node; and restoring, based on the transaction log file in the disk, lost data of the current node when a data loss event occurs in the current node. By means of the present invention, a risk of system data can be reduced, and durability, safety, and reliability of the system data can be improved.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: A method and device are provided for processing data. The method includes, after receiving data input by a data bus, according to a destination indication of the data and a valid bit field indication of the data, writing the data input by the data bus into an uplink side shared cache, polling the uplink side shared cache according to a fixed timeslot order, reading out the data in the uplink side shared cache, and outputting the data to respective corresponding channels. The method and device enable effective saving of cache resources, reduction of pressure on area and timing, and improvement of cache utilization while reliably achieving data cache and bit width conversion.

Abstract: An information handling system (IHS) comprising a chassis, a motherboard disposed within the chassis, a management controller (MC) coupled to the motherboard and a network attached storage (NAS) coupled to the MC wherein the MC provides access to the NAS. An IHS may further include and input/output (I/O) module (IOM) disposed within the chassis, at least one blade and a keyboard video mouse (KVM) module, wherein the NAS is directly accessible to the IOM blade(s) and KVM module.

Abstract: A memory system may include a command storage unit for storing maximum N commands received from a host, K memory devices each for storing maximum M commands based on the maximum N commands and performing each set operation in response to the stored maximum M commands in order of input, and a resetting unit for resetting execution sequences of the maximum N commands based on execution information regarding each of the maximum N commands and the maximum M commands in each of the K memory devices whenever the commands received from the host are stored in the command storage unit, and distributing the N commands to the K memory devices. The execution information includes a logical address, a physical address, a length, and a use time of a corresponding command.

Abstract: System and method of using a processor driven master Quad-SPI (QSPI) bus or interface to simultaneously and time-synchronously transmit different streams of data from a FIFO buffer to a plurality of different slave SPI interface peripherals. Here the QSPI interface data ports are configured to simultaneously transmit multiple 1 bit wide streams of different binary data and different chip select commands on an SPI clock cycle synchronized basis. Additional SPI slave peripherals may be controlled by use of additional non-SPI clock synchronized GPIO chip select commands and suitable logic gates. These methods are useful for creating a variety of embedded systems with faster response speeds, such as improved microwave frequency synthesizers with faster frequency changing times.

Abstract: Systems and methods are provided that enable flow aware buffer management. The method includes storing in a queue of a buffer a first type of traffic, storing in the queue of the buffer a second type of traffic, wherein the first type of traffic is less sensitive to latency than the second type of traffic, and when an amount of the first type of traffic meets or exceeds a first threshold, effecting flow control of the first type of traffic to slow a flow of the first type of traffic into the buffer. Flow control can be effected using packet marking or discarding packets. The methodology has particular utility in connection with managing elephant and mouse flows in a network switch.

Abstract: Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword.

Abstract: A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.

Abstract: A system including an encoder module, a buffer first-in first-out (FIFO) module, a buffer manager module, N FIFO modules, and N input/output (I/O) modules. The encoder module encodes data received from a host and generates P units of encoded data, where P is an integer greater than 1. The buffer FIFO module receives the P units from the encoder module and outputs the P units. The buffer manager module receives the P units from the buffer FIFO module, stores the P units in a buffer, retrieves N of the P units from the buffer, and outputs the N units in parallel, where N is an integer greater than 1. The N FIFO modules respectively receive the N units in parallel directly from the buffer manager. The N I/O modules receive the N units from the N FIFO modules in parallel, respectively, and output the N units to a storage medium.

Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.

Abstract: Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.