Abstract: A system program causes, as an execution preparation process for a control operation of a PLC, execution of a process for generating a reception buffer for storing received input data, and execution of a process for generating, for each input data referred to by a control program, an input synchronization buffer used by the control program as a reference target for the input data. The system program causes, as an execution control process for the control operation of the PLC, execution of an input copy process for copying the received input data from the reception buffer to the input synchronization buffer corresponding to the input data, and execution of a control program start process for starting execution of the control program.

Abstract: A method of controlling one or more devices in data communication with a common controller to perform one or more functions, each of the devices having a synchronous clock, a synchronized real time clock register and a memory, the method comprising: arming the devices such that the devices commence performing the functions synchronously, receive and store to their respective memory data acquired as a result of performing the functions and store to their respective memory time stamp information indicative of the time of acquisition of the acquired data; a trigger device in data communication with the common controller responding to a command to perform the functions by sending a first message to the host controller that includes data indicative of a time of receipt of the command; the host controller responding to the first message by sending the devices a second message including data indicative of the time of receipt by the further device of the command; and the devices responding to the second message by re

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: In one embodiment, a main circuit board includes a plurality of expansion slots that are operative to receive a corresponding plurality of expansion cards. The plurality of expansion slots include at least one first expansion slot configured at a first position on the main circuit board, that is operative to connect to at least one corresponding first expansion card. At least one second expansion slot configured at a second position on the main circuit board, and the second expansion slot is operative to connect to at least one corresponding second expansion card. The plurality of expansion cards includes at least one secondary expansion card that is different from the main circuit board and that is configured to be operatively coupled to at least one of the plurality of expansion slots. One or more particular expansion slots are selected for connecting one or more corresponding particular expansion cards, based on the size, dimensions, and/or function of the particular expansion cards to be connected.

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract: The disclosed system and methods involve controlling the timing and order in which numerous motors and sensors exchange data over a data bus. The method can be used with, for example, motion control, automotive, industrial automation, and medical equipment applications using data buses. As an example of one possible medical equipment application, the method of exchanging data on a bus can be used with a remote catheter guidance system. The disclosed system and methods help optimize data exchange over a bus and avoid collisions by grouping the transmission of sensor readings, by grouping the transmission of motor commands, and by predetermining the order of these groups. Further, the method provides a way of ensuring that incomplete data sets are not exchanged over the bus. The method also provides a way of synchronizing motor actuation based on data transmitted to the data bus.

Abstract: A host device is managed that communicates with a peripheral device via an interface on the basis of a high frequency clock; the host device is in a suspended state in which the high frequency clock is deactivated. At the host device, an activation state of the peripheral device is detected (21) on the interface. Then the duration of a period of time (T1) since the detection of the activation state is counted, on the basis of a low frequency clock. Then this activation state is maintained on the interface (23) by means of hardware before the period of time expires.

Abstract: A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.

Abstract: A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.

Abstract: A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first a

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: There is provided a signal transmission system including an information processing device and an interface device. The information processing device codes transmitted data into a code that does not include a direct-current component, and the information processing device transmits the code while superimposing the code on a direct-current power. A polarity of the code is inverted every half a period of a clock. The interface device detects a polarity inversion period of a signal received from the information processing device, and the interface device reproduces the clock based on the detection result.

Abstract: A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path.

Abstract: A method and communication system that provide an inexpensive approach that enables the times of events that are detected in IO device to be determined in a higher-level controller. The higher-level controller has a system clock and is connected to an IO link device to which multiple first IO devices are able to be connected. In addition, a second IO device is connected to the IO link device. The clock of the second IO device is synchronized by a synchronization device with the system clock of the higher-level controller. The status data that are provided by at least one of the first IO devices and the current time data that the second IO device supplies are transmitted simultaneously to the IO link device. The IO link device assigns the status data received to the received current time data, then transmits these data to the higher-level controller.

Abstract: A method for transmitting data frames between a master device and one or more slave devices via a bus system having at least one request line for transmitting request data frames from the master device to the slave devices, a response line for transmitting response data frames from the slave devices to the master device and at least one selection line for activating the slave devices, the request data frames and the response data frames being transmitted together with at least one address bit for addressing one of the slave devices, the useful data bits and at least one length-indicating bit for indicating the data frame length.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: Systems and methods for streaming data are disclosed. In various implementations, the system comprises a hardware device and input streaming interface operably connected to the hardware device. The input streaming interface is configured to inform a data source, based on a determination that a receiving device will accept data transmitted by the hardware device, that the input streaming interface is ready to receive data, and then receive, in response to the detecting the activation of a source signal and a data initiation signal associated with the data source, source data transmitted by the data source over a data bus, and forward the source data to the hardware device.

Abstract: A centralised synchronizing device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system. A system synchronizing request is a request generated by one of the plurality of transaction generating devices and queries progress of a subset of the transaction requests. The synchronizing device includes: at least one port to and from the data processing system; a multicast circuitry configured to output a plurality of synchronizing requests for multicast to at least some of the devices within the data processing system where the requests query the progress of the subset of the transaction requests. Gather circuitry collects responses to the requests confirming that the queried progress has occurred at the respective devices. The gather circuitry determines when responses to all of the requests have been received and outputs a response to the system synchronizing request.

Abstract: A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Abstract: Some demonstrative embodiments of the invention include methods, devices and/or systems to transfer data over serial signals, for example, a method of transferring over serial signals data representing an image to be reproduced, the method including generating a set of one or more data signals including image data received at an image data rate, and generating a transmission clock signal having a clock cycle during which the set of image data signals includes image data of more than one pixel of the image to be reproduced. Other embodiments are described and claimed.

Abstract: A computer-implemented method may include determining a number of virtual functions that each port of a hardware input/output adapter is capable of supporting. The computer-implemented method may include assigning a first portion of internal resources of the hardware input/output adapter to each port of the hardware input/output adapter. The computer-implemented method may also include, for a particular port of the hardware input/output adapter, assigning a second portion of the internal resources to each virtual function that the particular port is capable of supporting. The second portion of the internal resources may be a subset of the first portion of the internal resources. The computer-implemented method may further include configuring a virtual function prior to a runtime to use the assigned second portion of the internal resources.

Abstract: A method for transmitting data on a configurable bus of z physical links, including receiving input data on an input bus at at least one of a plurality of data rates, selecting a number of physical links n, amongst the z physical links, on which data is to be transmitted, selecting a clock frequency f at which the data is to be transmitted on the configurable bus, wherein the selections of n and f are based on information concerning the at least one of the plurality of data rates, the number of links used on the input bus.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A process is provided for transferring a first sequence control and/or first data into a first control device and a second sequence control and/or second data into a second control device in a motor vehicle. The transfer is carried out by way of a first data bus while using a first transmission protocol which has a data frame with a predetermined frame format or message format, and the transfer as a whole takes place by the transmission of a plurality of data frames. In a first step, by way of a first data frame, a portion of the first sequence control and/or of the first data is transmitted to the first control device. In a second step, by way of the second data frame, a portion of the second sequence control and/or of the second data is transmitted to the second control device.

Abstract: A system and method for enabling legacy media access control (MAC) to do energy efficient Ethernet (EEE). A backpressure mechanism is included in an EEE enhanced PHY that is responsive to a detected need to transition between various power modes of the EEE enhanced PHY. Through the backpressure mechanism, the EEE enhanced PHY can indicate to the legacy MAC that transmission of data is to be deferred due to a power savings initiative in the EEE enhanced PHY.

Abstract: Methods, apparatuses, and computer program products are provided for synchronization of data between an electronic mobile device and an electronic computing dockstation. Embodiments include detecting, by the dockstation, completion of a docking procedure connecting the mobile device to the dockstation; identifying, by the dockstation, applications that are open on the mobile device; opening, by the dockstation, the identified applications on the dockstation; identifying, by the dockstation, files that are open on the mobile device; syncing, by the dockstation, the identified files with corresponding files within the dockstation, including updating an existing file within the dockstation; and opening on the dockstation, by the dockstation, the synced files with the open applications on the dockstation.

Abstract: A centralised synchronising device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system in response to receipt of a system synchronising request, the data processing system having a plurality of devices including a plurality of transaction request generating devices for generating the transaction requests and a plurality of recipient devices for receiving the transaction requests, the synchronising device and at least one interconnect for interconnecting at least some of the devices; wherein the system synchronising request comprising a request generated by one of the plurality of transaction generating devices and querying progress of the at least a subset of the transaction requests; the synchronising device comprising: at least one port for receiving requests from, and outputting requests and responses to, the data processing system; multicast circuitry configured to generate a plurality of synchronising requests in response to recei

Abstract: Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect lane-to-lane skew in the patterns of read data. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.

Abstract: A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.

Abstract: A method according to one embodiment includes receiving a request to perform a backup of data associated with an application running on multiple servers; communicating with I/O Handlers on the servers for initiating a coordinated backup operation on the data at about a same start time; and instructing the I/O Handlers to stretch communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: The invention relates to a method according to which a cycle-oriented control program generated for a programmable logic controller (110) is at least partially converted into a code that may be executed by a logic component (80) of a communications module (10), such that at least the converted program segment of the cycle-oriented control program may be executed in a cycle-free manner. Cycle-free or virtually cycle-free means that at least some of the implemented control functions and system functions may be executed in a parallel fashion and therefore more quickly than would be the case if the cycle-oriented control program were executed by the PLC (110).

Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.

Abstract: A data conversion system for converting data outputted from an information processor into data in a different format in real time while preventing any defect of an image such as frame missing or frame repetition of moving image data by synchronizing data transfer with converted data output. One of first and second nodes on an IEEE1394 bus functions as a cycle master, and first data is transferred from the first node to the second node in synchronism with a cycle start packet outputted from the cycle master. Second data generated by converting the first data by the second node is outputted in synchronism with a reference signal inputted from outside.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: An on-chip Radio Frequency (RF) Interconnect (RF-I) for communication between internal circuit nodes of an integrated circuit is provided. In one embodiment, an integrated circuit is provided that includes an on-chip transmission line, a first circuit node associated with an RF transmitter connected to the transmission line, and a second circuit node associated with an RF receiver connected to the transmission line. In order to transmit data from the first circuit node to the second circuit node, the RF transmitter associated with the first circuit node modulates the data onto an RF carrier frequency to provide a modulated RF signal and transmits the modulated RF signal over the transmission line. The RF receiver associated with the second circuit node receives the modulated RF signal from the transmission line and demodulates the modulated RF signal to recover the data for the second circuit node.

Abstract: A data transmission method and the transmission circuit thereof for transmitting data between a host and a peripheral apparatus are disclosed. The data transmission method includes the following steps. First, a clock signal is transmitted by a first pin. Then, a data signal is transmitted by a second pin according to the timing of the clock signal.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.

Abstract: A system and method for efficient timing optimization for asymmetric paths to replicated units. A microprocessor may include multiple instantiations of a processing core. Chip-level interconnects may have asymmetric routing paths to the multiple cores. The interconnect routes may need to be stable early in the design cycle and yet possess multiple timing paths to the multiple instantiated cores. Modifications to the input/output ports of the cores may provide the necessary timing requirements for the cores without dynamically altering the chip-level interconnects.

Abstract: The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing.

Abstract: A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor.

Abstract: A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data register unit in response to the strobe or non-free running clock and to output the data stored, in response to another clock.

Abstract: A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.