Operation Scheduling Patents (Class 710/6)
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Patent number: 9906062Abstract: Methods, systems, and apparatuses for charging a host device from a charging source through an accessory are described. Upon detecting an input power signal from the charging source, an accessory may send an identification request to the host device and authenticate the host device based on the identification information received from the host device. Upon authenticating the host device, the accessory may enable a power path between the charging source and the host device to supply a charging current to charge the host device.Type: GrantFiled: December 8, 2015Date of Patent: February 27, 2018Assignee: APPLE INC.Inventors: Jeffrey J. Terlizzi, Jonathan J. Andrews, Alexei Kosut, James M. Hollabaugh, Zachary C. Rich, Daniel J. Fritchman
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Patent number: 9891866Abstract: Methods and systems are described herein to provide efficient data retrieval in a data storage system. Specifically, in cases where users of a data storage system are not overly sensitive to data retrieval time, such as the case for backup and archival data storage systems, random read requests may be fulfilled as part of sequential reads to reduce I/O operations. A data storage system may be divided into data storage zones. Sequential reads may be performed for data stored in those data storage zones with pending data retrieval requests. Data retrieval requests may be fulfilled based at least in part on the sequentially-read data.Type: GrantFiled: October 1, 2012Date of Patent: February 13, 2018Assignee: Amazon Technologies, Inc.Inventors: Colin L. Lazier, Kestutis Patiejunas
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Patent number: 9870414Abstract: Methods, systems, and computer program products are provided for performing a secure delete operation in a wide area network (WAN) including a cache site and a home site. A method includes identifying a file for deletion at the cache site, determining whether the file has a copy stored at the home site, detecting a location of the copy at the home site prior to a disconnection event of the cache site from the home site, deleting the file from the cache site during the disconnection event, and in response to the secure deletion of the file not being complete during the disconnection event, indicating on a table a remote inode number assigned to the copy associated with the file at the home site, a name under which the copy is saved, and a list of data chunk tuples specifying selected data of the copy to undergo secure deletion.Type: GrantFiled: October 14, 2016Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence C. Blount, Deepak R. Ghuge, Shah Mohammad R. Islam, Sandeep R. Patil, Riyazahamad M. Shiraguppi, Renu Tewari
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Patent number: 9811574Abstract: Various of the disclosed embodiments present systems and methods for generating consolidated job postings from disparate originating sources and formats. Applying an Extraction Transform Load (ETL) framework to the incoming data, a parallel and asynchronous as well as scalable approach to distributing job posting information is presented. “Extraction” may involve the recognition of salient information in the disparate formats (e.g., in employment listings on company webpages). During “transformation”, the information may be reformatted into a universal format or into a format suitable for use at a given destination system. During “loading”, the reformatted data may be supplied to a suitable destination system, e.g., the Application Programming Interface (APIs) of a job board system. Applications in related domains and various optimizations are also discussed.Type: GrantFiled: October 29, 2014Date of Patent: November 7, 2017Assignee: Work4Labs, Inc.Inventors: Maxime Verger-Del Bove, Paul Clais, Olivier Le Floch
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Patent number: 9811283Abstract: A system includes: input-output devices including a first input-output device having a first input-output characteristic and a second input-output device having a second input-output characteristic, and a control device. The control device is configured to when jobs include a first job in which a ratio between reading and writing included in the first job is more suitable for the first input-output characteristic than the second input-output characteristic, a second job having a dependency relationship with the first job and in which a ratio between reading and writing included in the second job is more suitable for the second input-output characteristic than the first input-output characteristic, and a third job having a dependency relationship with neither the first job nor the second job, control submitting order of the jobs into nodes, coupling the input-output devices and the nodes, and copying of execution result data by the jobs between the input-output devices.Type: GrantFiled: February 25, 2016Date of Patent: November 7, 2017Assignee: FUJITSU LIMITEDInventor: Takatsugu Ono
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Patent number: 9792059Abstract: An apparatus, method and computer program in a distributed cluster storage network comprises storage control nodes to write data to storage on request from a host; a forwarding layer at a first node to forward data to a second node; a buffer controller at each node to allocate buffers for data to be written; and a communication link between the buffer controller and the forwarding layer at each node to communicate a constrained or unconstrained status indicator of the buffer resource to the forwarding layer. A mode selector selects a constrained mode of operation requiring allocation of buffer resource at the second node and communication of the allocation before the first node can allocate buffers and forward data, or an unconstrained mode of operation granting use of a predetermined resource credit provided by the second to the first node and permitting forwarding of a write request with data.Type: GrantFiled: July 20, 2016Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carlos F. Fuente, John E. Lindley, William J. Scales
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Patent number: 9794316Abstract: Disclosed are a method and a system for content management, the method comprises: a master control server allocates, for contents to be issued, one or more merged file blocks and a storage location of each content in its corresponding merged file block according to a received content issue request, and sends to a media storage-and-forward server a content download request containing one or more names of the one or more merged file block and the storage location of each content; the media storage-and-forward server downloads the content to be issued according to the content download request, and stores each downloaded content in the corresponding storage location of the corresponding merged file block. The solutions save the storage space of the file system, improve the storage efficiency of the file system, and reduce the storage cost of the file system.Type: GrantFiled: August 27, 2013Date of Patent: October 17, 2017Assignee: XI'AN ZHONGXING NEW SOFTWARE CO. LTDInventor: Li Dong
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Patent number: 9792051Abstract: An input output scheduler. The scheduler runs in user space and is associated with one core of a multi-core central processing unit. Applications submit input output commands to the scheduler, which queues the input output commands and submits them in batches to a mass storage device. The input output scheduler may include a plurality of command queues with different batching strategies configured to provide, e.g., different performance characteristics as measured, for example, by latency or input output throughput.Type: GrantFiled: April 29, 2016Date of Patent: October 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Fei Liu, Yang Seok Ki, Aakanksha Pudipeddi
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Patent number: 9779003Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include detecting, by a storage system, a change in a mapping of a logical volume to one or more host ports of a host computer communicating with the storage system via a storage area network (SAN). Subsequent to detecting the change, first and second input/output (I/O) requests for the logical volume are received from a given host port, and a first unit attention message is conveyed to the given host port in response to the first I/O request. A second unit attention message is conveyed to the given host port upon determining that the storage system received the second I/O request within a specific time period commencing upon receiving the first I/O request. However, the second I/O request can be performed if the storage system received the second I/O request subsequent to the specific time period.Type: GrantFiled: June 12, 2013Date of Patent: October 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oren Li-On, Orit Nissan-Messing, Assaf Nitzan, Eyal Perek
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Patent number: 9720601Abstract: A technique for load balancing uses heuristic-based algorithms with respect to input/output (I/O) latency of workloads destined to storage devices, e.g., solid state drives (SSDs), of a storage array attached to a storage system. Illustratively, “front-end” requests received from a host result in a back-end workload as those requests are processed by a storage I/O stack of the storage system and stored on the storage array. Accordingly, the technique maintains a consistent latency for the host requests (front-end) to control latency for the back-end workload. The load balancing technique illustratively load balances fixed (back-end) workloads having similar I/O sizes and I/O patterns. Illustratively, the technique balances the workloads across a plurality of storage ports over one or more I/O paths to the SSDs. Access to the SSDs may then be distributed among the storage ports.Type: GrantFiled: February 11, 2015Date of Patent: August 1, 2017Assignee: NetApp, Inc.Inventors: Anish Gupta, Samiullah Mohammed, Jamie Nguyen, Hung Lu
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Patent number: 9710302Abstract: According to one exemplary embodiment, a method for dynamically timing out a first process within a plurality of suspended processes is provided. The method may include determining that a second process is attempting to suspend. The method may also include determining if a number of suspended processes plus one is less than a threshold value. The method may then include selecting the first process within the plurality of suspended processes to prematurely time out based on determining that the number of suspended processes plus one is not less than the threshold value. The method may further include timing out the selected first process. The method may also include suspending the second process.Type: GrantFiled: November 24, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Andrew P. Bates, Fraser P. Bohm, Pradeep Gohil, Anthony P. Papageorgiou
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Patent number: 9703597Abstract: According to one exemplary embodiment, a method for dynamically timing out a first process within a plurality of suspended processes is provided. The method may include determining that a second process is attempting to suspend. The method may also include determining if a number of suspended processes plus one is less than a threshold value. The method may then include selecting the first process within the plurality of suspended processes to prematurely time out based on determining that the number of suspended processes plus one is not less than the threshold value. The method may further include timing out the selected first process. The method may also include suspending the second process.Type: GrantFiled: April 27, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Andrew P. Bates, Fraser P. Bohm, Pradeep Gohil, Anthony P. Papageorgiou
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Patent number: 9684494Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: GrantFiled: March 16, 2015Date of Patent: June 20, 2017Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
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Patent number: 9672067Abstract: A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.Type: GrantFiled: April 27, 2015Date of Patent: June 6, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ye-Jyun Lin, Hsiang-Pang Li, Shang-Xuan Zou, Chia-Lin Yang
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Patent number: 9524307Abstract: Systems and methods perform asynchronous error checking on a structured document. In accordance with the systems/methods, a first thread, such as a main application thread of a document editor, parses the document to identify one or more new elements included therein and create copies of the one or more new elements. A second thread, such as a background thread, applies error checking to the copies of the one or more new elements to generate error results corresponding to the one or more new elements. The first thread the uses the error results to indicate errors in association with the one or more new elements.Type: GrantFiled: March 14, 2013Date of Patent: December 20, 2016Assignee: Microsoft Technology Licensing, LLCInventor: Mikhail Arkhipov
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Patent number: 9477586Abstract: Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.Type: GrantFiled: November 3, 2011Date of Patent: October 25, 2016Assignee: Altera CorporationInventors: Sam Hedinger, Philip Clarke
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Patent number: 9477595Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.Type: GrantFiled: September 14, 2015Date of Patent: October 25, 2016Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Ajith Kumar
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Patent number: 9378052Abstract: Improved techniques of implementing range lock involve granting a sleeping thread access to an address range when no conflicts exist with earlier pending requests as well as with already granted requests. Along these lines, a current child thread that has a conflict with a parent thread that currently holds a range lock on a range of bytes during a read/write operation will be awoken from waiting state when the parent thread has completed its access and releases its lock. In response, the processor compares the range to which the current child thread request access with the ranges to which other sleeping threads request access. However, the comparisons are only performed in connection with (i) requests that arrived prior to the current child thread and (ii) other granted requests.Type: GrantFiled: March 31, 2015Date of Patent: June 28, 2016Assignee: EMC CorporationInventors: Ruiling Dou, Feng Zhang, Ying Hu, Gong Chen, Hao Pan
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Patent number: 9323663Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.Type: GrantFiled: June 26, 2013Date of Patent: April 26, 2016Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Ajith Kumar
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Patent number: 9256521Abstract: A controller comprising a transport layer, an internal memory, and a link list manager block. The internal memory stores pending instruction entries. The link list manager block is configured to read instructions stored in an external memory, update an active vector, the active vector for storing indications of instructions from the external memory; update the pending instruction entries in the internal memory; and update the instructions stored in the external memory. The link list manager block configured to dispatch a instruction from the pending instruction entries in the internal memory to the transport layer.Type: GrantFiled: November 3, 2011Date of Patent: February 9, 2016Assignee: PMC-Sierra US, Inc.Inventors: Raymond Lam, Ivy Chow
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Patent number: 9224077Abstract: A control apparatus includes an operation section, a correction section, and a controller. The operation section performs an operation for forming an image having a predetermined density. The correction section corrects a value of the density. In a case where an image formation condition is switched from a first image formation condition to a second image formation condition, when image formation under the second image formation condition is to be performed on at least a predetermined number of recording media or to be performed for at least a predetermined period, the controller performs control so that the correction section executes a process of correcting the value. When the image formation is not to be performed on at least the predetermined number of recording media or not to be performed for at least the predetermined period, the controller performs control so that the correction section does not execute the process.Type: GrantFiled: February 9, 2012Date of Patent: December 29, 2015Assignee: FUJI XEROX CO., LTD.Inventor: Satoshi Tanaka
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Patent number: 9223579Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.Type: GrantFiled: September 10, 2014Date of Patent: December 29, 2015Assignee: Intel CorporationInventor: Ramakrishna Saripalli
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Patent number: 9182923Abstract: The storage system includes a progress status detection unit that detects respective progress statuses representing proportions of the amounts of processing performed by respective processing units to the amount of processing performed by the entire storage system, each of the processing units being implemented in the storage system and performing a predetermined task; a target value setting unit that sets target values of processing states of the processing units, based on the detected progress statuses of the respective processing units and ideal values of the progress statuses which are preset for the respective processing units; and a processing operation controlling unit that controls the processing states of the processing units such that the processing states of the processing units meet the set target values.Type: GrantFiled: August 25, 2011Date of Patent: November 10, 2015Assignee: NEC CORPORATIONInventors: Piotr Skowron, Marek Biskup, Lukasz Heldt, Cezary Dubnicki
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Patent number: 9143403Abstract: Example embodiments relate to autonomous metric tracking and adjustment. In some examples, a computing node may include a processor to run a main operating system and an application that runs on top of the main operating system. The computing node may include a hardware-level controller that dynamically adjusts individual hardware components of the computing node via control signals that do not pass through the main operating system. The adjustments may be based on a target metric from a scheduling service external to the computing node and individual performance metrics from the computing node.Type: GrantFiled: June 19, 2013Date of Patent: September 22, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Paolo Faraboschi, Dejan S Milojicic, Dwight L Barron
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Patent number: 9128796Abstract: A system and method for updating an accessory device are described. A software upgrade for upgrading an accessory device is received from a wireless network at a wireless device. In response, it is automatically determined at the wireless device whether the accessory device is in communication with the wireless device. Upon determining that the accessory device is in communication with the wireless device, the software upgrade is forwarded from the wireless device to the accessory device to enable upgrade of the accessory device according to the software upgrade.Type: GrantFiled: August 31, 2012Date of Patent: September 8, 2015Assignee: Cellco PartnershipInventors: Monica Chitre, Yoganand Rajala
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Patent number: 9098209Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.Type: GrantFiled: October 27, 2013Date of Patent: August 4, 2015Assignee: Rambus Inc.Inventors: Liji Gopalakrishnan, Vlad Fruchter, Lawrence Lai, Pradeep Batra, Steven C. Woo, Wayne Frederick Ellis
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Patent number: 9098274Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.Type: GrantFiled: December 3, 2009Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Ryan D. Wells, Ohad Falik, Mary Jean Allarey
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Patent number: 9092218Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.Type: GrantFiled: June 8, 2011Date of Patent: July 28, 2015Assignee: Intel CorporationInventors: Ryan D. Wells, Ohad Falik, Mary Jean Allarey
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Patent number: 9092354Abstract: According to one embodiment, storage device, a CRC generator device and a CRC generation method includes A storage device includes: a storage unit 1, a data reading unit 2, and a CRC generation device 3. The CRC generation device 3 includes a CRC generation unit 31 generates a first CRC value; an ECC unit 32 detects an error sequence in a reverse order; a CRC reverse operation unit 33 calculates a CRC reverse operation result for the error sequence; a CRC generation shift register group 34 to retain CRC conversion information; an error sequence CRC generation unit 35 obtains a second CRC value; and an XOR unit 36 obtains a CRC value for an errorless recording sequence.Type: GrantFiled: September 5, 2013Date of Patent: July 28, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yosuke Kondo, Kenji Yoshida
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Patent number: 9053330Abstract: A method and devices for providing secure data backup from a mobile communication device to an external computing device is described. In one embodiment, there is provided a method of backing up data from a mobile communication device to an external computing device, the mobile communication device being in communication with the external computing device, the method includes: receiving a request to backup one or more data items stored on the mobile communication device; encrypting a data item using an encryption key stored in a protected memory of the mobile communication device; and transferring the encrypted data item to the external computing device for storage by the external computing device. A method of restoring backup data to a mobile communication device from an external computing device is also provided, as are mobile communication devices and computing devices configured for implementing the backup and restore operations.Type: GrantFiled: June 21, 2013Date of Patent: June 9, 2015Assignee: BlackBerry LimitedInventors: Michael Kenneth Brown, Andrew Douglas Bocking, Scott William Totzke, David Francis Tapuska, Ronald Scotte Zinn, Maxime Matton, Michael Thomas Hardy, George Dos Santos, Christopher James Runstedler
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Patent number: 9043512Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.Type: GrantFiled: January 7, 2015Date of Patent: May 26, 2015Assignee: Google Inc.Inventor: Arif Merchant
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Patent number: 9032104Abstract: A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.Type: GrantFiled: September 16, 2013Date of Patent: May 12, 2015Assignee: Cradle IP, LLCInventors: Moshe B. Simon, Erik P. Machnicki, David A. Harrison
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Patent number: 9032377Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: GrantFiled: June 2, 2013Date of Patent: May 12, 2015Assignee: Rocketick Technologies Ltd.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
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Patent number: 9025194Abstract: To reduce power consumption, a data transmission apparatus comprises: a memory; a timing instruction unit which indicates a start timing of outputting data from the memory; a first interface which outputs data stored in the memory according to the timing instruction unit; a second interface which transfers the data from the first interface to a buffer; and a control unit which issues a command to perform transition of the first interface and the second interface to a power saving state based on the data output start timing indicated by the timing instruction unit, and a sum of a time required to perform transition of the first interface and the second interface to the power saving state and a time required to return from the power saving state.Type: GrantFiled: November 14, 2011Date of Patent: May 5, 2015Assignee: Canon Kabushiki KaishaInventor: Koichi Ueda
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Patent number: 9026682Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: December 13, 2012Date of Patent: May 5, 2015Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 9021147Abstract: A method and system for command queuing in disk drives may improve performance by queuing multiple commands and sequentially executing them automatically without firmware intervention. The method may use a number of queues, e.g., a staging queue for commands to be executed, an execution queue for commands currently being executed, and a holding queue for commands which have been executed but have not received a status report from a host. With the pipelined nature of queued commands, when data requested by one command are being sent to the host, the queue logic may already be fetching data for the next command. If an error occurs in the transmission, commands in the queues may backtrack and restart from the point where data were last known to have been successfully sent to the host.Type: GrantFiled: October 4, 2013Date of Patent: April 28, 2015Assignee: Marvell International Ltd.Inventors: Huy Tu Nguyen, William C. Wong, Kha Nguyen, Yehua Yang
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Patent number: 9021158Abstract: A memory device includes a memory array with a plurality of memory elements. Each memory element is configured to store data. The device includes an input/output (I/O) buffer coupled to the memory array. The I/O buffer is configured to receive data from an I/O interface of a memory device controller and write the data to the memory array. The device includes a memory control manager coupled to the memory array. The memory control manager is configured to pause a program operation to the memory array in response to receiving a pause command. The memory control manager is also configured to resume the program operation in response to receiving a resume command.Type: GrantFiled: March 15, 2013Date of Patent: April 28, 2015Assignee: SanDisk Technologies, Inc.Inventors: Jea Woong Hyun, Mark Brinicombe, Hairong Sun, Hao Zhong, John Strasser, Robert Wood
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Patent number: 9021146Abstract: In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.Type: GrantFiled: August 30, 2011Date of Patent: April 28, 2015Assignee: Apple Inc.Inventors: Diarmuid P. Ross, Douglas C. Lee
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Patent number: 9015356Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: GrantFiled: May 2, 2014Date of Patent: April 21, 2015Assignee: Micron TechnologyInventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
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Patent number: 9015389Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.Type: GrantFiled: September 19, 2013Date of Patent: April 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Woong Lee, Hyong-Ryol Hwang
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Patent number: 9003078Abstract: A system and method is described for managing subscriptions between a consumer mobile phone, merchant server, billing server and carrier server. A charge-info method is used for the merchant server to retrieve charge elements from the billing server for constructing a user interface for the consumer mobile phone. An opt-in method is used to confirm a consumer's opt-in for a subscription. A remind-charge method is used to remind the consumer of an upcoming charge on the subscription. A charge method allows the merchant server to charge a user account on a carrier server via the billing server. A cancel method is used for the consumer to cancel the subscription.Type: GrantFiled: March 18, 2013Date of Patent: April 7, 2015Assignee: Boku, Inc.Inventors: John P. Browne, James C. McIntyre, Marcin L. Pawlowski
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Patent number: 9003067Abstract: A method for operating a network with two control devices and at least one peripheral device, wherein each of the control devices, in relation to the peripheral device, is in an active operating state in which it is sending control instructions to the peripheral device or is in an idle operating state in which it is not sending any control instructions to the peripheral device. The control device that is in the active operating state in relation to the peripheral device sends synchronization signals at regular intervals to the other control device and activity signals to the peripheral device. Upon failure of the synchronization signals, the non-active control device checks whether the peripheral device is still receiving activity signals from the active control device. If it is not, the non-active control device assumes control of the peripheral device.Type: GrantFiled: August 10, 2011Date of Patent: April 7, 2015Assignee: Siemens AktiengesellschaftInventors: Herbert Barthel, Reiner Griessbaum, Enrico Ramm
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Patent number: 9003079Abstract: A phone-on-file opt-in method is described. A phone-on-file opt-in request is received at the billing server including a msisdn and a merchant supplied unique consumer identifier. The billing server confirms the phone-on-file opt-in with a consumer device and records a phone-on-file opt-in status as active if the first phone-on-file is confirmed. A charge method includes receiving, at the billing server, a charge API call from a merchant server including at least one identifier and an amount, determining a phone-on-file opt-in status corresponding to the identifier at the billing server and transmitting a request to charge a user account to a carrier server if the phone-on-file opt-in status is active, but not if the phone-on-file opt-in status is inactive, the request including an amount corresponding to the amount received in the charge API call.Type: GrantFiled: June 26, 2013Date of Patent: April 7, 2015Assignee: Boku, Inc.Inventors: John P. Browne, Pankhudi Pankhudi, Natalya Elkanova, James C. McIntyre, Annie Minh Ma
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Patent number: 8996764Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.Type: GrantFiled: May 12, 2014Date of Patent: March 31, 2015Assignee: Marvell International Ltd.Inventor: Martin White
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Patent number: 8984172Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load based on fill percentages of storage media devices.Type: GrantFiled: December 6, 2013Date of Patent: March 17, 2015Assignee: Concurrent Ventures, LLCInventors: Jesse D. Beeson, Jesse B. Yates
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Patent number: 8984208Abstract: An input/output (I/O) scheduling device comprises a plurality of trans-descriptor operators each corresponding to one of a plurality of hosts and configured to sustain a trans-descriptor and transmit the trans-descriptor to a hardware module, a transmitting scheduler configured to schedule transmission of trans-descriptors through communication with the plurality of trans-descriptor operators, and a receiving scheduler configured to schedule reception of trans-descriptors through communication with the trans-descriptor operators.Type: GrantFiled: February 8, 2012Date of Patent: March 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Kyoung Back Lee
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Patent number: 8972616Abstract: A method of prioritizing data transmissions between a SCSI initiator and a SCSI target in a network system with DCB enabled switches. The method includes a switch controller detecting a SCSI set priority response transmitted via a first pair of switch ports from a SCSI target to a SCSI initiator, which communicate SCSI messaging and transmit I/O data via the first pair of switch ports. In response to detecting the SCSI set priority response, the priority data established by the SCSI target is retrieved and, based on the retrieved priority data, the switch controller autonomously sets the DCB priority for the first pair of switch ports to a first DCB priority value correlated to the retrieved priority data. Transmission of the I/O data between the SCSI initiator and the SCSI target is supported with a priority of the first pair of switch ports set to the first DCB priority value.Type: GrantFiled: March 15, 2013Date of Patent: March 3, 2015Assignee: Dell Products, L.P.Inventors: Gaurav Chawla, Rajesh Narayanan, Shyamkumar T. Iyer
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Patent number: 8972615Abstract: A computer program product is provided for performing: obtaining, by a channel subsystem, a transport command word (TCW) specified by an operating system, the TCW comprising an address of a transport services request block (TSRQB) and an address of a transport services response block (TSRSB); obtaining the TSRQB; building at least one command request based on the TSRQB, and sending the at least one command request from the channel subsystem to at least one network entity, the at least one command request including at least one of a fiber-channel generic services (FC-GS) request, a fiber-channel link services (FC-LS) request, and a fiber-channel link-level function (FC-SB) request; receiving a response to the at least one command request from the at least one network entity; and storing the response to the TSRSB based on the address of the TSRSB obtained from the TCW.Type: GrantFiled: December 7, 2012Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Daniel F. Casper, Patricia G. Driever, John R. Flanagan, Louis W. Ricci, Gustav E. Sittmann, III
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Patent number: 8972710Abstract: The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network device driver is loaded during a machine boot, where the bus-to-network device driver is capable of sending machine bus commands over a network, providing access to the network for a network device driver, and distinguishing between received responses to the machine bus commands and other network traffic corresponding to the network device driver. Loading of the bus-to-network device driver can occur in response to an operating system load of bus drivers. For example, the bus-to-network device driver can be an iSCSI driver, and the operating system load of bus drivers can be the operating system load of SCSI drivers.Type: GrantFiled: November 19, 2012Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: David M. Lerner, Dave Matheny, Douglas D. Boom
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Patent number: 8972627Abstract: An apparatus, system, and method are disclosed for managing operations for data storage media. An adjustment module interrupts or otherwise adjusts execution of an executing operation on the data storage media. A schedule module executes a pending operation on the data storage media in response to adjusting execution of the executing operation. The pending operation comprises a higher execution priority than the executing operation. The schedule module finishes execution of the executing operation in response to completing execution of the pending operation.Type: GrantFiled: February 13, 2012Date of Patent: March 3, 2015Assignee: Fusion-io, Inc.Inventors: John Strasser, David Flynn, Robert Wood