Abstract: The disclosure relates to a method for detecting a current comprising: generating a bias current, transmitting the bias current to a feedback stage and a measurement stage connected to the measurement node receiving a current to be measured, slaving a voltage to the measurement node at a constant value by the measurement and feedback stages, transmitting to an output stage, a current circulating in the measurement stage, which depends on the bias current and the current to be measured, and converting a current circulating in the output stage into a voltage.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or GPUs concurrently are described. One or more executables are compiled online from a source having an existing executable for a type of physical compute devices different from the one or more physical compute devices. Dependency relations among elements corresponding to scheduled executables are determined to select an executable to be executed by a plurality of threads concurrently in more than one of the physical compute devices. A thread initialized for executing an executable in a GPU of the physical compute devices are initialized for execution in another CPU of the physical compute devices if the GPU is busy with graphics processing threads.

Abstract: A method of managing a memory by an electronic device is provided. The method includes configuring a swap data amount per unit time, identifying an actual use amount of swap data, and comparing the identified actual use amount of the swap data with the configured swap data amount per unit time.

Abstract: An application program stored in a ROM includes a function lookup data structure in which functions called by the application program have identifiers and memory addresses at which the function is located and can be executed. Upon startup, the function lookup data structure is copied to a RAM as a revised lookup data structure and is compared to a revision lookup data structure also written to that RAM or elsewhere. If the revision lookup data structure contains replacement functions having the same function identifiers but new memory addresses, these new memory addresses are written over the existing addresses in the revised lookup data structure for those replacement functions. The application program refers to the revised lookup data structure to find and execute the functions; thus the original application program on the ROM can continue to be used with revised functions.

Abstract: A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording data into the nonvolatile memory is received from the access device, the memory controller starts recording of data into the nonvolatile memory. When the memory controller receives from the access device a suspension instruction for suspending the recording of data, the memory controller stores suspension information into the nonvolatile memory, the suspension information indicating a suspended position as a position in a recording area of the nonvolatile memory at which the data is being recorded upon reception of the suspension instruction.

Abstract: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.

Abstract: Many of the benefits of solid-state-based storage devices can be obtained, while minimizing the costs associated therewith, by write-throttling solid-state storage media in accordance with empirically derived capabilities. Untested solid-state storage media can be obtained inexpensively due to the lack of waste that is otherwise been inherent in the testing and subsequent discarding of solid-state storage media whose capabilities do not meet stringent manufacturer standards. The untested solid-state storage media is initialized through a testing procedure that empirically identifies capabilities of individual solid-state blocks, or groupings of blocks, within such solid-state storage media. Such empirically obtained capability information is then utilized to throttle the speed at which data is written to the solid-state storage media. Additionally, it can enable binning of individual solid-state blocks, or individual groupings of blocks, into bins that can comprise different performance thresholds.

Abstract: An embodiment may include circuitry to perform option (a) and/or option (b). In option (a), the circuitry may maintain a journal to record information that is related to a transaction that may result in writing to at least one logical address and at least one physical address of the storage. The information may be recorded in the journal via an atomic operation that may be executed prior to recording, at least in part, the information in a data structure that correlates the at least one logical address to the at least one physical address. In option (b), the circuitry may maintain another data structure that indicates a correlation between at least one other physical address and the at least one logical address. The correlation may be valid prior to completion of the transaction, but the correlation may no longer be valid after the completion.

Abstract: A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected.

Abstract: Techniques for use with a processor configured to function as at least a Mapper in a MapReduce system include generating a set of [key, value] pairs by executing a Map function on input data. The set of [key, value] pairs may be stored in a storage system implemented on at least one data storage medium, the storage system being organized into a plurality of divisions with different divisions of the storage system storing [key, value] pairs corresponding to different keys. A first [key, value] pair corresponding to a first key handled by a first Reducer in the MapReduce system and a second [key, value] pair corresponding to a second key handled by a second Reducer in the MapReduce system may both be stored in a first division of the plurality of divisions.

Abstract: A method according to one embodiment includes determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a set of tracks of the extent is presently being accessed. In response to determining that a parameter of the extent exceeds a migration threshold, a destination-tier cache is populated with tracks as they are removed from a read-stack associated with the source-tier and/or a write-stack associated with the source-tier using a predetermined read-to-write ratio. The extent is migrated from the source-tier to the destination-tier.

Abstract: An information recording device comprises a memory component configured to hold data, a first file system controller configured to manage data held in the memory component on the basis of a first file name formed by a first code, and a wireless component configured to send and receive wireless signals. The first file system controller receives, from an access device connected to the information recording device, the first file name and a second file name that corresponds to the first file name and is formed by a second code that is different from the first code, identifies specific data having the first file name out of the data held in the memory component, and sends the second file name and the specific data to another information recording device connected via the wireless component.

Abstract: A storage module may include a non-volatile memory module and a controller that communicates with the non-volatile memory module using a communications bus. In response to receipt of a host command, the controller may generate one or more sets of context commands for communication of data on the communications bus between the controller and an area of memory. The controller may execute the sets of context commands in a cache sequence. During execution of the context commands in the cache sequence, the controller may determine an opportunity window that occurs after execution of a context command of a prior set and before execution of a context command of a current set, during which the controller may utilize the communications bus.

Abstract: The present disclosure includes apparatuses and methods related to identifying an extremum value using sensing circuitry. An example method can include determining a location of an extremum value of a set of N data values stored as vectors in a memory array. A number of operations to determine the location of the extremum value can remain constant with respect to a value of N. The method can include determining the value of the extremum by reading memory cells coupled to the sense line based on the determined location of the extremum value.

Abstract: The embodiments described herein methods and devices that enhance the endurance of a non-volatile memory (e.g., flash memory). The method includes obtaining, for each of the plurality of die, an endurance metric. The method also includes sorting the plurality of die into a plurality of die groups based on their corresponding endurance metrics, where each die group includes one or more die and each die group is associated with a range of endurance metrics. In response to a write command specifying a set of write data, the method further includes writing the write data to the non-volatile memory by writing in parallel subsets of the write data to the one or more die assigned to a single die group of the plurality of die groups.

Abstract: A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.

Abstract: A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method.

Abstract: A non-volatile storage subsystem is described which identifies performance-sensitive commands and heterogeneous performance characteristics of portions of a non-volatile storage media, and matches the performance sensitivity of the commands with an available physical write address corresponding to performance characteristics appropriate for the performance sensitivity of the command. A command can be considered performance sensitive if it originates from a host or a preferred host among a plurality of hosts, or if the command designates a frequently accessed logical address. Performance characteristics of the storage device can be determined by physical architectures of the storage media such as the distance from the axial center of a disk media, or the architecture technology of a solid-state array. Performance characteristics can also be determined dynamically and heterogeneous performance can be encouraged by internal maintenance policies of the subsystem.

Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.

Abstract: Improved data management systems for managing and maintaining unstructured data in a computing system environment. Data content is associated with particular types of metadata to create data objects. In certain examples, the metadata is stored in various fields of the data objects, certain fields being designated as permanently read-only after their creation. Such fields can include, for instance, a unique identifier, a type of content and a classification governing copy permissions relating to the data object. Data objects, or didgets, can be grouped into logical containers referred to as chambers, which are further grouped by common control elements or attributes into domains. Chambers within a particular domain can generally freely share information therebetween, including copies of various types of didgets. A control program, or didget manager, in each domain manages the creation of didgets and subsequent operations directed thereto.

Abstract: A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102A) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102A) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.

Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.

Abstract: The present invention relates to the field of the management of memory writes to an information processing device and more precisely to a method of writing a set of data in a unitary and coherent manner. The invention, although of more general scope, applies more particularly in the field of chip cards. There is described a method of writing one or more data to the memory of an information processing device which comprises a step of copying a so-called original memory block comprising the data to be written to a so-called backup memory block. The data writing step is then carried out in the original memory block or in the backup memory block. It is then always possible to return if necessary to the values of the original data if the writing phase fails.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.

Abstract: A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.

Abstract: A data programming circuit is provided. A one-time-programmable (OTP) stores a first version of encoding data corresponding to a first version of a read-only memory (ROM) code. A control unit stores a second version of the ROM code into the OTP memory, wherein the control unit obtains a matching table according to the first version of the encoding data and the second version of the ROM code. The control unit obtains a first data segment of the first version of the encoding data and a second data segment of the second version of the ROM code that have the same content, according to the matching table. The control unit encodes the second data segment as a specific address, and the specific address points to the first data segment of the first version of the encoding data in the OTP memory.

Abstract: A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode.

Abstract: The present disclosure relates to a method and system for mapping cache lines to a row-based cache. In particular, a method includes, in response to a plurality of memory access requests each including an address associated with a cache line of a main memory, mapping sequentially addressed cache lines of the main memory to a row of the row-based cache. A disclosed system includes row index computation logic operative to map sequentially addressed cache lines of a main memory to a row of a row-based cache in response to a plurality of memory access requests each including an address associated with a cache line of the main memory.

Abstract: Systems and methods providing a versioning feature in a storage system may allow the versioning feature to be toggled on and/or off during operation. Access operations targeting data objects stored in the system (e.g., delete and store type operations) may behave differently depending on whether versioning is (or has ever been) enabled for the storage system or a storage bucket thereof, or is not (or has never been) enabled for the storage system or storage bucket. For example, if versioning is off or suspended, a store operation may overwrite existing data. However, if versioning is enabled, a store type operation may create and store a new, unique object. If versioning has never been enabled, a delete operation may delete a stored object. However, if versioning has ever been enabled, a delete operation may create a new, unique delete marker object and may or may not delete any objects or data.

Abstract: A control circuit includes a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the ROM address corresponding to said time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to said time point.

Abstract: Systems and methods provide an efficient method for executing transactions on a storage device (e.g., a disk or solid-state disk) by using special support in the storage device for making a set of updates atomic and durable. The storage device guarantees that these updates complete as a single indivisible operation and that if they succeed, they will survive permanently despite power loss, system failure, etc. The storage device performs transaction (e.g., read/write) operations directly at storage device controllers. As a result, transactions execute with lower latency and consume less communication bandwidth between the host and the storage device. Additionally, a unique interface is provided which allows the application to manage the logs used by the hardware.

Abstract: Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.

Abstract: A method includes implementing, with a memory of a computing device, a memory controller of the memory of the computing device, a storage device coupled to the computing device and/or an external device coupled to the computing device, a scheme for detecting an overlap between a first address range and a second address range. The first address range includes a first starting address and a first ending address, and the second address range includes a second starting address and a second ending address. The method also includes reducing a number of comparators utilized in the address range overlap detection through solely determining whether the first starting address is within the second address range or the second starting address is within the first address range.

Abstract: A method for selectively placing cache data, comprising the steps of (A) determining a line temperature for a plurality of devices, (B) determining a device temperature for the plurality of devices, (C) calculating an entry temperature for the plurality of devices in response to the cache line temperature and the device temperature and (D) distributing a plurality of write operations across the plurality of devices such that thermal energy is distributed evenly over the plurality of devices.

Abstract: In a three-dimensional nonvolatile memory, physical levels in blocks are zoned and different zones store different numbers of bits per cell so that different blocks have different data capacities. Block data capacities are calculated and recorded, and may be updated as data capacities change. User data is mapped to blocks according to their respective data capacities.

Abstract: A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip.

Abstract: A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an LIO line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (I/O) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. If the page-size information is the first information, the LIO line switching circuit generates the first and second selection signals using a row address, and if the page-size information is the second information, the LIO line switching circuit generates the first and second selection signals using a column address.

Abstract: A control apparatus includes a signal processing module. The signal processing module includes a field programmable gate array and a volatile memory. The volatile memory is configured to store configuration information of the field programmable gate array. The field programmable gate array has access to the volatile memory after a configuration of the field programmable gate array.

Abstract: Methods and apparatus related to on-the-fly performance adjustment techniques for solid state storage devices are described. In one embodiment, a controller logic controls access to one or more non-volatile memory devices. The controller logic causes a change in an operational frequency of one or more of: the controller logic, a bus that couples the one or more non-volatile memory devices to the controller logic, and one or more of the one or more non-volatile memory devices. Also, the controller logic is capable of causing the change in the operational frequency in response to a command. Furthermore, changing power limits is made possible to scale solid state storage device performance based on system capabilities. Other embodiments are also disclosed and claimed.

Abstract: A method and system for code storage using volatile memory are disclosed. In a first aspect, the method comprises providing a system on a chip (SOC) that includes at least one volatile memory. The method includes coupling a portable power source to the SOC, wherein the portable power source powers the at least one volatile memory with minimal leakage. The method includes storing updatable code on the at least one volatile memory. In a second aspect, the system comprises a system on a chip (SOC) and at least a Static Random-Access Memory (SRAM) coupled to the SOC with updatable code stored therein. The system includes a portable power source coupled to the SOC, wherein the portable power source powers the SRAM with minimal leakage.

Abstract: A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.

Abstract: A method, system, and apparatus for improving performance when retrieving data from one or more storage media. Files to be stored on the one or more storage media are classified into a ranking of different sets. Differences in retrieval value of different regions of the one or more storage media are exploited by selecting which files to store in which regions. For example, files that have a higher classification are stored in regions with faster retrieval values. The files can be classified based on frequency of access. Thus, files that are more frequently accessed are stored in regions that have a faster retrieval value. The files can be classified by another measure such as priority. For example, the classification for some or all of the files can be based on user-assigned priority. The classification may be based on events or data grouping.

Abstract: A memory system according to at least one example embodiment stores meta data in a cache register when the memory system enters a standby mode. Therefore, the memory system may reduce power consumption in the standby mode, and/or rapidly perform a mode switch.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for conditional iteration. A method includes receiving a request comprising a condition. A method includes checking an address mapping structure for entries satisfying a condition for a request. A method includes providing a result for a request based on one or more entries satisfying a condition for a request.

Abstract: A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state, and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD are provided. The method can include includes gathering at least two workload data items related with to a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device, and a controller configured to receive a write command from a host and program and to write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.