Parallel Caches Patents (Class 711/120)
  • Patent number: 9529759
    Abstract: Multipath I/O in a computer system includes: receiving asynchronously, for a single I/O operation by a memory controller from a plurality of I/O adapters, a request to access a memory page, where each request to access the memory page includes an adapter-specific tag; and for each request received by the memory controller: determining, by the memory controller, whether an adapter-specific tag has been assigned to the memory page; if an adapter-specific tag has not been assigned to the memory page: assigning, by the memory controller, the received adapter-specific tag to the memory page; and allowing, by the memory controller, access to the memory page; and if an adapter-specific tag has been assigned to the memory page, granting access to the memory page only when the received adapter-specific tag is the adapter-specific tag assigned to the memory page.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Hart, Anil Kalavakolanu, James A. Pafumi, Vani D. Ramagiri, Evelyn T. Yeung
  • Patent number: 9524171
    Abstract: A split level history buffer in a central processing unit is provided. A history buffer is split into a first portion and a second portion. An instruction fetch unit fetches and tags instructions with unique tags. A register file stores tagged instructions. An execution unit generates results for tagged instructions. A first instruction is fetched, tagged, and stored in an entry of the register file. A second instruction is fetched and tagged, and then evicts the first instruction from the register file, such that the second instruction is stored in the entry of the register file. Subsequently, the first instruction is stored in an entry in the first portion of the history buffer. After a result for the first instruction is generated, the first instruction is moved from the first portion of the history buffer to the second portion of the history buffer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 9495300
    Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Adam B. Collura
  • Patent number: 9491099
    Abstract: A method and a system embodying the method for information lookup request processing at a look-aside processor unit entailing storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet is a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a method and a system embodying the method for exception packet processing at a look-aside processor unit entailing storing at least one received lookup transaction request in a first buffer; receiving a packet; determining that the received packet is an exception packet; and associating the exception packet with one of the at least one stored lookup transaction request in accordance with an identifier of the first buffer is disclosed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Cavium, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Steven Craig Barner, Richard Eugene Kessler
  • Patent number: 9483502
    Abstract: A computational processing device includes: a computational-processor that outputs access requests to a storage device; a plurality of request-holding-units that respectively hold access requests output by the computational processor according to individual access types, the access types being types of access requests; an arbitration-unit that arbitrates access requests held in the plurality of request holding units; a buffer-unit that includes a plurality of entries that hold data; and a buffer-controller that causes one of the plurality of entries to hold data output by the storage device in response to an access request arbitrated by the arbitration unit, on the basis of a result of comparing, for each access type, a count value that counts, for each access type, the number of entries holding data from among the plurality of entries against a maximum value for the number of entries made to hold data for each access type.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: November 1, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koichi Onodera, Shuji Yamamura, Toru Hikichi
  • Patent number: 9477600
    Abstract: A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: October 25, 2016
    Assignee: ARM LIMITED
    Inventors: Jamshed Jalal, Mark David Werkheiser, Brett Stanley Feero, Michael Alan Filippo
  • Patent number: 9418007
    Abstract: In response to execution in a memory transaction of a transactional load instruction that speculatively binds to a value held in a store-through upper level cache, a processor core sets a flag, transmits a transactional load operation to a store-in lower level cache that tracks a target cache line address of a target cache line containing the value, monitors, during a core TM tracking interval, the target cache line address for invalidation messages from the store-in lower level cache until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the target cache line address, and responsive to receipt during the core TM tracking interval of an invalidation message indicating presence of a conflicting snooped operation, resets the flag. At termination of the memory transaction, the processor core fails the memory transaction responsive to the flag being reset.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: August 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Hugh Shen, Derek E. Williams
  • Patent number: 9405644
    Abstract: A redundant automation system having a plurality of automation devices which are connected to one another comprises a plurality of master devices and a slave device. Each of the plurality of automation devices processes a control program in order to control a technical process. At least one of the plurality of automation devices operates as a slave and at least two of the plurality of automation devices, each operates as a master. The plurality of master devices is each configured to run a respective master program and to process processing sections of the respective master program of the respective master program, and the slave device is configured to process a corresponding slave control program for each master control program run by the plurality of master devices and, if one of the plurality of master devices fails, to assume the function of the failed master.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 2, 2016
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Grosch, Jürgen Laforsch, Albert Renschler
  • Patent number: 9389788
    Abstract: The present invention is to provide a reading method of a solid state disk, receiving read requests, pre-checking the blocked state of the request queue in non-volatile memory, registering the reading request to the reading request queue if the request queue is adjudged to be unblocked, buffering the request queue if the reading request queue is adjudged to be blocked, sending a next reading request, and checking and re-sending the buffered reading request at predetermined time length in order to improve the speed of data reading.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 12, 2016
    Assignee: QUANTA STORAGE INC.
    Inventors: Cheng-Yi Lin, Yi-Long Hsiao
  • Patent number: 9385915
    Abstract: A dynamic caching technique adaptively controls copies of data blocks stored within caches (“cached copies”) of a caching layer distributed among servers of a distributed data processing system. A cache coordinator of the distributed system implements the dynamic caching technique to increase the cached copies of the data blocks to improve processing performance of the servers. Alternatively, the technique may decrease the cached copies to reduce storage capacity of the servers. The technique may increase the cached copies when it detects local and/or remote cache bottleneck conditions at the servers, a data popularity condition at the servers, or a shared storage bottleneck condition at the storage system. Otherwise, the technique may decrease the cached copies at the servers.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 5, 2016
    Assignee: NETAPP, INC.
    Inventors: Sethuraman Subbiah, Gokul Soundararajan, Tanya Shastri, Lakshmi Narayanan Bairavasundaram
  • Patent number: 9329930
    Abstract: Aspects disclosed herein include cache memory error detection circuits for detecting bit flips in valid indicators (e.g., valid bits) in cache memory following invalidate operations. Related methods and processor-based systems are also disclosed. If a cache hit results from access to a cache entry following an invalidate operation, a bit flip(s) has occurred in a valid indicator of the cache entry. This is because the valid indicator should indicate an invalid state following the invalidate operation of the cache entry, as opposed to a valid state. Thus, a cache memory error detection circuit is configured to determine if an invalidate operation was performed on the cache entry. The cache memory error detection circuit can cause a cache miss or an error for the accessed cache entry to be generated as a result, even though the valid indicator for the cache entry indicates a valid state due to the bit flip(s).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: John Sumner Ingalls, Brian Michael Stempel, Thomas Philip Speier
  • Patent number: 9170947
    Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Xavier Vera, Matteo Monchiero, Javier Carretero Casado, Enric Herrero, Tanausu Ramirez
  • Patent number: 9110658
    Abstract: Techniques are provided for automatic verification and inference of memory fences in concurrent programs that can bound the store buffers that are used to model relaxed memory models. A method is provided for determining whether a program employing a relaxed memory model satisfies a safety specification. An abstract memory model is obtained of the relaxed memory model. The abstract memory model represents concrete program states of the program as a finite number of abstract states. The safety specification is evaluated for the program on the abstract memory model having the finite number of abstract states. Fence positions at one or more locations can be determined to ensure that the safety specification is satisfied.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael Kuperstein, Martin Vechev, Eran Yahav
  • Patent number: 9081688
    Abstract: In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: July 14, 2015
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr, Shubhendu S. Mukherjee, Arijit Biswas, Adrian C. Moga
  • Patent number: 9083710
    Abstract: Methods and articles of manufacture relating to server load balancing are disclosed. In one aspect, the method includes load balancing a plurality of network packets among a plurality of servers using a minimally disruptive hash table having a plurality of hash table buckets by identifying a plurality of elements, each element corresponding to at least one of the plurality of servers, inserting at least two of the identified plurality of elements into the minimally disruptive hash table so that at least some of the hash table buckets each include one of the plurality of elements, receiving one of the plurality of network packets, determining a hash table index for the received network packet using a hash function, identifying an element stored in a hash table bucket corresponding to the hash table index, and transmitting the received network packet to a server corresponding to the identified element.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: July 14, 2015
    Assignee: GOOGLE INC.
    Inventor: Navindra Yadav
  • Publication number: 20150149713
    Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Nvidia Corporation
    Inventors: Michael Asbury Woodmansee, J. Arjun Prabhu
  • Patent number: 9037800
    Abstract: A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache, implemented as low-cost, solid-state memory, such as flash memory, to store data evicted from the main buffer cache or data read from the primary persistent storage. To prevent bursts of writes to the secondary cache, data is copied from the main buffer cache to the secondary cache speculatively, before there is a need to evict data from the main buffer cache. Data can be copied to the secondary cache as soon as the data is marked as clean in the main buffer cache. Data can be written to secondary cache at a substantially constant rate, which can be at or close to the maximum write rate of the secondary cache.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: May 19, 2015
    Assignee: NetApp, Inc.
    Inventor: Daniel J. Ellard
  • Publication number: 20150134912
    Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 14, 2015
    Inventors: Hiromasa YAMAUCHI, Koichiro YAMASHITA, Takahisa SUZUKI, Koji KURIHARA
  • Publication number: 20150134911
    Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Muralidhar Krishnaprasad, Anil K. Nori, Subramanian Muralidhar
  • Publication number: 20150127907
    Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Inventors: Bahaa Fahim, Samuel D. Strom, Vedaraman Geetha, Robert G. Blankenship, Yen-Cheng Liu, Krishnakumar Ganapathy, Cesar Maldonado
  • Publication number: 20150121008
    Abstract: Disclosed is a system for controlling write actions to a plurality of data storage devices, the system comprising a plurality of write caches, wherein each cache is associated with a set of said data storage devices; and a controller adapted to issue write permissions to said data storage devices, said write permissions including a permission to perform a data destage operation from a cache to a data storage device; wherein each cache has a first performance score expressed as the difference between the number of data destage operations said cache has in flight and the maximum number of data destage actions said cache is permitted to issue in parallel; and wherein the controller is adapted to offer a data destage operation permission to the cache in said plurality of caches associated with the highest first performance score.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 30, 2015
    Inventors: Ian Boden, Geraint North, Lee J. Sanders, David Sherwood
  • Patent number: 9003163
    Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Oracle International Corporation
    Inventors: Pranay Koka, Michael O. McCracken, Herbert D. Schwetman, Jr., David A. Munday, Jose Renau Ardevol
  • Patent number: 8996839
    Abstract: A data storage device is disclosed comprising a non-volatile memory comprising a plurality of sectors. A partition map is evaluated that identifies a partition accessed through a plurality of logical block addresses (LBAs), where each LBA maps to a fraction of a sector. A partition offset is determined for the partition relative to a boundary of one of the sectors. N write commands are received each having a write offset relative to a corresponding sector. When the write offset for X of the N write commands matches the partition offset, at least part of the partition is moved to align at least part of the partition to a boundary of one of the sectors.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: March 31, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Kai Ling Lee, Sang Huynh, Ayberk Ozturk, Billy Rickey, Aznizam Abdullah Salehudin, Robert M. Fallone
  • Patent number: 8996811
    Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Limited
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Patent number: 8972660
    Abstract: A disk subsystem and a data restoration method with which the rise time when the disk subsystem is restored can be shortened. A disk subsystem and data restoration method whereby, when the power of the disk subsystem is shut off, the shared memory management table is saved to non-volatile memory together with the cache data and, when the power of the disk subsystem is restored, the shared memory management table is referenced and the duplex data is assigned by two non-volatile memories and restored to each of two shared memories.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: March 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Iida, Naoki Moritoki
  • Patent number: 8966180
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Publication number: 20150046650
    Abstract: A processor having a streaming unit is disclosed. In one embodiment, a processor includes a streaming unit configured to load one or more input data streams from a memory coupled to the processor. The streaming unit includes an internal network having a plurality of queues configured to store streams of data. The streaming unit further includes a plurality of operations circuits configured to perform operations on the streams of data. The streaming unit is software programmable to operatively couple two or more of the plurality of operations circuits together via one or more of the plurality of queues. The operations circuits may perform operations on multiple streams of data, resulting in corresponding output streams of data.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 12, 2015
    Applicant: Oracle International Corporation
    Inventors: Darryl J. Gove, David L. Weaver
  • Patent number: 8949540
    Abstract: A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Hien M. Le, Alvan W. Ng, Michael S. Siegel, Derek E. Williams, Phillip G. Williams
  • Patent number: 8949537
    Abstract: A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Moritoki, Shohei Asakawa, Takeshi Yamauchi, Suguru Shimotaya
  • Patent number: 8943271
    Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: January 27, 2015
    Assignee: Microsoft Corporation
    Inventors: Muralidhar Krishnaprasad, Anil K. Nori, Subramanian Muralidhar
  • Patent number: 8914391
    Abstract: To provide a method, program, and system for converting graph data to a data structure that enables manipulations in various applications to be reflected in the original graph data. The method uses at least one graph matching pattern to convert at least a part of graph data including nodes and edges to a data structure as an image of a homomorphism thereof. A pattern is provided which includes one representative node variable having a first constraint that at most one node in the graph data matches the representative node variable; the node is prohibited from matching a node variable in another pattern. The method includes the step of performing matching between the graph data and the pattern to obtain a matching result that does not violate constraints including the first constraint, and the step of generating a data structure corresponding to the matching result that does not violate the constraints.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Futoshi Iwama, Hisashi Miyashita, Hideki Tai
  • Patent number: 8909872
    Abstract: A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 9, 2014
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Michael S. Schlansker, Boon Ang, Erwin Oertli
  • Patent number: 8898390
    Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Xiaowei Jiang, Li Zhao, Ravishankar Iyer
  • Publication number: 20140344521
    Abstract: A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted.
    Type: Application
    Filed: February 25, 2013
    Publication date: November 20, 2014
    Applicant: HITACHI, LTD.
    Inventors: Naoki Moritoki, Shohei Asakawa, Takeshi Yamauchi, Suguru Shimotaya
  • Patent number: 8868828
    Abstract: A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Brian L. Bowles, Michael J. Carnevale, Robert E. Galbraith, II, Adrian C. Gerhard, Murali N. Iyer, Daniel F. Moertl, Mark J. Moran, Gowrisankar Radhakrishnan, Rick A. Weckwerth, Donald J. Ziebarth
  • Patent number: 8861011
    Abstract: A print image processing system includes plural logical page interpretation units, a dual interpretation unit, a cache memory, an assignment unit, and a print image data generation unit. The logical page interpretation units interpret assigned logical pages in input print data in parallel. The dual interpretation unit interprets an assigned logical page in the print data or an element to be cached which is included in the logical page. The cache memory stores interpretation results of elements to be cached. The assignment unit assigns logical pages to the dual interpretation unit and the logical page interpretation units. The print image data generation unit generates print image data for the logical pages using the interpretation results output from the logical page interpretation units or the dual interpretation unit and the interpretation results stored in the cache memory. The print image data generation unit supplies the print image data to a printer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 14, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Michio Hayakawa
  • Patent number: 8862826
    Abstract: A method and an apparatus for increasing capacity of cache directory in multi-processor systems, the apparatus comprising a plurality of processor nodes and a plurality of cache memory nodes and a plurality of main memory nodes.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: October 14, 2014
    Inventor: Conor Santifort
  • Patent number: 8856457
    Abstract: In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache synchronization, the system controller includes a cache synchronization unit which monitors an address contention between a preceding request and a subsequent request and a setting unit which sets different monitoring range of the contention between the preceding request and the subsequent request for each capacity of the cache memory in each of the CPU units.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Limited
    Inventors: Yuuji Konno, Hiroshi Murakami
  • Publication number: 20140297957
    Abstract: An operation processing apparatus includes an operation processing unit to perform an operation process using first data administered by the own operation processing apparatus and second data acquired from another operation processing apparatus; a main memory to store the first data; and a control unit to include a storing unit to store status of data indicating whether or not the first data is held by another operation processing apparatus and a indicating unit to indicate a transition between the status in which the first data is held by another operation processing apparatus and the status in which the first data is not held thereby, wherein when the indicating unit indicates that the first data is not held by another operation processing apparatus and a data acquisition request occurs for the first data, the control unit skips a process for referring to the status of use of the first data.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takahiro AOYAGI, Toru HIKICHI
  • Publication number: 20140258620
    Abstract: Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Inventors: Ramadass Nagarajan, Robert G. Milstrey, Michael T. Klinglesmith
  • Patent number: 8832333
    Abstract: According to the embodiment, a memory system includes a first memory which includes a memory cell array and a read buffer, a second memory, a command queue, a command sorting unit, and a data transfer unit. The command sorting unit dequeues commands excluding a later-arrived command whose access range overlaps with an access range of an earlier-arrived command from the command queue. The data transfer unit performs a data preparing process of transferring data that is specified by dequeued read command and is read out from the memory cell array to the read buffer, a first data transfer of outputting the data stored in the read buffer, and a second data transfer of storing data that is specified by dequeued write command in the second memory. The data transfer unit is capable of performing the data preparing process and the second data transfer in parallel.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirokazu Morita
  • Patent number: 8806134
    Abstract: Methods of protecting cache data are provided. For example, various methods are described that assist in handling dirty write data cached in memory by duplication into other locations to protect against data loss. One method includes caching a data item from a data source in a first cache device. The data item cached in the first cache device is designated with a first designation. In response to the data item being modified by a data consumer, the designation of the data item in the first cache device is re-assigned from the first designation to a second designation, and the data item with the second designation is copied to a second cache device.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 12, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventors: Jonathan Flower, Nadesan Narenthiran
  • Patent number: 8799583
    Abstract: A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Jonathan T. Hsieh, Christian Jacobi, Timothy J. Slegel
  • Publication number: 20140173203
    Abstract: In an embodiment, a processor is disclosed and includes a cache memory and a memory execution cluster coupled to the cache memory. The memory execution cluster includes a memory execution unit to execute instructions including non-block memory instructions, and block memory logic to execute one or more block memory operations. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Inventor: Andrew T. Forsyth
  • Patent number: 8751676
    Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
  • Patent number: 8738859
    Abstract: Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Michael K. Gschwind
  • Patent number: 8738886
    Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 8706968
    Abstract: An apparatus, system, and method are disclosed for redundant write caching. The apparatus, system, and method are provided with a plurality of modules including a write request module, a first cache write module, a second cache write module, and a trim module. The write request module detects a write request to store data on a storage device. The first cache write module writes data of the write request to a first cache. The second cache write module writes the data to a second cache. The trim module trims the data from one of the first cache and the second cache in response to an indicator that the storage device stores the data. The data remains available in the other of the first cache and the second cache to service read requests.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: April 22, 2014
    Assignee: Fusion-io, Inc.
    Inventor: David Flynn
  • Patent number: 8706966
    Abstract: A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor core to its L2 cache using an L2 data/address bus. Sharing the n L2 caches with enabled processors means connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: April 22, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Waseem Saify Kraipak, George Bendak
  • Patent number: RE45078
    Abstract: A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the set of data associated with a tag of a subset of the set of tags. The tag portion of an address is compared with the subset of data in the second space in the cache memory in that said subset of data is read when the tag portion of the address and the tag associated with the subset of data match. The tag portion of the address is compared with the set of tags associated with the set of data in the first space in cache memory and the set of data in the first space is read when the tag portion of the address matches one of the sets of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: August 12, 2014
    Inventor: Gautam Nag Kavipurapu