Parallel Caches Patents (Class 711/120)
  • Patent number: 8700862
    Abstract: A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts
  • Patent number: 8695011
    Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, William A. Maron, Ram Raghavan, Satya Prakash Sharma, Mysore S. Srinivas
  • Patent number: 8677371
    Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, William A. Maron, Ram Raghavan, Satya Prakash Sharma, Mysore S. Srinivas
  • Patent number: 8671245
    Abstract: In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part of a data request, where the ID field has a line ID sub-field that represents a line ID value that uniquely identifies a particular cache line (or subset of cache lines) in the master, where the memory returns the line ID value back to the master along with the retrieved data. The master uses the line ID value to identify the cache line into which the retrieved data is to be stored. In this way, the master does not need to maintain a queue of address buffers to retain the addresses for data requests currently being processed, where the size of the queue limits the number of parallel in-service data requests by the master.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: March 11, 2014
    Assignee: LSI Corporation
    Inventor: Eran Dosh
  • Publication number: 20140052917
    Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.
    Type: Application
    Filed: May 10, 2012
    Publication date: February 20, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Pranay Koka, Michael O. McCracken, Herbert D. Schwetman, JR., David A. Munday
  • Patent number: 8656129
    Abstract: An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units, and the third system memory pool is accessible to both the third and fourth processing units. An interconnect couples the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, such that the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventor: William J. Starke
  • Patent number: 8656128
    Abstract: A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy L Guthrie, Charles F. Marino, William J. Starke, Derek E. Williams
  • Patent number: 8626866
    Abstract: A network caching system has a multi-protocol caching filer coupled to an origin server to provide storage virtualization of data served by the filer in response to data access requests issued by multi-protocol clients over a computer network. The multi-protocol caching filer includes a file system configured to manage a sparse volume that “virtualizes” a storage space of the data to thereby provide a cache function that enables access to data by the multi-protocol clients. To that end, the caching filer further includes a multi-protocol engine configured to translate the multi-protocol client data access requests into generic file system primitive operations executable by both the caching filer and the origin server.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: January 7, 2014
    Assignee: NetApp, Inc.
    Inventors: Jason Ansel Lango, Robert M. English, Paul Christopher Eastham, Qinghua Zheng, Brian Mederic Quirion, Peter Griess, Matthew Benjamin Amdur, Kartik Ayyar, Robert Lieh-Yuan Tsai, David Grunwald, J. Chris Wagner, Emmanuel Ackaouy, Ashish Prakash
  • Patent number: 8595437
    Abstract: One embodiment of the present invention sets forth a compression status bit cache with deterministic latency for isochronous memory clients of compressed memory. The compression status bit cache improves overall memory system performance by providing on-chip availability of compression status bits that are used to size and interpret a memory access request to compressed memory. To avoid non-deterministic latency when an isochronous memory client accesses the compression status bit cache, two design features are employed. The first design feature involves bypassing any intermediate cache when the compression status bit cache reads a new cache line in response to a cache read miss, thereby eliminating additional, potentially non-deterministic latencies outside the scope of the compression status bit cache.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: November 26, 2013
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts
  • Publication number: 20130282952
    Abstract: A storage system includes a storage that stores a file; and a plurality of access control devices that control access to the storage and include a cache memory in which the file is stored in blocks, wherein when receiving an update request of a prescribed block and latest data of the prescribed block is not stored in the cache memory of a first access control device, the first access control device among the plurality of access control devices obtains a version number added to the latest data from a second access control device, in which the latest data is stored, among the plurality of access control devices, and wherein the first access control device stores update data that updates the prescribed block in the cache memory of the first access control device and adds a new version number to the update data based on the version number.
    Type: Application
    Filed: March 18, 2013
    Publication date: October 24, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Takeshi MIYAMAE
  • Patent number: 8560795
    Abstract: A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 15, 2013
    Assignees: IMEC, Samsung Electronics Co., Ltd.
    Inventors: Bingfeng Mei, Suk Jin Kim, Osman Allam
  • Publication number: 20130262767
    Abstract: An apparatus for concurrently accessing a primary cache and an overflow cache, comprising a core logic unit configured to perform a first instruction that accesses the primary cache and the overflow cache in parallel, determine whether the primary cache stores a requested data, determine whether the overflow cache stores the requested data, and access a main memory when the primary cache and the overflow cache do not store the requested data, wherein the overflow cache stores data that overflows from the primary cache.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 3, 2013
    Applicant: Futurewei Technologies, Inc.
    Inventors: Iulin Lih, Richard Trauben
  • Patent number: 8539155
    Abstract: Managing cache memories in a computing system comprising multiple cores includes: assigning home cache locations for portions of data stored among caches in a group of caches of respective cores; accessing a first one of the portions of the cached data by sending an access request to a first home core of that first one of the portions of cached data; tracking a history of access for the first one of the portions of cached data; determining whether the tracked history of access for the first one of the portions of cached data exceeds or meets a predetermined condition, and re-assigning a home cache location of the first one of the portions of cached data from the first home core to a second, different home core when the predetermined condition is met or exceeded.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: September 17, 2013
    Assignee: Tilera Corporation
    Inventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
  • Patent number: 8533402
    Abstract: The present invention provides for automatically caching via extensions indices in a technical computing environment one or more portions of a distributed array assigned to other technical computing environments for processing. A set of executable instruction, such as a technical computing program or script, may be executed to run in parallel in multiple technical computing environments. As the technical computing program runs on each technical computing environment, the technical computing program performs operations on the portion of the distributed array assigned to the technical computing environment, which may be stored in a storage location local to the technical computing environment. For example, the technical computing program may perform an operation or calculation that requires data points adjacent or nearby to, but not included in the portion of the distributed array that the technical computing environment is processing or is assigned to process.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: September 10, 2013
    Assignee: The MathWorks, Inc.
    Inventor: Cleve Moler
  • Patent number: 8521963
    Abstract: Managing data in a computing system comprising multiple cores includes: assigning a first set of data to caches within cores of a first subset of fewer than all of the cores in the computing system, and assigning a second set of data to caches within cores of a second subset of at least some remaining cores in the computing system not already assigned; and maintaining cache coherence among caches of respective cores in the first subset in response to data stored in at least one of the cores in the first subset being modified, and maintaining cache coherence among caches of respective cores in the second subset in response to data stored in at least one of the cores in the second subset being modified.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: August 27, 2013
    Assignee: Tilera Corporation
    Inventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
  • Publication number: 20130198457
    Abstract: The entirety or a part of free space of a second storage device included in a host computer is used as a cache memory region (external cache) outside of a storage apparatus. If Input/Output (I/O) in the host computer is Write, a Write request is transmitted from the host computer to a storage apparatus, the storage apparatus writes data associated with the Write request into a main cache that is a cache memory region included in this storage apparatus, and the storage apparatus writes the data in the main cache into a first storage device included in the storage apparatus. The storage apparatus writes the data in the main cache into an external cache included in the host computer. If the I/O in the host computer is Read, the host computer determines whether or not Read data as target data of the Read exists in the external cache. If a result of the determination is positive, the host computer reads the Read data from the external cache.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Applicant: HITACHI, LTD.
    Inventors: Masakazu Kobayashi, Hiroshi Nojima, Takuya Okamoto
  • Patent number: 8489820
    Abstract: A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache, implemented as low-cost, solid-state memory, such as flash memory, to store data evicted from the main buffer cache or data read from the primary persistent storage. To prevent bursts of writes to the secondary cache, data is copied from the main buffer cache to the secondary cache speculatively, before there is a need to evict data from the main buffer cache. Data can be copied to the secondary cache as soon as the data is marked as clean in the main buffer cache. Data can be written to secondary cache at a substantially constant rate, which can be at or close to the maximum write rate of the secondary cache.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: July 16, 2013
    Assignee: NetApp, Inc
    Inventor: Daniel J. Ellard
  • Publication number: 20130138886
    Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.
    Type: Application
    Filed: January 24, 2013
    Publication date: May 30, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Publication number: 20130138865
    Abstract: Certain embodiments of the present disclosure related to systems, methods, and devices for increasing data access speeds. In certain embodiments, a method includes running multiple cache retrieval processes in parallel, in response to a read command. In certain embodiments, a method includes initiating a first cache retrieval process and a second cache retrieval process to run in parallel, in response to a single read command.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 30, 2013
    Applicant: Seagate Technology, LLC
    Inventor: Seagate Technology LLC
  • Patent number: 8447874
    Abstract: A system generates a web page that includes a plurality of embedded data windows. The system receives a request for the web page from a browser and in response generates and displays a frame for the web page on the browser. The frame includes holes for the embedded data windows. The system also receives a data streaming request for each of the embedded data windows and determines if the data streaming requests are thread-safe. For all the data streaming requests that are thread-safe, the system generates a parallel thread to fetch the data for each corresponding data streaming requests. When the data has been fetched for a particular data streaming requests, the data is rendered and streamed to the browser where it is displayed in place of the hole by the browser.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 21, 2013
    Assignee: Oracle International Corporation
    Inventors: Blake Sullivan, Max Starets, Edward J. Farrell
  • Patent number: 8443145
    Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventors: Raj Kumar Jain, Xiao Ni Wei, Pin Xing Lin
  • Patent number: 8443148
    Abstract: Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 26, 2010
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: James R. Vash, Bongjin Jung, Rishan Tan
  • Patent number: 8433772
    Abstract: An approach for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer is presented. The first computer receives a message that includes a shared tape drive identifier, a source port identifier of the second computer, and a reservation status change for the tape drive. Based on the tape drive identifier, the first computer determines that the tape drive is connected to the first computer. The source port identifier is determined to not identify any host bus adapter installed in the first computer. In response to the first computer determining that the reservation status change indicates a reservation or a release of the tape drive for the second computer, the first computer sets the tape drive offline or online, respectively, in an application executing in the first computer.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: April 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Leonard George Jesionowski, Wolfgang Muelller-Friedt, Ulf Troppens
  • Publication number: 20130042067
    Abstract: A method and system are disclosed herein for performing operations on a parallel programming unit in a memory system. The parallel programming unit includes multiple physical structures (such as memory cells in a row) in the memory system that are configured to be operated on in parallel. The method and system perform a first operation on the parallel programming unit, the first operation operating on only part of the parallel programming unit and not operating on a remainder of the parallel programming unit, set a pointer to indicate at least one physical structure in the remainder of the parallel programming unit, and perform a second operation using the pointer to operate on no more than the remainder of the parallel programming unit. In this way, the method and system may realign programming to the parallel programming unit when partial writes to the parallel programming unit occur.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Inventor: Nicholas James Thomas
  • Patent number: 8370579
    Abstract: A pipelined cache memory supports global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a memory hierarchy and a spiral push-back network for pushing out modified values to the backing-store. The cache controller manages application of global commands by propagating individual commands to the tiles. The global commands may provide zeroing, flushing and reconciling of the given tiles. Commands for interrupting and resuming interrupted global commands may be implemented, to reduce halting or slowing of processing while other global operations are in process. A line detector within each tile supports reconcile and flush operations, and a line patcher in the controller provides for initializing address ranges with no processor intervention.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventor: Volker Strumpen
  • Patent number: 8370595
    Abstract: A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Charles F. Marino, William J. Starke, Derek E. Williams
  • Patent number: 8369971
    Abstract: A media system is disclosed that uses preemptive recording of media files to reduce playback latency when media tracks are subsequently selected for playback during the recording process. The media system comprises a primary storage device capable of storing media files and a secondary storage device capable of reading digital media files from a removable storage medium. The system also includes a media player capable of playing media files stored on the primary storage device and a recorder that is connected to read digital media data from the secondary storage device. The recorder stores media files corresponding to the digital media data of the removable storage medium on the primary storage device.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: February 5, 2013
    Assignee: Harman International Industries, Incorporated
    Inventors: Nicholas Murrells, Mark Sears
  • Patent number: 8364922
    Abstract: An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units, and the third system memory pool is accessible to both the third and fourth processing units. An interconnect couples the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, such that the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventor: William J. Starke
  • Patent number: 8352681
    Abstract: Proposed are a highly reliable storage system and its control method capable of accelerating the processing speed of the copy processing seen from the host device. With the storage system and its control method which stores a command issued from a host device in a command queue and executes the command stored in the command queue in the order that the command was stored in command queue, a copy queue is set for temporarily retaining a copy command among the commands issued from the host device in the memory, the copy command among the commands is moved from the host device stored in the command queue to the copy queue and an execution completion reply of copy processing according to the command is sent to the host device as a sender of the command, and the copy command that was moved to the copy queue is executed in the background in the order that the copy command was stored in the copy queue.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kosuke Sakai, Koji Nagata, Yoshiyuki Noborikawa
  • Patent number: 8341353
    Abstract: A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: December 25, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh K. Venkumahanti, Christopher Edward Koob, Lucian Codrescu
  • Patent number: 8341355
    Abstract: Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are identified. Based on a determined mode of operation for the set, the following may be performed: determining if a cache hit occurs in a preferred cache line without accessing other cache lines in the set of cache lines; retrieving data from the preferred cache line without accessing the other cache lines in the set of cache lines, if it is determined that there is a cache hit in the preferred cache line; and accessing each of the other cache lines in the set of cache lines to determine if there is a cache hit in any of these other cache lines only in response to there being a cache miss in the preferred cache line(s).
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jian Li, William E. Speight, Lixin Zhang
  • Publication number: 20120290780
    Abstract: A method of fetching data from a cache begins by preparing to fetch a first set of cache ways for a first data word of a first cache line a using a first thread. Next, in parallel, a second set cache ways for a first data word of a second cache line is prepared to be fetched using a second thread, and data associated with each cache way of the first set of cache ways are fetched using the first thread. Also performed in parallel, data associated with each cache way of the second set of cache ways is fetched using the second thread and a third set of cache ways for a second data word of the first cache line is prepared to be fetched using the first thread based on a selected cache way, the selected cache way selected from the first set of cache ways.
    Type: Application
    Filed: January 27, 2012
    Publication date: November 15, 2012
    Applicant: MIPS Technologies Inc.
    Inventors: Ryan C. Kinter, Thomas Benjamin Berg, Matthias Knoth
  • Patent number: 8312219
    Abstract: Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Michael K. Gschwind
  • Patent number: 8312218
    Abstract: A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 13, 2012
    Assignee: Fujitsu Limited
    Inventor: Masaki Ukai
  • Patent number: 8307105
    Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 6, 2012
    Assignee: Intel Corporation
    Inventors: Steven King, Ram Huggahalli, Xia Zhu, Mazhar Memon, Frank Berry, Nitin Bhardwaj, Amit Kumar, Theodore Willke, II
  • Patent number: 8301842
    Abstract: An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit. The first PLRU vector specifies a first entry from a set of the cache memory specified by the first allocation request. The first vector is a tree of bits comprising a plurality of levels. Toggling logic receives the first vector and toggles predetermined bits thereof to generate a second PLRU vector in response to a second allocation request from a second functional unit generated concurrently with the first allocation request and specifying the same set of the cache memory specified by the first allocation request. The second vector specifies a second entry different from the first entry from the same set. The predetermined bits comprise bits of a predetermined one of the levels of the tree.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: October 30, 2012
    Assignee: VIA Technologies, Inc.
    Inventors: Colin Eddy, Rodney E. Hooker
  • Patent number: 8296516
    Abstract: A first controller has a first CM area having a plurality of first sub-areas, and a second controller has a second CM area having a plurality of second sub-areas. The first controller stores first data in any of the first sub-areas, and in addition, stores a mirror of the first data (first mirror data) in any of the second sub-areas. The first controller manages a pair (an association relationship) of the storage-destination first sub-area of the first data and the storage-destination second sub-area of the first mirror data. Similarly, the second controller stores second data in any of the second sub-areas, and in addition, stores a mirror of the second data (second mirror data) in any of the first sub-areas. The second controller manages a pair (an association relationship) of the storage-destination second sub-area of the second data and the storage-destination first sub-area of the second mirror data.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: October 23, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Yusuke Nonaka, Hideyuki Koseki
  • Patent number: 8255476
    Abstract: A method and system for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer. The first computer receives a message that includes a shared tape drive identifier, a source port identifier of the second computer, and a reservation status change for the tape drive. Based on the tape drive identifier, the first computer determines that the tape drive is connected to the first computer. The source port identifier is determined to not identify any host bus adapter installed in the first computer. In response to the first computer determining that the reservation status change indicates a reservation or a release of the tape drive for the second computer, the first computer sets the tape drive offline or online, respectively, in an application executing in the first computer.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Leonard George Jesionowski, Wolfgang Muelller-Friedt, Ulf Troppens
  • Patent number: 8243313
    Abstract: A method is disclosed. The method includes identifying a received object to be cached, calculating a time to rasterize the object, determining if the rasterize time is greater than a time to reuse a rasterized image of the object, caching the object if the reuse time is greater than the rasterize time and caching the rasterized image of the object if the rasterize time is greater than the reuse time.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: August 14, 2012
    Assignee: InfoPrint Solutions Company LLC
    Inventors: John Varga, Dennis Carney
  • Patent number: 8219761
    Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: July 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ron Bercovich, Odi Dahan, Norman Goldstein, Yehuda Nowogrodski
  • Publication number: 20120166728
    Abstract: Systems and methods for performing parallel multi-level data computations in a storage system are provided. One system includes a memory storing data, multiple caches, and a processor. The processor is configured to perform the method below. One method includes determining the total amount of data in the memory, dividing the amount of data by each cache capacity to determine the number of nodes needed for processing the data in the memory, and automatically creating the nodes. Here, the nodes form a tree structure including multiple levels where the lowest level includes a first number of nodes equal to the amount of data divided by the cache memory capacity. Also, each lowest level node is configured to process an amount of data equal to the cache memory capacity and each level above the lowest level is configured to include one or more nodes for receiving an input from lower level nodes.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vikas K. GARG, Raj GUPTA, Ankur NARANG
  • Patent number: 8195880
    Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Gai, Guy Lynn Guthrie, Hugh Shen, William John Starke
  • Patent number: 8185700
    Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Carlos Madriles Gimeno, Carlos García Quinones, Pedro Marcuello, Jesús Sánchez, Fernando Latorre, Antonio González
  • Patent number: 8161242
    Abstract: Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates that a plurality of non-dedicated cache sets within the cache should operate as spill cache sets or receive cache sets. The cache controller sets the plurality of non-dedicated cache sets to spill an evicted cache line to an associated cache set in another cache in the event of a cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the spill cache sets. The cache controller sets the plurality of non-dedicated cache sets to receive an evicted cache line from another cache set in the event of the cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the receive cache sets.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventor: Moinuddin K. Qureshi
  • Patent number: 8145844
    Abstract: A memory controller includes a write data cache, a read data cache and coherency circuitry. The coherency circuitry manages coherency of data between the write data cache, the read data cache and data stored within a main memory when servicing read requests and write requests received by the memory controller. Write complete signals are issued back to a write requesting circuit as soon as a write request has had its write data stored within the write data cache.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: March 27, 2012
    Assignee: ARM Limited
    Inventor: Alistair Crone Bruce
  • Patent number: 8139592
    Abstract: A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Leo J. Clark, James S. Fields, Jr., Benjiman L. Goodman, William J. Starke, Jeffrey A. Stuecheli
  • Patent number: 8140765
    Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Gai, Guy Lynn Guthrie, Hugh Shen, William John Starke
  • Patent number: 8135910
    Abstract: A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency matcher” may shift the cycle speed to a lower speed upon receiving snoop addresses from the interconnect thereby slowing down the rate at which requests are transmitted to the dispatch pipelines. Each dispatch pipeline is coupled to a sliced cache directory and is configured to search the cache directory to determine if data at the received addresses is stored in the cache memory. As a result of slowing down the rate at which requests are transmitted to the dispatch pipelines and accessing the two sliced cache directories simultaneously, the bandwidth or throughput of the cache directory may be improved.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, William J. Starke, Derek E. Williams, Phillip G. Williams
  • Patent number: 8095733
    Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Guy L. Guthrie, Michael Siegel, William J. Starke, Derek E. Williams
  • Publication number: 20110320719
    Abstract: A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled. Through the use of an on-chip communications network, changes to the shared state data may be communicated quickly and efficiently to multiple threads of execution, enabling those threads to locally update their local copies of the shared state. Furthermore, by avoiding attempts to access a shared memory, the interface to the shared memory is not overloaded with concurrent access attempts, thus preserving memory bandwidth for other activities and reducing memory latency.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs