Abstract: This document describes techniques for cache entry management using read direction detection. In one set of embodiment, the caching system segregates cache entries into two lists. The caching system receives one or more requests to read a range of data from a cache entry in the first list. For each of these read requests, the caching system determines a read direction wherein the read direction is either a forward read or a backward read. The caching system then determines a relationship between the read directions and moves the cache entry from the first list to the second list based on the relationship.

Abstract: A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each associated with one data storage line allocated in the data storage device, and a controller. The controller sets a first number of address tags and configures a first number of data storage lines to serve as a first data storage line with a first data storage line size, and sets a second number of address tags and configures a second number of data storage lines to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.

Abstract: An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.

Abstract: In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.

Abstract: In order to provide a more efficient persistent storage device, one or more long-term storage media are included along with a non-volatile memory. In one embodiment, one portion of the non-volatile memory is used as a write buffer and a read cache for writes and reads to the long-term storage media. Interfaces are provided for controlling the use of the non-volatile memory as a write buffer and a read cache. Additionally, a portion of the non-volatile memory is used to provide a direct mapping for specified sectors of the long-term storage media. Descriptive data regarding the persistent storage device is stored in another portion of the non-volatile memory.

Abstract: A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

Abstract: Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the cache. The cache controller is operable to determine that the first way in the cache is not lockable by the device. The cache controller is also operable to send, to the device, a rejection of the first request. The cache controller is further operable to receive a second request from the device to lock a second way in the cache. The cache controller is operable to lock the second way in the cache in response to the second request.

Abstract: An integrated circuit including a cache and first and second modules. The cache is folded a predetermined number of times. The cache includes arrays and storage elements. Each of the arrays includes respective ones of the storage elements. The arrays store a cache line. The cache line includes segments of data. The segments of data are stored in two or more of the arrays. Each of the segments of data is stored in a corresponding one of the storage elements. The first module receives a first identifier of one of the segments of data and a second identifier of a set of the storage elements. The first module determines an index based on the first and second identifiers. The second module, based on the index, accesses one of the segments of data from the two or more of the arrays and outputs the one of the segments of data.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.

Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract: Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.

Abstract: A flush control apparatus controls a Set Associative cache memory apparatus. A flush control apparatus includes: a tag memory unit associating a tag identifier identifying a tag which associates a plurality of cache lines and tag information representing whether or not the tag is valid. It also includes a line memory unit, a way specification unit and a flush unit which flushes the way specified by the way specification unit.

Abstract: Systems, methods, and apparatuses for implementing selective victimization to reduce power and utilized bandwidth in a multi-level cache hierarchy. Each set of an upper-level cache includes a counter that keeps track of the number of times the set was accessed. These counters are periodically decremented by another counter that tracks the total number of accesses to the cache. If a given set counter is below a certain threshold value, clean victims are dropped from this given set instead of being sent to a lower-level cache. Also, a separate counter is used to track the total number of outstanding requests for the cache as a proxy for bus-bandwidth in order to gauge the total amount of traffic in the system. The cache will implement selective victimization whenever there is a large amount of traffic in the system.

Abstract: Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.

Abstract: An information processing system and computer program storage product for managing objects stored in a shared memory cache. The system includes at least a plurality of cache readers accessing data from the shared memory cache. The system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.

Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

Abstract: A method for managing objects stored in a shared memory cache. The method includes accessing data from the shared memory cache using at least a plurality of cache readers. A system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.

Abstract: A method and corresponding system for providing a skip group rule feature is disclosed. When a search for a key matches a skip group rule in a group of prioritized rules, the search skips over rules having priorities lower than the skip group rule and the search continues to a next group. A convenient example of a compiler rewrites the lower priority rules by subtracting the skip group rule from them. The subtraction includes subtracting range, exact-match, mask, and prefix fields. The rewritten rules appear to a search processor as typical rules. Beneficially, the search processor requires no additional logic to process a skip group rule, skip over lower priority rules, and go on to search a next group of rules. Advantageously, this approach enables any number of skip group rules to be defined allowing for better classification of network data.

Abstract: To prevent an increase in the management information and to increase the capacity of a secondary cache. The cache control device includes: a secondary cache having the data of the data sector and management information; and a primary cache having a digest value calculated from the address of the data and secondary management information. A controller includes: a digest value calculation unit which calculates the digest value of the data when reading out the data; a management information searching unit which searches the management information in the primary cache based on the digest value; and a readout control unit which specifies the data sector in the secondary cache based on the management information and reads out the data.

Abstract: Techniques are described for assigning an application thread to a cache. A newly created application thread may be assigned to a plurality of caches. The cache assignment that optimizes performance may be determined. The newly created application thread may be associated with the determined cache.

Abstract: Devices and methods for accurate reading of data in memory technology prone to drifting memory characteristics. An example device includes a memory array for storing data, and a memory buffer for storing a subset of the data in the memory array. A memory controller is configured to read data from the memory buffer if the data was written to the memory array before a predetermined duration of time, and to read the data from the memory array if the data is at least one of not valid or not available at the memory buffer.

Abstract: Systems and methods for extending the memory resources of a user device to storage resources and/or network resources associated with the user device. The cache and system memory of the user device may be utilized as a cache memory and the storage resources and/or network resources of the user device may be utilized as a storage memory.

Abstract: A cache management unit manages allocation and configuration of a cache memory that is utilized by a multi-threaded processor. In some implementations, the cache management unit is configured to determine a number of active threads being executed by the multi-threaded processor, assign a separate cache unit to each active thread when the number of active threads is equal to a maximum number of active threads supported by the multi-threaded processor, and assign more than one cache unit to an active thread when the number of active threads is less than the maximum number of active threads.

Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.

Abstract: System and method for performing a high-bandwidth memory copy. Memory transfer instructions allow for copying of data from a first memory location to a second memory location without the use of load and store word instructions thereby achieving a high-bandwidth copy. In one embodiment, the method includes the steps of (1) decoding a destination address from a first memory transfer instruction, (2) storing the destination address in a register in the bus interface unit, (3) decoding a source address from a second memory transfer instruction, and (4) copying the contents of a memory location specified by the source memory address to a memory location specified by the contents of the register. Other methods and a microprocessor system are also presented.

Abstract: A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel.

Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.

Abstract: A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.

Abstract: A device includes a memory including ways and a processor in communication with the memory. The processor is configured to execute logic. The logic can monitor a parameter of the processor or a device connected with the processor. The logic can allocate, based on the parameter, a number a ways and a size of ways of the memory for use by the processor. The logic can power down an unallocated number of ways and unused portions of the ways of the memory.

Abstract: A cache memory provided in the central processing unit is configured to include a data field which stores data in a main memory unit, a tag field which stores management information on data stored in the data field, and a valid bit which stores information about whether the data stored in the data field and the management information stored in the tag field are valid or invalid. Nonvolatile memory cells are used as memory cells which are components of the data field, the tag field, and the valid bit. Further, a power controller is provided for the central processing unit, and the power controller is configured to selectively supply power supply voltage to the data field, the tag field, and the valid bit when the cache memory is accessed from an arithmetic unit provided in the central processing unit.

Abstract: Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments.

Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.

Abstract: A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.

Abstract: Techniques for transferring a matrix for performing one or more operations are provided. The techniques include applying a permutation on at least one of one or more columns and one or more rows of a matrix to group each of at least one of one or more columns and one or more rows of the matrix with a same alignment, blocking at least one of the grouped columns and grouped rows, and performing one or more operations on each matrix block.

Abstract: Parameters indicative of resistance variance of the memory elements are tracked. The resistance variance affects values of data stored in the resistance-based memory elements. A hash function is performed for each memory element. The hash function returns a reference to one of a plurality of counter elements. A value of each counter element is modified in response to the tracked parameter data of the associated memory element. Read operations affecting the memory elements are adjusted based on the values for the associated counter elements.

Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

Abstract: A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated.

Abstract: A computer processing system with a hierarchical memory system that associates a number of valid bits for each cache line of the hierarchical memory system. The valid bits are provided for each cache line stored in a respective cache and make explicit which bytes are semantically defined and which are not for the associated given cache line. Memory requests to the cache(s) of the hierarchical memory system can include an address specifying a requested cache line as well as a mask that includes a number of bits each corresponding to a different byte of the requested cache line. The values of the bits of the byte mask indicate which bytes of the requested cache line are to be returned from the hierarchical memory system. The memory request is processed by the top level cache of the hierarchical memory system, looking for one or more valid bytes of the requested cache line corresponding to the target address of the memory request.

Abstract: Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.

Abstract: Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

Abstract: Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank selector configured to receive an address and to apply a hash function that maps the address to one of the tag banks.

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other ways. A target active way count is maintained and the system cache attempts to keep the number of currently active ways equal to the target active way count. The bandwidth and allocation intention of the system cache is monitored. Based on these characteristics, the system cache adjusts the target active way count up or down, which then causes the number of currently active ways to rise or fall in response to the adjustment to the target active way count.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: There is provided a memory control device including a device driver that executes writing or reading of data to/from a main storage unit and temporary writing or reading of data to/from a cache unit including a plurality of cache blocks, and a control unit that issues an instruction for writing or reading of data of a file system to/from the main storage unit or the cache unit to the device driver. The control unit may notify priority information about a priority for data storage into a logical block to which the cache block is associated to the device driver.

Abstract: Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.

Abstract: A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (host LBAs). A secondary memory is implemented as a cache for the primary host memory. A hybrid controller is configured directly map the clusters of host LBAs to clusters of secondary memory. The secondary memory clusters correspond to a memory space of the cache. Mapping of the host LBA secondary memory clusters is fully associative such that any host LBA cluster can be mapped to any secondary memory cluster.