Abstract: A memory module device for use in a high frequency operation provides for ease in synchronization. In one example, the memory module includes integrated buffers, each having first and second data ports connected to respective data buses in a point-to-point configuration, such that data input through either data port of the first and second data ports is transferred to the memory device and is simultaneously output through the other data port of the first and second data ports. The integrated buffers each further include first and second command address ports connected to respective command address buses in a point-to-point configuration, such that a command address signal input through either port of the first and second command address ports is transferred to the memory device and simultaneously output through the other command address port of the first and second command address ports.

Abstract: A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

Abstract: A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

Abstract: A control apparatus of a storage unit having a first and a second communication ports for conducting communication with a computer, a first and a second processors that control respectively the first and the second communication ports, first and second storage devices that store respectively a first and a second queues for storing commands sent from the computer respectively to the first and the second communication ports, and a first nonvolatile memory that the first processor accesses, the first and the second processors executing the commands stored respectively in the first and the second queues to thereby control the communications with the computer, comprising a unit causing the second processor to implement execution of the command stored in the first queue; and a unit changing data stored in the first memory while the second processor is being caused to implement execution of the command stored in the first queue.

Abstract: An integrated circuit includes a register array having a number of entry groups. Each of the entry groups includes multiple entries. Each of the entries has multiple bits. The bits among different entries are grouped into bit groups. The integrated circuit also includes a number of output ports. Each of the output ports has multiple selecting units. Each of the selecting units connects to one of the bit groups. The integrated circuit further includes a number of match ports. Each of the match ports has multiple comparing units. Each of the comparing units connects to one of the bit groups.

Abstract: An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.

Abstract: A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of independently accessible storage blocks. The buses may be coupled to convey a plurality of cache access requests to each of the storage blocks. In response to the plurality of cache access requests being conveyed on the plurality of cache buses, different ones of the storage blocks are concurrently accessible.

Abstract: A memory circuit (1) comprises at least a non-volatile random access memory (3) and a random access memory (4). The memory circuit (1) also comprises a memory controller (5) connected by a first bus (6) to the non-volatile random access memory (3) and by a second bus (10) to the random access memory (4). Thus, data can be transmitted between non-volatile random access memory (3) and random access memory (4) via the memory controller (5). The memory circuit comprises a control bus (12) connected to the memory controller (5) to control operation of the memory circuit (1). The invention also relates to a corresponding system and corresponding electronic device (2) in which the memory circuit (1) is used. The invention also relates to a corresponding method in connection with a memory circuit, in which at least a non-volatile random access memory (3) and a random access memory (4) are used.

Abstract: In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Each storage cell bank has valid bit array unit and a tag unit for each execution unit incorporated therein. Each valid bit array unit has a valid/invalid storage cell associated with each data group stored in the storage cell bank. The valid bit array units have a read/write address port and snoop address port. During a read operation, the associated valid/invalid signal is retrieved to determine whether the data signal group should be processed by the associated execution unit. In a write operation, a valid bit is set in the valid/invalid bit location(s) associated with the storage of a data signal group (or groups) during memory access.

Abstract: Maintaining data used for performing “what-if” analysis is disclosed. The systems and methods of the invention define an efficient mechanism allowing a user to specify how base values from a database are to be changed. The changes can be held in a local delta cache which is only exposed to a single user, leaving the base data unchanged. The changes can also be maintained in a write-back partition, which results in the changes being exposed to all clients of the database. Values in the write-back partition can be selectively rolled back if required.

Abstract: Maintaining data used for performing “what-if” analysis is disclosed. The systems and methods of the invention define an efficient mechanism allowing a user to specify how base values from a database are to be changed. The changes can be held in a local delta cache which is only exposed to a single user, leaving the base data unchanged. The changes can also be maintained in a write-back partition, which results in the changes being exposed to all clients of the database. Values in the write-back partition can be selectively rolled back if required.

Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.

Abstract: A multinode, multiprocessor computer system with distributed shared memory has reduced hardware and improved performance by providing a directory free environment. Without a directory, nodes do not track where cache lines are stored in caches on other nodes. In two-node systems, cache lines are implied to be either on the local node or cached at the remote node or both. Thus, if a local node has a cache miss it is implied that the other node in the system has the cache line. In another aspect, the system allows for “silent rollouts.” In prior distributed memory multiprocessor systems, when a remote node has capacity limitations, it must overwrite (i.e., rollout) a cache line and report to the home node that the rollout occurred. However, the described system allows the remote node to rollout a cache line without reporting to the home node that the rollout occurred. Such a silent rollout can create timing problems because the home node still believes the remote node has a shared copy of the cache line.

Abstract: Storing data in a cache memory of a storage device includes providing access to a first segment of the cache memory on behalf of a first group of external host systems coupled to the storage device and providing access to a second segment of the cache memory on behalf of a second group of external host systems coupled to the storage device, where at least a portion of the second segment of the cache memory is not part of the first segment of the cache memory. In some embodiments, no portion of the second segment of the cache memory is part of the first segment. Storing data in a cache memory of a storage device may also include providing a first data structure in the first segment of the cache memory and providing a second data structure in the second segment of the cache memory, where accessing the first segment includes accessing the first data structure and accessing the second segment includes accessing the second data structure. The data structures may be doubly linked ring lists of blocks of data.

Abstract: In accordance with an embodiment of the invention, a semiconductor memory includes a number of data ports each having a predetermined number of data bits. The memory further has a number of memory macros each including at least one memory array having rows and columns of memory cells. Each memory macro further includes a plurality of internal data connection points directly connected to external terminals to transfer data to or from the at least one memory array. The internal data connection points correspond in number to the number of the data ports, and the internal data connection points in the memory macros together form the plurality of data ports.

Abstract: A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e.g., SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write operations and a second memory port that is configured to receive read data from the extended capacity memory during memory read operations. The multi-port cache memory includes at least a data input register and a multiplexer that is responsive to at least one path signal. The multiplexer is configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations that occur when the FIFO memory device is filled beyond a threshold level.

Abstract: In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.

Abstract: Any of the processors CPU1 to CPUn turns the miss hit detecting signal line 5 to a low level upon detecting occurrence of a miss hit. In response, the mode switching controller 2 is notified of the occurrence of a miss hit and switches each of the processors CPU1 to CPUn to the synchronous operation mode. Also, each command from each of the processors CPU1 to CPUn is appended with a tag. When each of the processors CPU1 to CPUn feeds the synchronization detecting signal line 6 with the tags which are identical as designated as a synchronous point, the operation of the processors can be switched to the non-synchronous operation mode by the mode switching controller 2.

Abstract: The conventional multi-port cache memory, which is formed by using multi-port cells, is excellent in its operating speed. However, the integration area of the constituent multi-port cells is increased in proportion to the square of the number of ports. Thus, if it is intended to decrease the cache miss probability by increasing the storage capacity, the chip size is increased correspondingly, which increases the manufacturing cost. On the other hand, the multi-port cache memory of the present invention is formed by using, as constituents, one-port cell blocks adapted for a large storage capacity, making it possible to easily provide a multi-port cache memory of a large storage capacity and reduced integration area, which has a large random access bandwidth, is capable of parallel access from a plurality of ports, and is adapted for use in advanced microprocessors having a small cache miss probability.

Abstract: The invention relates to a multiport-RAM memory device, comprising a RAM memory unit (1), a number of serial/parallel converters (5, 6, 7) and a parallel/serial converter (10), for converting serial signals into parallel signals. Said multiport-RAM memory device further comprises a control unit (11) and two timeslot allocation devices (8, 9), whereby an emulation of a number of connections by using the simple RAM memory unit (1) may be achieved. Furthermore, a power controller (12) can significantly reduce the power demand.

Abstract: A memory agent may include a first port and a second port, wherein the memory agent is capable of detecting the presence of another memory agent on the second port. A method may include performing a presence detect operation on a first port of a memory agent, and reporting the results of the presence detect operation through a second port of the memory agent.

Abstract: A method and apparatus for adapting a single computer to drive at least two displays is disclosed. In one embodiment, an apparatus for adapting a single computer to drive at least two displays is disclosed. The apparatus comprises a controller, coupled between a user input device such as a computer, the controller for providing a control signal according to a user input; and a video switcher, for selectively providing a signal from the computer to one of at least two video displays in response to the control signal. In another embodiment, a method of presenting information on at least two displays communicatively coupled to a computer is disclosed. The method comprises the steps of intercepting a user input to the computer, and directing a video output signal from the computer to one of at least two video displays according to the intercepted video input.

Abstract: An apparatus for implementing a least-recently used (LRU) mechanism in a multi-port cache memory includes an LRU array and a shift decoder. The LRU array has multiple entries. The shift decoder includes a shifting means for shifting the entries within the LRU array. The shifting means shifts a current one of the entries and adjacent entries once, and loading new address, in response to a single cache hit in the current one of the entries. The shifting means shifts a current one of the entries and adjacent entries once, and loading an address of only one of multiple requesters into the most-recently used (MRU) entry, in response to multiple cache hits in the current one of the entries. The shifting means shifts all subsequent entries, including the current entries, n times, and loading addresses of all requesters contributed to the multiple cache hits in consecutive entries into the MRU entry and subsequent entries, in response to multiple cache hits in consecutive entries.

Abstract: In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

Abstract: A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

Abstract: A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction request for use by a memory external to the circuit based upon the first transaction request and the particular policy in response to a first cache signal of the first transaction request having a non-cacheable state and (C) searching a plurality of address tags for cache data cached within the circuit for a match with the first transaction request in response to the first cache signal having a cacheable state.

Abstract: A communication device (100) includes a processor (130) for processing communications on more than one communication line and a multi-line message memory (200) including a memory storage location for each of the one or more communication lines. The communication device (100) operates using a message manager application (155) programmed to: operate using a first communication line as an active communication line, switch the active communication line to a second communication line, access a second memory storage location associated with the second communication line within the multi-line message memory, and switch the active communication line to the first communication line.

Abstract: A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e.g., SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write operations and a second memory port that is configured to receive read data from the extended capacity memory during memory read operations. The multi-port cache memory includes at least a data input register and a multiplexer that is responsive to at least one path signal. The multiplexer is configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations that occur when the FIFO memory device is filled beyond a threshold level.

Abstract: The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a plurality of data banks for storing entries, a plurality of ports for writing to the plurality of data banks, pointers associated with the respective banks for identifying table locations suitable for overwriting by upcoming entries, wherein an entry is suitable for overwriting when it is deemed invalid by the inventive system. A preferred embodiment is disclosed involving two ports writing to two banks wherein a plurality of factors is considered in deciding where prospective entries from the two ports will be written in the table. The Factors include, matches between existing and prospective entries, the default designated data bank for a given port, whether two write operations are being attempted simultaneously, and the number of entries already present in each data bank.

Abstract: In one embodiment of the present invention, a method includes organizing a memory buffer to receive profile data corresponding to an instruction of interest within a code segment; instrumenting the code segment to store the profile data in the memory buffer; storing the profile data in the memory buffer; and sampling the profile data in the memory buffer.

Abstract: A circuit generally comprising a memory and a core module is disclosed. The memory may be configured as (i) a first stack having a plurality of index pointers and (ii) a table having a plurality of entries. The core module may be configured to (i) pop a first index pointer of the index pointers from the first stack in response to receiving a first command generated by a first module external to the circuit, (ii) assign a first entry of the entries identified by the first index pointer to the first module, (iii) generate an address in response to converting the first index pointer and (iv) transfer the address to the first module.

Abstract: According to some embodiments, an interconnect structure includes write and read structures.

Abstract: A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

Abstract: A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port.

Abstract: A memory system, memory module and memory device are described. The memory system includes a plurality of the memory modules connected in a series configuration on a first signal path. The first signal path and a second signal path carry memory control and data signals between the memory modules and a memory controller. The memory controller transmits and receives the control signals and data signals on the first and second signal paths. The first and second signal paths are connected together such that the memory modules are connected in a ring configuration. The control signals and data signals travel in opposite directions on the first and second signal paths. The first and second signal paths are shared by both the data signals and the control signals. The memory modules include multi-functional ports, each of which can receive both the control signals and the data signals and re-drive the signals onto the connected signal paths.

Abstract: It is an object to obtain a semiconductor storage having a 1—chip structure which can be simultaneously accessed to memory cells present in different memory cell arrays. A 1—port memory cell array (11) provided with a word line (WL1) for a first port in common and a 2—port memory cell array (12) are provided together over one chip, thereby constituting a semiconductor storage. By selectively bringing any of a plurality of the word lines (WL1) for the first port into an active state by a row decoder (16), it is possible to simultaneously access respective memory cells of the 1—port memory cell array (11) and the 2—port memory cell array (12). By selectively bringing any of a plurality of word lines (WL2) for a second port into an active state by a row decoder (18), it is possible to singly access the 2—port memory cell array (12).

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry.

Abstract: A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.

Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Abstract: The present invention includes a microprocessor having a system bus for exchanging data with a computer system, and a private bus for exchanging data with a cache memory system. Since the processor exchanges data with the cache memory system through the private bus, cache memory operations thus do not require use of the system bus, allowing other portions of the computer system to continue to function through the system bus. Additionally, the cache memory and the processor are able to exchange data in a burst mode while the processor determines from the tag data when a read or write miss is occurring.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a microprocessor and a first cache coupled to the microprocessor. The first cache detects conflicts between multiple requests to access a bank within the first cache.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: In a cache memory access operation data words are retrieved from the cache memory in dependence upon whether the data word reside in the cache memory. If the words reside in cache memory they are provided from the cache memory to a processor, if not then they are brought into cache memory from a main memory. Unfortunately, the data words are stored in cache memory in such a manner that accessing of the cache memory multiple times is required in order to retrieve a single cache line. During the retrieval of the single cache line, the cache memory cannot be accessed for other operations such as cache line refill and copy-back. This results in the processor to incur stall cycles while waiting for these operations to complete. By storing the cache line in such a manner that it spans multiple memory circuits, the processing stall cycles are decreased since fewer clock cycles are required to retrieve the entire cache line from the cache memory.

Abstract: An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.

Abstract: A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.

Abstract: The invention relates to a multiprocessor system having plural processors and an optical bus shared by the plural processors, and intends to simplify the cache control, reduce the volume of hardware, and shorten the memory access processing time. For this purpose, the multiprocessor system of the invention includes a shared memory, a cache memory connected to the shared memory, an optical bus connected to the cache memory, and plural processors connected to the optical bus, which access to the cache memory through the optical bus.

Abstract: A method for operating a shared memory computer system to reduce the latency times associated with lock/unlock code sequences. The computer system includes a shared memory and a plurality of processors. When one of the processors wishes to modify a shared variable stored in the shared memory, the processor must first request and receive a lock from the shared memory. The lock prevents any other processor in the computer system from modifying data in the shared memory during the locked period. In the present invention, a list of variables in the shared memory that are shared by two or more of the processors is generated. When one of the processors is granted a lock, a prefetch instruction is executed for each variable in the list. Each prefetch instruction specifies the processor receiving the lock as the destination of the data specified in that prefetch instruction. The list may be generated by a compiler during the compilation of a program that is to run on one of the processors.

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays.