Snooping Patents (Class 711/146)
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Patent number: 10289191Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.Type: GrantFiled: January 9, 2018Date of Patent: May 14, 2019Assignee: Apple Inc.Inventors: David J. Williamson, Gerard R. Williams, III
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Patent number: 10282308Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.Type: GrantFiled: June 23, 2016Date of Patent: May 7, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Nuwan Jayasena, Andrew G. Kegel
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Patent number: 10268579Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.Type: GrantFiled: April 1, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Sanjeev Kumar, Christopher J. Hughes, Partha Kundu, Anthony Nguyen
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Patent number: 10255181Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.Type: GrantFiled: September 19, 2016Date of Patent: April 9, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Bohuslav Rychlik
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Patent number: 10248565Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.Type: GrantFiled: September 19, 2016Date of Patent: April 2, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Bohuslav Rychlik
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Patent number: 10251194Abstract: In an operation scheduler adapted to schedule in an asynchronous contention-based system a first FIFO queue is adapted to store one trigger message or one operation request. A message router is coupled to the first FIFO queue and is adapted to route instructions to a second FIFO queue or a memory and locate in the memory the instructions of a suspended operation associated with a trigger message and authorize execution of the suspended operation. An arbitration unit is coupled to the second FIFO queue and to the memory, and is adapted to schedule the execution of instructions associated with a standalone non-preemptable operation during a period of time within which at least one operation of the first sequence is being suspended.Type: GrantFiled: June 17, 2013Date of Patent: April 2, 2019Assignee: NXP USA, Inc.Inventors: Ioan-Virgil Dragomir, Alexandru Balmus, Paul Marius Bivol
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Patent number: 10241917Abstract: A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.Type: GrantFiled: September 14, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Nobuyuki Ohba, Atsuya Okazaki
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Patent number: 10244016Abstract: Techniques are described for providing a local cache for media content playback. A proxy device on a local network can store fragments of media content received from a media server in a local cache. Viewer devices on the local network can request the fragments from the local cache when a bandwidth of a communication connection between the viewer devices and the media server degrades.Type: GrantFiled: September 18, 2015Date of Patent: March 26, 2019Assignee: Amazon Technologies, Inc.Inventors: Justin Michael Binns, Girish Bansilal Bajaj
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Patent number: 10223225Abstract: Test cases for testing speculative execution of instructions are replicated into a memory with non-naturally aligned data boundaries to create a non-contiguous instruction stream to efficiently test a processor. Placing test cases with test code and test data in the non-naturally aligned data boundaries as described herein allows test code to test speculative execution of branches. The test case includes a branch with a hint bit set to cause the hardware to mispredict the path of the branch to cause speculative execution of test code, bad code or erroneously execute data. The processor can then be tested to see if it properly flushes the speculatively executed code upon taking the opposite branch of the mispredicted path.Type: GrantFiled: November 7, 2016Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor
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Patent number: 10216640Abstract: According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.Type: GrantFiled: March 9, 2015Date of Patent: February 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Andrew J. Rushing, Kevin M. Lepak
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Patent number: 10212443Abstract: One embodiment provides for a general-purpose graphics processor comprising a multisample antialiasing compression module to perform planar multi-sample anti-aliasing, the multisample antialiasing compression module to analyze color data for a set of sample locations of a first pixel; determine a first plane to allocate for the first pixel, wherein the first plane is a lowest order plane to be allocated for the first pixel; and merge a plane allocation for the first pixel with a plane allocation for a second pixel in response to a determination that the first plane is the lowest order plane to be allocated for the second pixel.Type: GrantFiled: January 17, 2018Date of Patent: February 19, 2019Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 10198265Abstract: A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to a prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table. The method further comprises determining if the matching entry provides a valid prediction and, if valid, retrieving a location for the prior aliasing store instruction using the distance field. The method finally comprises performing a gating operation on the load operation.Type: GrantFiled: October 25, 2013Date of Patent: February 5, 2019Assignee: INTEL CORPORATIONInventor: Hui Zeng
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Patent number: 10185663Abstract: A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. The receiver cache level includes presence determination circuitry for performing a determination as to whether the given data value is present in the at least one bypassed cache level. In response to the determination indicating that the data value is present in the at least one bypassed cache level, one of the at least one bypassed cache level is made to respond to the data access request.Type: GrantFiled: February 8, 2017Date of Patent: January 22, 2019Assignee: ARM LimitedInventors: Jamshed Jalal, Michael Filippo, Bruce James Mathewson, Phanindra Kumar Mannava
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Patent number: 10169237Abstract: A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.Type: GrantFiled: September 14, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Nobuyuki Ohba, Atsuya Okazaki
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Patent number: 10152327Abstract: An apparatus for gating a load operation is presented. The apparatus comprises a memory resident data structure, wherein the memory resident data structure is a prediction table comprising a plurality of entries, wherein a matching entry corresponding to the load operation within the prediction table comprises a prediction regarding a dependence of the load operation on a prior aliasing store instruction, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to the prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table, wherein the prediction strength influences a gating of the load operation.Type: GrantFiled: October 25, 2013Date of Patent: December 11, 2018Assignee: INTEL CORPORATIONInventor: Hui Zeng
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Patent number: 10073786Abstract: The present application includes apparatuses and methods for compute enabled cache. An example apparatus includes a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.Type: GrantFiled: March 10, 2016Date of Patent: September 11, 2018Assignee: Micron Technology, Inc.Inventor: Richard C. Murphy
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Patent number: 10067871Abstract: A microprocessor comprises a cache including a tag array; a tagpipe that arbitrates access to the tag array; and a logic analyzer for investigating a starvation, livelock, or deadlock condition. The logic analyzer, which comprises read logic coupled to the tagpipe, is configured to record snapshots of transactions to access the tag array.Type: GrantFiled: December 13, 2014Date of Patent: September 4, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Rodney E. Hooker, Douglas R. Reed
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Patent number: 10055807Abstract: An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.Type: GrantFiled: March 2, 2016Date of Patent: August 21, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seungjin Lee, Seok-Jun Lee
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Patent number: 9996487Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.Type: GrantFiled: June 26, 2015Date of Patent: June 12, 2018Assignee: INTEL CORPORATIONInventors: Jose S. Niell, Daniel F. Cutter, Stephen J. Robinson, Mukesh K. Patel
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Patent number: 9916246Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.Type: GrantFiled: August 16, 2016Date of Patent: March 13, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Carson Donahue Henrion, Michael K. Ciraula, Gregg Donley, Alok Garg, Eric Busta
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Patent number: 9898375Abstract: A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.Type: GrantFiled: December 22, 2015Date of Patent: February 20, 2018Assignee: EMC IP Holding Company LLCInventor: Jean-Philippe Fricker
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Patent number: 9892042Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.Type: GrantFiled: January 12, 2015Date of Patent: February 13, 2018Assignee: Inspur (Beijing) Electronic Information Industry Co., Ltd.Inventors: Endong Wang, Leijun Hu, Rengang Li
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Patent number: 9880944Abstract: A page replacement algorithm is provided. An idle range of memory pages is determined based, at least in part, on indications of references to memory pages in the idle range of memory pages, wherein the idle range of memory pages is a set of one or more memory pages. A first memory page is identified in the idle range of memory page for paging out of memory. The first memory page is identified based, at least in part, on indications of modifications to the memory pages. The first memory page is paged out of memory.Type: GrantFiled: July 21, 2017Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Mengze Liao, Jiang Yu
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Patent number: 9875159Abstract: Exemplary method, system, and computer program product embodiments for efficient state tracking for clusters are provided. In one embodiment, by way of example only, in a distributed shared memory architecture, an asynchronous calculation of deltas and the views is performed while concurrently receiving client requests and concurrently tracking the client requests times. The results of the asynchronous calculation may be applied to each of the client requests that are competing for data of the same concurrency during a certain period with currently executing client requests. Additional system and computer program product embodiments are disclosed and provide related advantages.Type: GrantFiled: March 1, 2013Date of Patent: January 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael Keller
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Patent number: 9870039Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: December 15, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 9858203Abstract: A page replacement algorithm is provided. An idle range of memory pages is determined based, at least in part, on indications of references to memory pages in the idle range of memory pages, wherein the idle range of memory pages is a set of one or more memory pages. A first memory page is identified in the idle range of memory page for paging out of memory. The first memory page is identified based, at least in part, on indications of modifications to the memory pages. The first memory page is paged out of memory.Type: GrantFiled: May 3, 2017Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Mengze Liao, Jiang Yu
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Patent number: 9847971Abstract: According to one aspect, a method includes coupling first and second security units in series between first and second networks. The first security unit obtains packets from the first network, and the second security unit obtains the packets from the first security unit. The first security unit includes first logic arranged to provide security. The second security unit includes second logic arranged to provide security. The method also includes configuring the second security unit in a bypass mode such that the second logic does not provide security, and obtaining a first packet from the first network via the first security unit. The first packet is identified as secure by the first logic. Finally, the method includes providing the first packet from the second security unit to the second network by passing the first packet through the second unit without using the second logic to provide security.Type: GrantFiled: November 3, 2015Date of Patent: December 19, 2017Assignee: Cisco Technology, Inc.Inventors: Kishore Karighattam, Jian Wu, Madhusudhan Karnam Rao, Madhu Babu Kodali
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Patent number: 9836326Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.Type: GrantFiled: March 31, 2015Date of Patent: December 5, 2017Assignee: Oracle International CorporationInventors: David Richard Smentek, Kathirgamar Aingaran, Sumti Jairath, Manling Yang, Serena Wing Yee Leung, Paul N. Loewenstein
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Patent number: 9823722Abstract: A method for adjusting a voltage of a supercapacitor is disclosed, the method, which is used to retard aging of the supercapacitor and extend a service life of the supercapacitor, includes: acquiring information that carries a system service volume; configuring a size of an available capacity value of the Cache according to the information; and adjusting a working voltage of the supercapacitor according to the configured size of the available capacity value of the Cache.Type: GrantFiled: February 13, 2015Date of Patent: November 21, 2017Assignee: Huawei Technologies Co., Ltd.Inventor: Weijian Liu
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Patent number: 9817760Abstract: The disclosure relates to filtering snoops in coherent multiprocessor systems. For example, in response to a request to update a target memory location at a Level-2 (L2) cache shared among multiple local processing units each having a Level-1 (L1) cache, a lookup based on the target memory location may be performed in a snoop filter that tracks entries in the L1 caches. If the lookup misses the snoop filter and the snoop filter lacks space to store a new entry, a victim entry to evict from the snoop filter may be selected and a request to invalidate every cache line that maps to the victim entry may be sent to at least one of the processing units with one or more cache lines that map to the victim entry. The victim entry may then be replaced in the snoop filter with the new entry corresponding to the target memory location.Type: GrantFiled: March 7, 2016Date of Patent: November 14, 2017Assignee: QUALCOMM IncorporatedInventors: Eric Francis Robinson, Khary Jason Alexander, Zeid Hartuon Samoail, Benjamin Charles Michelson
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Patent number: 9804803Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for identifying a data processing function to be executed in a hybrid main memory system, the hybrid main memory system including a first type of main memory and a second type of main memory, the data processing function including data access operations to access the hybrid main memory system, accessing a write metric for the data processing function, the write metric based at least in part on a proportion of the data access operations that are write operations, and, based at least in part on the write metric being less than a threshold value, designating the data processing function for execution in the first type of main memory.Type: GrantFiled: August 20, 2015Date of Patent: October 31, 2017Assignee: SAP SEInventor: Ahmad Hassan
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Patent number: 9785557Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.Type: GrantFiled: October 25, 2016Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
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Patent number: 9785556Abstract: Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.Type: GrantFiled: December 23, 2014Date of Patent: October 10, 2017Assignee: Intel CorporationInventors: Ramacharan Sundararaman, Tracey L. Gustafson, Robert J. Safranek
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Patent number: 9772945Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.Type: GrantFiled: October 25, 2016Date of Patent: September 26, 2017Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
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Patent number: 9740438Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving, from an application being executed, a memory allocation request, the memory allocation request indicating a type of physical memory in a hybrid memory system, providing a virtual memory area based on the type of physical memory, providing a mapping entry that maps the virtual memory area to the type of physical memory, and enabling access to physical memory in the hybrid memory based on a plurality of mapping entries, the mapping entry being included in the plurality of mapping entries.Type: GrantFiled: August 20, 2015Date of Patent: August 22, 2017Assignee: SAP SEInventor: Ahmad Hassan
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Patent number: 9734062Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state. The controller is connected to the memory and configured to (i) recognize sub-cache line boundaries and (ii) process the I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills.Type: GrantFiled: December 18, 2013Date of Patent: August 15, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Saugata Das Purkayastha, Luca Bert, Horia Simionescu, Kishore Kaniyar Sampathkumar, Mark Ish
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Patent number: 9703492Abstract: A page replacement algorithm is provided. An idle range of memory pages is determined based, at least in part, on indications of references to memory pages in the idle range of memory pages, wherein the idle range of memory pages is a set of one or more memory pages. A first memory page is identified in the idle range of memory page for paging out of memory. The first memory page is identified based, at least in part, on indications of modifications to the memory pages. The first memory page is paged out of memory.Type: GrantFiled: May 19, 2015Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Mengze Liao, Jiang Yu
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Patent number: 9645931Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: GrantFiled: March 18, 2016Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Patent number: 9639470Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.Type: GrantFiled: August 26, 2014Date of Patent: May 2, 2017Assignee: ARM LimitedInventors: Sean James Salisbury, Andrew David Tune, Jamshed Jalal, Mark David Werkheiser
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Patent number: 9632954Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.Type: GrantFiled: November 7, 2011Date of Patent: April 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark A. Brittain, John Steven Dodson, Benjiman L. Goodman, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli
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Patent number: 9600407Abstract: A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.Type: GrantFiled: September 30, 2011Date of Patent: March 21, 2017Assignee: Intel CorporationInventor: Robert Faber
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Patent number: 9594713Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.Type: GrantFiled: September 12, 2014Date of Patent: March 14, 2017Assignee: QUALCOMM IncorporatedInventors: Randall John Pascarella, Jaya Prakash Subramaniam Ganasan, Thuong Quang Truong, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier
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Patent number: 9575893Abstract: A snoop filter for a multi-processor system has a storage device and a control circuit. The control circuit manages at least a first-type entry and at least a second-type entry stored in the storage device. The first-type entry is configured to record information indicative of a first cache of the multi-processor system and first requested memory addresses that are associated with multiple first cache lines each being only available in the first cache. The second-type entry is configured to record information indicative of multiple second caches of the multi-processor system and at least a second requested memory address that is associated with a second cache line being available in each of the multiple second caches.Type: GrantFiled: August 7, 2015Date of Patent: February 21, 2017Assignee: MEDIATEK INC.Inventors: Chien-Hung Lin, Wei-Hao Chiao
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Patent number: 9501232Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.Type: GrantFiled: August 13, 2015Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 9495108Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.Type: GrantFiled: June 26, 2014Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 9489144Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.Type: GrantFiled: August 13, 2015Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 9489142Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.Type: GrantFiled: June 26, 2014Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 9483401Abstract: Embodiments of the present invention disclose a data processing method and apparatus. The method includes: first receiving an operation command, then searching, according to a memory address, a Cache memory in a Cache controller for data to be operated, and storing the operation command in a missed command buffer area in the Cache controller when the data to be operated is not found through searching in the Cache memory; then, storing data sent by an external memory in a data buffer area of the Cache controller after sending a read command to the external memory, and finally processing, according to a missed command, the data acquired from the external memory and the data carried in the missed command. The present invention applies to the field of computer systems.Type: GrantFiled: April 26, 2013Date of Patent: November 1, 2016Assignee: Huawei Technologies Co., Ltd.Inventors: Yongbo Cheng, Tao Li, Chenghong He
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Patent number: 9456335Abstract: A method and system for defining an offlinable model graph. In one embodiment of the method, a request is generated by a mobile device. The mobile device receives a response to the request. The mobile device updates a plurality of tables stored in memory of the mobile device, wherein the updating comprises adding a component of the response to a first table of the plurality of tables.Type: GrantFiled: October 31, 2013Date of Patent: September 27, 2016Assignee: Oracle International CorporationInventors: Wayne Carter, Donald Creig Humes
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Patent number: 9436605Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M?) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.Type: GrantFiled: December 20, 2013Date of Patent: September 6, 2016Assignee: INTEL CORPORATIONInventors: Jeffrey D. Chamberlain, Vedaraman Geetha, Robert G. Blankenship, Yen-Cheng Liu, Adrian C. Moga, Herbert H. Hum, Sailesh Kottapalli