Abstract: A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency.

Abstract: An apparatus including a memory having an array of blocks addressable using address bits; and a permutation circuit coupled to the memory and configured to permutate the address bits such that during a memory access blocks of data are rearranged virtually.

Abstract: Embodiments of the invention are directed to systems and methods for optimizing data access request handling in a non-volatile memory (NVM) device. In one embodiment, the device may include a number of storage elements that can be concurrently programmed, and the device may include a controller that determines whether data access requests may be staged and processed together so that the concurrency of the storage device may be optimized. In one embodiment, staged requests are selectively combined together so that their combined data size is greater than or equal to a data size that can be programmed in a single set of concurrent operations to the storage elements.

Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

Abstract: Methods and apparatus related to constructing a persistent file system from scattered persistent regions are described. In one embodiment, stored information in a storage unit corresponds to one or more persistent memory regions that are scattered amongst one or more non-volatile memory devices. The one or more persistent memory regions are byte addressable. Also, the one or more persistent memory regions are used to form a virtual contiguous region. Other embodiments are also disclosed and claimed.

Abstract: Method, process, and apparatus to efficiently store, read, and/or process portions of word data. A portion of a data word, which includes multiple portions, may be read by a computer processor. The processor may read a first portion of the data word from a first memory. The processor may read a second portion of the data word from a second portion of memory. The second portion may include bits which are less critical than the bits of the first portion. The second memory may be distinct from the first memory based on one or more physical attributes.

Abstract: An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.

Abstract: Various embodiments are generally directed to storing data of a three-dimensional (3D) array in a tiled manner in which adjacent rows of adjacent planes are interleaved to enable more efficient retrieval in performing 3D stencil calculations. An apparatus to perform a stencil calculation includes a processor component, a storage communicatively coupled to the processor component, and an interleaving component for execution by the processor component to interleave storage of data of cells of adjacent rows of a first plane with data of cells of adjacent rows of an adjacent second plane of a 3D array among contiguous storage locations of the storage. Other embodiments are described and claimed.

Abstract: A method begins by a processing module receiving data of a file for storage in a dispersed storage network (DSN) memory and determining a segmentation scheme for storing the data. The method continues with the processing module determining how to store the data in accordance with the segmentation scheme to produce information for storing the data and generating an entry within a segment allocation table associated with the file, wherein the entry includes the information for storing the data and the segmentation scheme. The method continues with the processing module facilitating storage of the segment allocation table in the DSN memory. The method continues with the processing module segmenting the data in accordance with the segmentation scheme to produce a plurality of data segments and facilitating storage of the plurality of data segments in the DSN memory in accordance with the information for storing the data.

Abstract: Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described herein includes a system for integrated sub-block interleaving and rate matching, which includes a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm and a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm, such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm or in the order that the data would be produced by the interleaving algorithm as modified by a rate matching algorithm.

Abstract: A system includes a hybrid memory module. The hybrid memory module includes volatile memory and non-volatile memory. The system further includes a processor coupled to the hybrid memory module. The processor prevents the hybrid memory module from being mapped during a memory initialization routine by misrepresenting a status of the hybrid memory module.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log2(Y)) and C=ceiling(log2(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S<Y, the system sets E=S. Otherwise, if S?Y, the system sets E=S?Y.

Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.

Abstract: A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device communicates with a plurality of initiators. The first port control module comprises a first world wide number (WWN) table. The first WWN table comprises connection rates of the plurality of initiators during communication with the first physical layer device. Each of the connection rates is a last connection rate of a respective one of the plurality of initiators.

Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

Abstract: A data storage device protecting security code stored therein and a data storage system including same are disclosed. The data storage device efficiently prevents unauthorized access to the security code by allowing command descriptor block (CDB) information to be read using only a read-only memory (ROM).

Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.

Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: One system may comprise an interleave system that determines a desired interleave for at least a selected portion of a distributed memory system. A migration system is associated with the interleave system to migrate blocks of data from first assigned memory locations of the distributed memory system to second interleaved memory locations of the distributed memory system to implement the desired interleave.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: A memory controller (16) is used in a system (10) having a main memory (22) and a set of non-volatile memories (26, 32, 38, 44). Each non-volatile memory comprises a plurality of sectors (S0-S28), pages, or other memory unit types. A command is received to write data to the set of non-volatile memories (26, 32, 38, 44). Within the data is identified a grouping of the data that is for writing to sectors in the set of non-volatile memories in which each non-volatile memory of the set of non-volatile memories is to be written and each sector to be written has a corresponding location to be written in all of the other non-volatile memories. Corresponding locations are locations that are in the same location in the sequential order. The grouping of data is written into the set of the non-volatile memories to result in the writing in the non-volatile memories occurring contemporaneously.

Abstract: Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.

Abstract: Embodiments of the present invention are directed to a method, computer-readable medium and system for deskewing data. More specifically, skewed data is accessed and written into a plurality of memories in an aligned manner. Each memory may be associated with a respective lane of a multiple lane distribution (MLD) system and may receive a respective initial portion of data associated with a frame. The memory or lane that is the last to receive an initial portion of data associated with the frame may be determined. The address at which the initial portion of data is written into the memory may be determined using a write pointer associated with the memory. At least one read pointer associated with the memories may be set to the address to allow the initial portions of data to be contemporaneously read from the memories.

Abstract: Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

Abstract: An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words.

Abstract: A storage controller including a processor and a memory controller. The processor is configured to generate a command corresponding to a first write operation and a second write operation, in which the first write operation is contiguous to the second write operation, and the first write operation is received prior to the second write operation. The command arranges the second write operation prior to the first write operation. The memory controller is configured to, in response to the command, execute each of the first write operation and the second write operation. The second write operation is executed by the memory controller prior to the first write operation.

Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

Abstract: Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract: Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.

Abstract: A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple data channels are assigned to multiple data writers based on a key code. Then, each subset of data units is transferred to a writer via an assigned channel for writing to storage media. Thereafter, to securely retrieve the stored data, each subset of data units is read from the storage media using a data reader. The original sequence of data units can only be reassembled using the key code for properly reassembling the subsets of data units into their original sequence.

Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.

Abstract: A method for increasing storage space in a system containing a block data storage device, a memory, and a processor is provided. Generally, the processor is configured by the memory to tag metadata of a data block of the block storage device indicating the block as free, used, or semifree. The free tag indicates the data block is available to the system for storing data when needed, the used tag indicates the data block contains application data, and the semifree tag indicates the data block contains cache data and is available to the system for storing application data type if no blocks marked with the free tag are available to the system.

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: A system may route media stream samples in time-stamped packets to a media interface. The system may determine a hash value from a stream identifier that identifies a source media stream corresponding to the media stream samples. The hash value may be determined based on a combination of a first portion of the stream identifier and a second portion of the stream identifier. The system may determine whether the stream identifier identifies a subscribed media stream by looking up the hash value in a hash table. The system may route the media stream samples to a media interface if source media stream is a subscribed media stream.

Abstract: A memory device includes a plurality of memory cells and programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. The memory device includes a program circuit configured to receive at least one second data word, and, for each second data word, send a program current in parallel to discriminated memory cells based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate the at least one second data word from the first data word. The number of discriminated memory cells of the second data word is maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit.

Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

Abstract: A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship.

Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.

Abstract: An image forming apparatus including: a storage device composed of a plurality of storage sections for storing a job data to be input; an image forming section for performing an image formation based on the job data having been stored in the storage device; and a control section configured to control a first mode for processing an independent job data, and a second mode for processing a plurality of job data in parallel, wherein the control section is configured to control in such a manner that a storage section, in said plurality of storage sections, to be used in the first mode differs from a storage section to be used in the second mode.

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks.

Abstract: A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n?1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.

Abstract: A control apparatus which controls a memory having a plurality of banks, allocates the plurality of banks to a first region and a second region, wherein data transfer is performed by interleaving access in a plurality of banks in the first region, and data transfer is performed by non-interleaving access in at least one bank in the second region. The control apparatus sets a bank in the first region and a bank in the second region independently to a low-power state.

Abstract: An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of being independently controlled so that data can be written or read in/from the memory banks, each having memory cells arranged in an N×M matrix structure. The memory write/read control unit generates control signals to write/read data in/from the memory unit. The memory access address generation unit generates a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals. The second permutation and output selection unit rearranges the positions of data bits output from the memory unit and outputs the position-rearranged data bits.