Least Recently Used (lru) Patents (Class 711/160)
  • Patent number: 8595745
    Abstract: A memory swap management method that can preferentially place in a primary storage device a process that has a high possibility of being executed next, thereby shortening the time to start executing the next process. A planned execution sequence of jobs is stored when there are a plurality of jobs waiting to be executed. A process as a swap-out candidate and a process as a swap-in candidate are determined based on the execution sequence and types of processes stored in the primary storage device. According to the determination, the process as the swap-out candidate is swapped out from the primary storage device to a secondary storage device, and the process as the swap-in candidate is swapped in from the secondary storage device into an area of the primary storage device freed as a result of the swap-out.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: November 26, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoichi Matsuyama
  • Patent number: 8583972
    Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
  • Publication number: 20130297898
    Abstract: Apparatus, methods, and other embodiments associated with reducing read starvation that is supported by a multi-purpose buffer managed by a least recently used (LRU) data structure are described. One example method includes changing how certain retired pages are added back into the LRU. The dual-purpose buffer may be used in data de-duplication to support satisfying ingest requests and to support satisfying read requests. The method may also include controlling the LRU to allocate active ingest pages and active read pages from the head of the LRU. The method may also include controlling the LRU to cause the active ingest page and the active read page to re-enter the LRU at the tail of the LRU. Unlike conventional approaches, the method may also include controlling the LRU to cause a retired ingest page to re-enter the LRU at a location other than the tail (e.g., head) of the LRU.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Applicant: Quantum Corporation
    Inventors: Todd Pisek, Matthew Dewey
  • Patent number: 8578373
    Abstract: Techniques for improving performance of a shared storage environment are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for improving performance of a shared storage environment comprising determining a unit of shared storage utilized by an environment to be migrated, retrieving a storage management memory structure of a source computing platform for the unit of the shared storage, transferring the storage management memory structure to a target computing platform, and building a portion of storage management memory for the target computing platform utilizing the transferred storage management memory structure.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: November 5, 2013
    Assignee: Symantec Corporation
    Inventors: Sasidharan Krishnan, Suhas Girish Urkude
  • Publication number: 20130275693
    Abstract: Provided are techniques for more efficient data storage on a computing system. An inode table is provided and populated with information relating to current and N previous locations within data storage that a particular data block has been stored. When a particular data block is modified in a redirect on write system, the modified data block is stored, if possible is a previous storage location for that particular data block and the current data location may be saved for use as the location for a subsequent modification.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adekunle Bello, Andrew N. Solomon, Robert Wright Thompson
  • Patent number: 8560765
    Abstract: Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: October 15, 2013
    Assignee: LSI Corporation
    Inventor: Robert W. Warren
  • Publication number: 20130254479
    Abstract: Systems and methods for tracking changes and performing backups to a storage device are provided. For virtual disks of a virtual machine, changes are tracked from outside the virtual machine in the kernel of a virtualization layer. The changes can be tracked in a lightweight fashion with a bitmap, with a finer granularity stored and tracked at intermittent intervals in persistent storage. Multiple backup applications can be allowed to accurately and efficiently backup a storage device. Each backup application can determine which block of the storage device has been updated since the last backup of a respective application. This change log is efficiently stored as a counter value for each block, where the counter is incremented when a backup is performed. The change log can be maintained with little impact on I/O by using a coarse bitmap to update the finer grained change log.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 26, 2013
    Applicant: VMware, Inc.
    Inventors: Christian Czezatke, Krishna Yadappanavar, Andrew Tucker
  • Patent number: 8543791
    Abstract: An apparatus for reducing a page fault rate in a virtual memory system includes a page table stored in a main storage unit which stores a reference address so as to read page information from the main storage unit; a buffer unit which stores a portion of the page table; and a processor which reads data from the main storage unit or which stores data in the main storage unit. When changing information for referring to a first page that exists in the page table, the processor performs a task invalidating information related to the first page in the buffer unit. A method of reducing the page fault rate includes resetting reference information stored in the page table; detecting whether the reference information exists in a buffer unit; and invalidating the reference information when the reference information exists in the buffer unit.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-hoon Shin, Ji-hyun In
  • Publication number: 20130238866
    Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for managing free chains of compute resources. A system configured to practice the method divides a free chain of compute resources into a usable part (UP) which contains resources available for immediate allocation and an unusable part (UUP) which contains resources not available for immediate allocation but which become available after a certain minimum number of allocations. The system sorts resources in the UP by block number, and maintains a last used object (LUO) vector, indexed by block number, which records a last object in the UP for each block. Each time the system frees a resource, the system adds the freed resource to a tail of the UUP and promotes an oldest resource in the UUP to the UP. This approach can manage free chains in a manner that is both flaw tolerant and has relatively high performance.
    Type: Application
    Filed: April 22, 2013
    Publication date: September 12, 2013
    Applicant: Avaya Inc.
    Inventor: John H. Meiners
  • Publication number: 20130219116
    Abstract: In one embodiment, a method for managing a composite storage device made up of fast non-volatile storage, such as a solid state device, and slower non-volatile storage, such as a traditional magnetic hard drive, can include maintaining a first data structure, which stores instances of recent access to each unit in a set of units in the fast non-volatile storage device, such as the SSD device and also maintaining a second data structure that indicates whether or not units in the slower storage device, such as the HDD, have been accessed at least a predetermined number of times. In one embodiment, the second data structure can be a probabilistic hash table, which has a low required memory overhead but is not guaranteed to always provide a correct answer with respect to whether a unit or block in the slower storage device has been referenced recently.
    Type: Application
    Filed: September 6, 2012
    Publication date: August 22, 2013
    Inventors: Wenguang Wang, Peter Macko
  • Publication number: 20130219117
    Abstract: Approaches to managing a composite, non-volatile data storage device are described. In one embodiment, a method for managing a composite storage device made up of fast non-volatile storage, such as a solid state device, and slower non-volatile storage, such as a traditional magnetic hard drive, can include maintaining a first data structure, which stores instances of recent access to each unit in a set of units in the fast non-volatile storage device, such as the SSD device and also maintaining a second data structure that indicates whether or not units in the slower storage device, such as the HDD, have been accessed at least a predetermined number of times. In one embodiment, the second data structure can be a queue of Bloom filters.
    Type: Application
    Filed: September 6, 2012
    Publication date: August 22, 2013
    Inventors: Peter Macko, Wenguang Wang
  • Patent number: 8516187
    Abstract: Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 20, 2013
    Assignee: Netlist, Inc.
    Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta
  • Publication number: 20130205107
    Abstract: The present invention relates to the field of digital media recording such as video or audio, where compression is used to reduce the amount of data to save onto a data storage. In particular the invention relates to recording media, wherein the memory area required to store the media is unknown. The invention discloses a method for recording digital streamed media with a number of media frames in a memory by encoding each media frame into an encoded frame comprising a first number of sets of data, representing different characteristics of the media stream. The invention further relates to detecting if the data storage is full and if the data storage is full, storing new frames in the data storage previously occupied by the data sets representing the least prioritized characteristics of the previously stored encoded frames. The invention also relates to a corresponding media recorder and computer program.
    Type: Application
    Filed: June 21, 2010
    Publication date: August 8, 2013
    Applicant: SAAB AB
    Inventors: Henrik Dikvall, Per Cronvall
  • Patent number: 8495275
    Abstract: A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a position selection signal which specifies a position for data insertion or data removal to a fixed value, or subtracts the position selection signal from the fixed value, generates an enable signal based on the calculation result, and controls data retention performed in the memories or data update performed in the memories using data of a memory in precedent stages based on the generated enable signal, wherein the selection circuits are controlled based on the position selection signal at the time of the data insertion, and data stored in a memory located at the position specified by the position specification signal is updated with data to be inserted.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 23, 2013
    Assignee: Fujitsu Limited
    Inventor: Takashi Toyoshima
  • Patent number: 8484405
    Abstract: Techniques are disclosed for managing memory within a virtualized system that includes a memory compression cache. Generally, the virtualized system may include a hypervisor configured to use a compression cache to temporarily store memory pages that have been compressed to conserve memory space. A “first-in touch-out” (FITO) list may be used to manage the size of the compression cache by monitoring the compressed memory pages in the compression cache. Each element in the FITO list corresponds to a compressed page in the compression cache. Each element in the FITO list records a time at which the corresponding compressed page was stored in the compression cache (i.e. an age). A size of the compression cache may be adjusted based on the ages of the pages in the compression cache.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: July 9, 2013
    Assignee: VMware, Inc.
    Inventors: Ali Mashtizadeh, Irfan Ahmad
  • Publication number: 20130173875
    Abstract: A method of managing a storage region of a memory device, and a storage apparatus using the method. In the method, data blocks are arranged in an order of performing writing on the memory device; a frequency of updating data in a logical page to be written is determined, based on whether an invalid physical page is present in a block within a window size that is initially set based on a most recently written data block from among the arranged data blocks, in response to a write request, and the data in the logical page is stored in a storage region of the memory device classified according to the determined frequency, according to the determined frequency.
    Type: Application
    Filed: December 17, 2012
    Publication date: July 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Patent number: 8478942
    Abstract: A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 2, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick Conway
  • Patent number: 8468536
    Abstract: A method that includes providing LRU selection logic which controllably pass requests for access to computer system resources to a shared resource via a first level and a second level, determining whether a request in a request group is active, presenting the request to LRU selection logic at the first level, when it is determined that the request is active, determining whether the request is a LRU request of the request group at the first level, forwarding the request to the second level when it is determined that the request is the LRU request of the request group, comparing the request to an LRU request from each of the request groups at the second level to determine whether the request is a LRU request of the plurality of request groups, and selecting the LRU request of the plurality of request groups to access the shared resource.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Deanna Postles Dunn Berger, Ekaterina M. Ambroladze, Michael Fee, Diana Lynn Orf
  • Patent number: 8458416
    Abstract: Various embodiments of the present invention provide systems and methods for selecting data encoding. As an example, some embodiments of the present invention provide methods that include receiving a data set to be written to a plurality of multi-bit memory cells that are each operable to hold at least two bits. In addition, the methods include determining a characteristic of the data set, and encoding the data set. The level of encoding is selected based at least in part on the characteristic of the data set. In some instances of the aforementioned embodiments, the characteristic of the data set indicates an expected frequency of access of the data set from the plurality of multi-bit memory cells.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 4, 2013
    Assignee: LSI Corporation
    Inventors: Robert W. Warren, Robb Mankin
  • Patent number: 8438334
    Abstract: A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
  • Publication number: 20130111160
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation. Thus, data that otherwise may be evicted or demoted, but that meets or exceeds the utility metric threshold, is exempted from space reclamation and is instead maintained in the data storage memory.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: MICHAEL T. BENHASE, EVANGELOS S. ELEFTHERIOU, LOKESH M. GUPTA, ROBERT HAAS, XIAO-YU HU, MATTHEW J. KALOS, IOANNIS KOLTSIDAS, ROMAN A. PLETKA
  • Patent number: 8417903
    Abstract: Disclosed is a computer implemented method, computer program product, and apparatus for maintaining a preselect list. The method comprises software components detecting a page fault of a memory page. In response to detecting a page fault, the software components determine whether the memory page is referenced in the preselect list and unhide the memory page. Upon determining whether the memory page is referenced in the preselect list, the software components remove an entry of the preselect list corresponding to the memory page to form at least one removed candidate page and skip paging-out of the at least one removed candidate page.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Abraham Alvarez, Andrew Dunshea, Douglas J. Griffith
  • Publication number: 20130086339
    Abstract: Method, apparatus, and systems employing novel delayed dictionary update schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.
    Type: Application
    Filed: October 1, 2011
    Publication date: April 4, 2013
    Inventors: Ilan Pardo, Ido Y. Soffair, Dror Reif, Debendra Das Sharma, Akshay G. Pethe
  • Patent number: 8386708
    Abstract: A method for metadata management in a storage system configured for supporting sub-LUN tiering. The method may comprise providing a metadata queue of a specific size; determining whether the metadata for a particular sub-LUN is cached in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is cached in the metadata queue; inserting the metadata for the particular sub-LUN to the metadata queue when the metadata queue is not full and the metadata is not cached; replacing an entry in the metadata queue with the metadata for the particular sub-LUN when the metadata queue is full and the metadata is not cached; and identifying at least one frequently accessed sub-LUN for moving to a higher performing tier in the storage system, the at least one frequently accessed sub-LUN being identified based on the metadata cached in the metadata queue.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: February 26, 2013
    Assignee: LSI Corporation
    Inventor: Martin Jess
  • Publication number: 20130046943
    Abstract: A row buffer 102 in DRAM 100 stores any data read from a memory array 101 in a specified data length unit. An LLC 206 is cache memory, and extracts and stores a part of data stored in the row buffer 102 as cache data. In a MAC 701, when push-out control of the LLC 206 is performed, it is predicted that data at which DIMM address is stored in the row buffer 102 in the near future based on the queuing state of an MRQ 203. In the MAC 701, each physical address of the cache data in a push-out target range 702 on the LLC 206 is converted into a DIMM address. If the converted address matches the predicted address of the data, then the cache data corresponding to the matching addresses is pushed out on a priority basis from the LLC 206.
    Type: Application
    Filed: July 10, 2012
    Publication date: February 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Takatsugu Ono, Takeshi Shimizu
  • Patent number: 8375178
    Abstract: Systems, methods, and other embodiments associated with selecting a memory page for removal from a buffer pool based on the operating conditions of a computing system.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: February 12, 2013
    Assignee: Oracle International Corporation
    Inventors: Inaam Ahmed Rana, Heikki Tuuri
  • Patent number: 8370597
    Abstract: Technologies are described for implementing a migration mechanism in a storage system containing multiple tiers of storage with each tier having different cost and performance parameters. Access statistics can be collected for each territory, or storage entity, within the storage system. Data that is accessed more frequently can be migrated toward higher performance storage tiers while data that is accessed less frequently can be migrated towards lower performance storage tiers. The placement of data may be governed first by the promotion of territories with higher access frequency to higher tiers. Secondly, data migration may be governed by demoting territories to lower tiers to create room for the promotion of more eligible territories from the next lower tier. In instances where space is not available on the next lower tier, further demotion may take place to an even lower tier in order to make space for the first demotion.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 5, 2013
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Ajit Narayanan, Loganathan Ranganathan, Sharon Enoch
  • Patent number: 8364915
    Abstract: Techniques for generating access information indicating a least recently used (LRU) memory region in a set of memory regions. In an embodiment, data is stored in an entry of an LRU tracking list (LTL) based on a touch message indicating when a memory group has been touched—e.g. read from, written to and/or associated with a memory region. The data stored in an LTL entry may include an identifier of a memory group and/or validity data specifying whether that LTL entry stores a set of default data. In another embodiment, access information may be generated based on the memory group identifier and the validity data.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Kie Woon Lim, Khee Wooi Lee, William A. Stevens, Jr.
  • Patent number: 8341371
    Abstract: Upon the arrival at a memory device of one or more data chunks associated with respective logical addresses, each data chunk is assigned a signature, stored in a first location, and copied to a second location. The copy is assigned a signature that matches the signature of its parent data chunk. Before erasing a memory block that includes one or more data chunks, it first is verified that those data chunks have been copied, i.e., that copies of all the data chunks in the block, with matching signatures, exist in the memory device.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: December 25, 2012
    Assignee: SanDisk IL Ltd
    Inventor: Menahem Lasser
  • Patent number: 8341350
    Abstract: A method for metadata management in a storage system may include providing a metadata queue of a maximum size; determining whether the metadata for a particular sub-LUN is held in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is held in the metadata queue; inserting the metadata for the particular sub-LUN at the head of the metadata queue when the metadata queue is not full and the metadata is not held in the metadata queue; replacing an entry in the metadata queue with the metadata for the particular sub-LUN and moving the metadata to the head of the metadata queue when the metadata queue is full and the metadata is not held in the metadata queue; and controlling the number of sub-LUNs in the storage system to manage data accessed with respect to an amount of available data storage.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: December 25, 2012
    Assignee: LSI Corporation
    Inventors: Martin Jess, Brian McKean
  • Patent number: 8316204
    Abstract: One embodiment of the present invention provides a system that uses versioned pointers to facilitate reusing memory without having to reclaim the objects solely through garbage collection. The system operates by first receiving a request to allocate an object. Next, the system obtains the object from a pool of free objects, and sets an allocated/free flag in the object to indicate that the object is allocated. The system also increments a version number in the object, and also encodes the version number into a pointer for the object. The system then returns the pointer, which includes the encoded version number. In this way, subsequent accesses to the object through the pointer can compare the version number encoded in the pointer with the version number in the object to determine whether the object has been reused since the pointer was generated.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 20, 2012
    Assignee: Oracle America, Inc.
    Inventor: David R. Chase
  • Patent number: 8301833
    Abstract: Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: October 30, 2012
    Assignee: Netlist, Inc.
    Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta
  • Patent number: 8301733
    Abstract: Systems and methods for dynamically chunking for delivery instances are provided that automatically implement chunking strategies based on one or more chunking considerations related to a request for a media file. These systems and methods may be part of a larger media servicing network that can be used to, among other things, process uploaded media content, provide it for streaming/downloading, and collect metric information regarding the streaming/downloading. The disclosed systems and methods provide for receiving a request having a Uniform Resource Locator (URL) and providing an index file to implement chunking strategies based on chunking considerations associated with the request.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: October 30, 2012
    Assignee: Unicorn Media, Inc.
    Inventor: Albert John McGowan
  • Publication number: 20120265954
    Abstract: A storage management application determines that a source virtual tape requires reclamation, identifies all block addresses for active data of a source virtual tape and sorts the block addresses in an ascending order, identifies a target virtual tape which has sufficient free capacity to store the active data of said source virtual tape and the last written block address on said target virtual tape, and sends a command to the VTL-system instructing it to perform reclamation including information about said source and said target virtual tape, the sorted list of block addresses denoting active data on the source virtual tape and the starting block address on the target virtual tape. The reclamation logic references the active data host blocks of said source volume to said target virtual tape starting at said starting block address by just updating the host block to disk block mapping table.
    Type: Application
    Filed: August 30, 2010
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nils Haustein, Stefan Neff
  • Publication number: 20120254564
    Abstract: A mechanism is provided for managing a high speed memory. An index entry indicates a storage unit in the high speed memory. A corresponding non-free index is set for a different type of low speed memory. The indicated storage unit in the high speed memory is assigned to a corresponding low speed memory by including the index entry in the non-free index. The storage unit in the high speed memory is recovered by demoting the index entry from the non-free index. The mechanism acquires a margin performance loss corresponding to a respective non-free index in response to receipt of a demotion request. The margin performance loss represents a change in a processor read operation time caused by performing a demotion operation in a corresponding non-free index. The mechanism compares the margin performance losses of the respective non-free indexes and selecting a non-free index whose margin performance loss satisfies a demotion condition as a demotion index.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 4, 2012
    Applicant: International Business Machines Corporation
    Inventors: Xue D. Gao, Chao Guang Li, Yang Liu, Yi Yang
  • Publication number: 20120254520
    Abstract: A swapping method performed using a data processing device, which includes a processor including a plurality of cores, the swapping method including searching for an empty page of a swap memory in response to the swap memory being connected to the data processing device, the search being performed by using at least one core of the plurality of cores, selecting a page to be swapped from a main memory of the data processing device, the selection being performed by using the at least one core by accessing a corresponding main memory list among a plurality of main memory lists, and swapping data of the page selected to be swapped to the empty page, the swapping being performed by using the at least one core.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 4, 2012
    Inventors: Yang Woo Roh, Min Chan Kim, Joo Young Hwang
  • Patent number: 8281087
    Abstract: Provided are a method, system, and program for receiving a request to remove a record. A determination is made as to whether a state associated with the record includes at least one hold state and whether the state associated with the record includes at least a retention period that has not expired. The request to remove the record is denied in response to determining that the state associated with the record includes at least one of at least one hold state and one retention period that has not expired.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: October 2, 2012
    Assignee: Google Inc.
    Inventors: Alan Stuart, Toby Lyn Marek, Avishai Haim Hochberg, David Maxwell Cannon, Howard Newton Martin
  • Publication number: 20120221812
    Abstract: A method for preserving memory affinity in a computer system is disclosed. The method reduces and sometimes eliminates memory affinity loss due to process migration by restoring the proper memory affinity through dynamic page migration. The memory affinity access patterns of individual pages are tracked continuously. If a particular page is found almost always to be accessed from a particular remote access affinity domain for a certain number of times, and without any intervening requests from other access affinity domain, the page will migrate to that particular remote affinity domain so that the subsequent memory access becomes local memory access. As a result, the proper pages are migrated to increase memory affinity.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 30, 2012
    Applicant: IBM CORPORATION
    Inventors: MATHEW ACCAPADI, ROBERT H. BELL, JR., MEN-CHOW CHIANG, HONG L. HUA
  • Patent number: 8255637
    Abstract: A mass storage system and method incorporates a cache memory or a cache management module which handles dirty data using an access-based promotion replacement process through consistency checkpoints. The consistency checkpoints are associated with a global number of snapshots generated in the storage system. The consistency checkpoints are organized within the sequence of dirty data in an invariable order corresponding to storage volumes with the generated snapshots, such that, responsive to destaging a consistency checkpoint the global number of generated snapshots are recorded and then read during recovery of the failed storage system.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: August 28, 2012
    Assignee: Infinidat Ltd.
    Inventor: Yechiel Yochai
  • Patent number: 8244981
    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: August 14, 2012
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
  • Patent number: 8239631
    Abstract: A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 7, 2012
    Assignee: Entropic Communications, Inc.
    Inventors: Jan-Willem van de Waerdt, Johan Gerard Willem Maria Janssen, Maurice Penners
  • Publication number: 20120198187
    Abstract: Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mathew Accapadi, Robert H. Bell, JR., Men-Chow Chiang, Hong L. Hua
  • Publication number: 20120191901
    Abstract: One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion. Each bit of the third portion of the first block may indicate whether an attempt to write data to a corresponding one or more words of the first portion of the first block has failed since the last erase of the corresponding one or more words of the first portion of the first block. Whether data to be written to a particular virtual address is written to the first block or the second block may depend on the write status of the first block and the second block.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Inventor: John Peter Norair
  • Patent number: 8219758
    Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 10, 2012
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
  • Patent number: 8214609
    Abstract: Some embodiments comprise a method for selecting data to be transferred to a storage space of virtual memory and include identifying a set of data and determining subsets. Determining subsets may allow for delays before transferring the subsets and allow access to memory of the subsets during the delays. Accesses during the delays may enable embodiments to select other data to be transferred to the storage space and prevent transference of the accessed data. Other embodiments comprise apparatuses that have a paging space, a page identifier, and a page transferrer to transfer pages to the paging space after a delay. The delay may prevent a number of pages from being transferred to the paging space, such as for pages that were accessed during the delay.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Shashidhar Bomma, Andrew Dunshea, Douglas J. Griffith, Jean-Philippe Sugarbroad
  • Publication number: 20120144111
    Abstract: A method for selectively storing data identified by a software application in higher performance media may include executing control programming for an operating system and a software application hosted by the operating system. The software application assigns a first importance level to a first portion of data and a second importance level to a second portion of data. A first portion of data having the first importance level assigned by the software application is stored in a first storage medium at the instruction of the operating system. A second portion of data having the second importance level assigned by the software application is stored in a second storage medium at the instruction of the operating system. The second storage medium has at least one performance, reliability, or security characteristic different from the first storage medium.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: LSI CORPORATION
    Inventors: Bret S. Weber, Jeremy Pinson, Mark Nossokoff, Brian McKean
  • Publication number: 20120134369
    Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 31, 2012
    Inventors: Andrew Li, Michael Lau, Asad Khamisy
  • Publication number: 20120124305
    Abstract: Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: VMWARE, INC.
    Inventors: Boris WEISSMAN, Aleksandr V. MIRGORODSKIY, Ganesh VENKITACHALAM, Feng TIAN
  • Publication number: 20120116179
    Abstract: Methods and apparatus for storing data records associated with a medical monitoring event in a data structure. These include initiating loop recording in an implantable medical device upon determination of a neurological event, wherein loop recording comprises storing a data record of a plurality of data records in a data structure, the plurality of data records representing information about determined neurological events. Methods and apparatus can further include determining a priority index for the plurality of data records based on severity levels of the determined neurological events and replacing older data records of the plurality of data records on the data structure with new data records according to the priority index, wherein the new data records selectively replace those data records in the data structure having the lowest associated priority index.
    Type: Application
    Filed: January 12, 2012
    Publication date: May 10, 2012
    Applicant: MEDTRONIC, INC.
    Inventors: Touby A. Drew, Jonathon E. Giftakis, David L. Carlson, Eric J. Panken, Jonathan C. Werder, Nina M. Graves
  • Publication number: 20120117299
    Abstract: Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Applicant: VMWARE, INC.
    Inventors: Carl A. WALDSPURGER, Rajesh VENKATASUBRAMANIAN, Alexander Thomas GARTHWAITE, Yury BASKAKOV, Puneet ZAROO