Access Limiting Patents (Class 711/163)
  • Patent number: 9483198
    Abstract: A processing request is received. The processing request includes information about a first location where a set of data is stored and information about a second location where the set of data is to be transferred. The size of the set of data is determined. The size of the available portion of the second location is determined. If the size of the set of data is smaller than the size of the available portion of the second location is determined. Responsive to determining the size of the set of data is larger than the size of the available portion of the second location, the size of the available portion is requested to be increased. The size of the available portion of the second location is increased to a size larger than the determined size of the set of data.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Prajwal M. Alva, Sindury R. R. Baddam, Michael Bender, Kiran K. Kompala
  • Patent number: 9483438
    Abstract: A data processing apparatus and method for performing speculative vector access operations are provided. The data processing apparatus has a reconfigurable buffer accessible to vector data access circuitry and comprising a storage array for storing up to M vectors of N vectors elements. The vector data access circuitry performs speculative data write operations in order to cause vector elements from selected vector operands in a vector register bank to be stored into the reconfigurable buffer. On occurrence of a commit condition, the vector elements currently stored in the reconfigurable buffer are then written to a data store. Speculation control circuitry maintains a speculation width indication indicating the number of vector elements of each selected vector operand stored in the reconfigurable buffer.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: November 1, 2016
    Assignee: ARM Limited
    Inventors: Alastair David Reid, Daniel Kershaw
  • Patent number: 9483665
    Abstract: A method and a computer program are provided for implementing memory accesses. A hypervisor is used for this purpose, via which the memory access takes place.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: November 1, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Martin Emele, Thomas Keller, Ingo Opferkuch
  • Patent number: 9448837
    Abstract: Techniques are provided for restoring thread groups in a cooperative thread array (CTA) within a processing core. Each thread group in the CTA is launched to execute a context restore routine. Each thread group, executes the context restore routine to restore from a memory a first portion of context associated with the thread group, and determines whether the thread group completed an assigned function prior to executing the context restore routine. If the thread group completed an assigned function prior to executing the context restore routine, then the thread group exits the context restore routine. If the thread group did not complete the assigned function prior to executing the context restore routine, then the thread group executes one or more operations associated with a trap handler routine. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 20, 2016
    Assignee: NVIDIA Corporation
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Merlin Danskin
  • Patent number: 9436598
    Abstract: In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 6, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tamaki Tsuruda, Tamiyu Kato
  • Patent number: 9436564
    Abstract: A system and method are provided for processing to create distributed volume in a distributed storage system during a failure that has partitioned the distributed volume (e.g. an array failure, a site failure and/or an inter-site network failure). In an embodiment, the system described herein may provide for continuing distributed storage processing in response to I/O requests from a source by creating the local parts of the distributed storage during the failure, and, when the remote site or inter-site network return to availability, the remaining part of the distributed volume is automatically created. The system may include an automatic rebuild to make sure that all parts of the distributed volume are consistent again. The processing may be transparent to the source of the I/O requests.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 6, 2016
    Assignee: EMC Corporation
    Inventor: Roel van der Goot
  • Patent number: 9436400
    Abstract: A device configuration silo is arranged to be accessed as an IEEE 1667-compatible silo which exposes interfaces to a host application to make changes to the presence of one or more other silos, as well as make changes to silo configurations on a per-silo basis for data and method sharing among silos across the ACTs on a storage device such as a transient storage device. The interfaces exposed by the device configuration silo are arranged to enable an authenticated provisioner, like administrator in a corporate network environment, to perform configuration changes to silos after the storage device is released into the field through a secure provisioning mechanism. In addition, users may make configuration changes to silos at runtime in some usage scenarios, for example to enable discrete portions of functionality on a storage device, by using a secure secondary authentication mechanism that is exposed by the device configuration silo.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: September 6, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: David Abzarian, Harish S. Kulkarni, Todd Carpenter
  • Patent number: 9424408
    Abstract: A system and a method are disclosed for authenticating a user of a mobile computing device. Information is received describing the location of the mobile computing device. The information can include the current location of the device or a current type of user activity associated with a location. A current timeout length is determined based on this information. If the mobile computing device has remained idle for a time period equal to the current timeout length, the user of the mobile computing device is authenticated.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 23, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Brian Hernacki
  • Patent number: 9411671
    Abstract: In one embodiment, a storage and privacy system stores and manages information associated with users and ensures and enforces access-control rules specified for the stored information.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: August 9, 2016
    Assignee: Facebook, Inc.
    Inventors: Robert Carlton Johnson, Stephen Charles Heise, Yiding Jia
  • Patent number: 9395993
    Abstract: Execution-Aware Memory protection technologies are described. A processor includes an instruction fetch unit to fetch instructions of applications executing in a multitasking environment and an execution unit to execute the instructions. A memory protection unit (MPU) enforces memory access control of the applications by defining an instruction region (I-space) and a data region (D-space and linking the I-space to the D-space. When the MPU determining whether an instruction address is within the I-space and whether a data address of a data access operation is within the D-space. The MPU issues a memory protection fault for the data access operation when either the instruction address is not within the I-space or the data address is not within the D-space.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Patrick Koeberl, Steffen Schulz
  • Patent number: 9384064
    Abstract: A processor comprising multiple processor cores and a bus for exchanging data between the multiple processor cores is disclosed. Each of the multiple processor cores includes: at least one processor register; a cache for storing at least one cache line of memory; a load store unit for executing a memory command to exchange data between the cache and the at least one processor register; an atomic memory operation unit for executing an atomic memory operation on the at least one cache line of memory; and a high throughput register for storing a status indicating a high throughput or a normal status. The load store unit is operable to transfer the atomic memory operation to the atomic memory operation unit of a designated processor core if the atomic memory operation status is the high throughput status using the bus.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: July 5, 2016
    Assignee: GlobalFoundries, Inc.
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 9379950
    Abstract: A streams manager monitors performance of a streaming application, and when the performance needs to be improved, the streams manager automatically requests virtual machines from a cloud manager. The streams manager specifies to the cloud manager streams infrastructure and one or more streams application components for the virtual machines. The cloud manager provisions one or more virtual machines in a cloud with the specified streams infrastructure and streams application components. The streams manager then modifies the flow graph so one or more portions of the streaming application are hosted by the virtual machines in the cloud.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lance Bragstad, Michael J. Branson, Bin Cao, James E. Carey, Mathew R. Odden
  • Patent number: 9367702
    Abstract: A method for automatically encrypting files is disclosed. In some cases, the method may be performed by computer hardware comprising one or more processors. The method can include detecting access to a first file, which may be stored in a primary storage system. Further, the method can include determining whether the access comprises a write access. In response to determining that the access comprises a write access, the method can include accessing file metadata associated with the first file and accessing a set of encryption rules. In addition, the method can include determining whether the file metadata satisfies the set of encryption rules. In response to determining that the file metadata satisfies the set of encryption rules, the method can include encrypting the first file to obtain a first encrypted file and modifying an extension of the first encrypted file to include an encryption extension.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: June 14, 2016
    Assignee: Commvault Systems, Inc.
    Inventors: Andrei Erofeev, Rahul S. Pawar
  • Patent number: 9354927
    Abstract: One embodiment of the present invention is a method including: (a) representing virtual primary disk data and state data of a virtual machine in a unit of storage; (b) exposing the virtual primary disk data of the virtual machine to a guest of the virtual machine to allow the guest to access the virtual primary disk data; and (c) preventing the guest from accessing the state data for the virtual machine.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: May 31, 2016
    Assignee: VMware, Inc.
    Inventors: Daniel K. Hiltgen, Rene W. Schmidt
  • Patent number: 9342310
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Oawami
  • Patent number: 9342477
    Abstract: A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 17, 2016
    Assignee: RDC SEMICONDUCTOR CO., LTD.
    Inventors: Chang-Cheng Yap, Ming-Chi Shih
  • Patent number: 9344762
    Abstract: A set top box or like device utilizing trusted applications in conjunction with an untrusted software framework. In one implementation, trusted or certified applications are received from a service provider for execution by a software framework of the device. Certification of a trusted application may entail, for example, verifying that the application is executable by the device in a manner consist with the industry standard certification process. The software framework may comprise, for example, an Android framework supported by an underlying. Linux operating system environment and isolated in a Linux resource container. A secure access client/server interface may also be provided to support interactions between the software framework and trusted portions of the device. In further embodiments, both trusted applications and a set top box application utilized by the device to perform traditional set top box operations are implemented in at least one version of an Android or like framework.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 17, 2016
    Assignee: Broadcom Corporation
    Inventors: Narayan Rajgopal, Fabian Russo, Xavier Miville
  • Patent number: 9338522
    Abstract: A set top box or like device incorporating an untrusted software framework as a client of a secure operating system kernel. The software framework may comprise, for example, an Android framework supported by an underlying Linux operating system environment having a secure kernel. The software framework can be executed using a variety of process isolation techniques depending on performance and isolation requirements. A secure access client/server interface may also be provided to support interactions between the untrusted software framework (and applications utilizing the untrusted software framework) and secure or trusted portions of the device. The secure access interface can be configured to perform operations such as handle validation, heap pointer validation, non-pointer parameter validation, heap isolation, and resource release relating to terminated processes.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: May 10, 2016
    Assignee: Broadcom Corporation
    Inventors: Narayan Rajgopal, Marcus C. Kellerman, David Erickson
  • Patent number: 9330026
    Abstract: A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system as a result of performing a prediction algorithm during a hardware table walk that uses a predictor to predict a PA based on a virtual address (VA). When the predictor is enabled, it might be possible for a person with knowledge of the system to configure the predictor to cause contents stored at a PA of a secure portion of the main memory to be loaded into a register in the TLB. In this way, a person who should not have access to contents stored in secure portions of the main memory could indirectly gain unauthorized access to those contents. The apparatus and method prevent such unauthorized access to the contents by masking the contents under certain conditions.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Thomas Zeng, Azzedine Touzni, Tzung Ren Tzeng, Phil J. Bostley
  • Patent number: 9330273
    Abstract: A computer-implemented method for increasing compliance with data loss prevention policies may include (1) identifying a file that is subject to a data loss prevention policy, (2) determining a classification of the file according to the data loss prevention policy, (3) identifying a graphical user interface that is configured to display a representation of the file, and (4) enhancing the representation of the file within the graphical user interface with a visual indication of the classification of the file according to the data loss prevention policy. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: May 3, 2016
    Assignee: Symantec Corporation
    Inventors: Rupesh Hanumant Khetawat, Amol Sharadchandra Ghatge, Sagar Shashikant Sonawane
  • Patent number: 9323934
    Abstract: A method, computer program product, and computer system for managing and tracking commands associated with a change on a managed computer system. The managed computer system receives a log-on of an administrator onto the managed computer system, determines the lockdown level of the managed computer system by querying a managing computer system, and retrieves a list of authorized commands under the lockdown level from the managing computer system. The managed computer system determines, by querying the managing computer system, whether an authorized change on the managed computer system exists. The managed computer system removes the lockdown level to receive from the managing computer system authorization of commands that have been locked down, in response to determining that the authorized change exists. The managed computer system sets the lockdown level with the authorized commands on the managed computer system, in response to determining that the authorized change does not exist.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Eric Anderson, Christopher J. Dawson, Leslie A. Nelson, Brett W. Singletary
  • Patent number: 9319269
    Abstract: A framework for handling a secure interaction between components in a cloud infrastructure system that wish to transfer information between each other during processing of a customer's subscription order is described. The framework orders the security zones of components based on security levels and protects the transfer of information between components in security zones with different security levels. The assignment of a component to a security zone is based upon the sensitivity of the data handled by the components, the sensitivity of functions performed by the component, and the like.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 19, 2016
    Assignee: Oracle International Corporation
    Inventors: Gopalan Arun, Ramkrishna Chatterjee, Ramesh Vasudevan
  • Patent number: 9317630
    Abstract: A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tracy Bashore, Ahmed Gheith, Aditya Kumar, Ronald L. Rockhold
  • Patent number: 9311474
    Abstract: Provided is an information processing apparatus configured to execute at least one function, including: a storage configured to store a first code; an authentication unit configured to obtain a second code from an external storage medium, and to verify the second code against the first code to thereby authenticate the second code; an execution allowing unit configured, when the authentication unit succeeds in authentication, to allow execution of a predetermined function out of the at least one function; and an update unit configured, when the authentication unit succeeds in authentication, to update the first code stored in the storage with another first code, and to update the second code stored in the external storage medium with another second code such that the authentication unit will succeed in authentication based on the updated first code.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: April 12, 2016
    Assignee: MITUTOYO CORPORATION
    Inventor: Masanobu Kataoka
  • Patent number: 9304798
    Abstract: A scalable, multi-tenant network architecture for a virtualized datacenter is provided. The network architecture includes a network having a plurality of servers connected to a plurality of switches. The plurality of servers hosts a plurality of virtual interfaces for a plurality of tenants. A configuration repository is connected to the network and each server in the plurality of servers has a network agent hosted therein. The network agent encapsulates packets for transmission across the network from a source virtual interface to a destination virtual interface in the plurality of virtual interfaces for a tenant in the plurality of tenants. The packets are encapsulated with information identifying and locating the destination virtual interface, and the information is interpreted by switches connected to the source virtual interface and the destination virtual interface.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 5, 2016
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Jayaram Mudigonda, Praveen Yalagandula, Jeffrey Clifford Mogul, Bryan Stiekes, Anna Fischer
  • Patent number: 9304942
    Abstract: A system for controlling access to resources in an apparatus when the apparatus is not active. Emerging technologies may allow information to be accessed in an apparatus memory without the operating system of the apparatus facilitating the access. In such instances, a subsystem in the apparatus may become active upon reception of wireless signals, and may grant direct access to memory. An access control configuration for the subsystem may be implemented in order to control memory access even when other software systems are inactive. The subsystem access control configuration may be configured (e.g., by the user) when the apparatus is active, and may be established (e.g., installed or updated) upon subsystem activation.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 5, 2016
    Assignee: Nokia Technologies Oy
    Inventors: Jaakko Varteva, Joni Jantunen
  • Patent number: 9292684
    Abstract: Systems and methods are provided for the prevention and mitigation of security attacks in computer systems. Virtualization technology is provided and leveraged to prevent and mitigate exploits in the computer systems. For example, malicious code may be prevented from system execution by inhibiting the delivery of such code in a payload to system memory. In other examples, virtualization technology is leveraged to mask the computer system machine architecture. By masking or otherwise hiding the machine architecture, the delivery of payloads into memory by malicious users can be prevented. In this manner, even if exploits are identified and accessed by malicious users of code, the denial of payload delivery prevents the execution of malicious actions within the computer system.
    Type: Grant
    Filed: September 6, 2014
    Date of Patent: March 22, 2016
    Inventor: Michael Guidry
  • Patent number: 9292679
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 22, 2016
    Assignee: INTEL CORPORATION
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Patent number: 9286245
    Abstract: Embodiments of apparatuses and methods for hardware enforced memory access permissions are disclosed. In one embodiment, a processor includes address translation hardware and memory access hardware. The address translation hardware is to support translation of a first address, used by software to access a memory, to a second address, used by the processor to access the memory. The memory access hardware is to detect an access permission violation.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: David M. Durham, Ravi L. Sahita, Prashant Dewan
  • Patent number: 9286232
    Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer, an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining a cache of ranges of currently registered virtual addresses, the cache including entries associating a range of currently registered virtual addresses, a handle representing physical addresses mapped to the range of currently registered virtual addresses, and a counter; determining whether to register ranges of virtual addresses in dependence upon the cache of ranges of currently registered virtual addresses; and determining whether to deregister ranges of virtual addresses in dependence upon the cache of ranges of currently registered virt
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Gary R. Ricard
  • Patent number: 9286192
    Abstract: Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9286236
    Abstract: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Florian A. Auernhammer, Patricia M. Sagmeister
  • Patent number: 9286136
    Abstract: A region lock (RL) method and system for ensuring data integrity is disclosed. The method and system in accordance with the present disclosure works in conjunction with a balanced-tree based RL scheme. By eliminating steps and checks that in most cases are unnecessary, the relatively high overhead associated with the balanced-tree based RL scheme may be reduced. For instance, the solution in accordance with the present disclosure may utilize a hash table to determine whether RL overlap checks may be bypassed for certain I/O commands. Since the new solution requires very little processing, therefore by reducing unnecessary RL overlap checks, RL overhead may be dramatically reduced and may lead to significant increases in overall system performance.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 15, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Horia C. Simionescu, Timothy E. Hoglund, Robert L. Sheffield
  • Patent number: 9286328
    Abstract: According to one embodiment of the present invention, a system includes a processor to copy an object of a database system. The system determines one or more portions of the object that are active and reside within a buffer pool of the database system, and copies the determined portions of the object from the buffer pool. Remaining portions of the object that are non-active are copied from database storage. A copy of the object is created from the copied object portions. Embodiments of the present invention further include a method and program product for copying an object of a database system in substantially the same manner described above.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel Kozin, Arthur Marais, Nigel G. Slinger, John B. Tobler
  • Patent number: 9286242
    Abstract: According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintarou Sano, Shunsuke Sasaki, Hiroshi Isozaki, Jun Kanai, Toshiki Kizu, Ryuta Nara
  • Patent number: 9280447
    Abstract: Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9274969
    Abstract: A cache memory apparatus includes an L1 cache memory, an L2 cache memory coupled to the L1 cache memory, an arithmetic logic unit (ALU) within the L2 cache memory, the combined ALU and L2 cache memory being configured to perform therewithin at least one of: an arithmetic operation, a logical bit mask operation; the cache memory apparatus being further configured to interact with at least one processor such that atomic memory operations bypass the L1 cache memory and go directly to the L2 cache memory.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 1, 2016
    Assignee: MMAGIX TECHNOLOGY LIMITED
    Inventor: Daniel Shane O'Sullivan
  • Patent number: 9268695
    Abstract: Methods and structure within a storage controller for using region locks to efficiently divert an I/O request received from an attached host system to one of multiple processing stacks in the controller. A region lock module within the controller allows each processing stack to request a region lock for a range of block addresses of the storage devices. A divert-type lock request may be established to identify a range of block addresses for which I/O requests should be diverted to a particular one of the multiple processing stacks.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Adam Weiner, Robert L. Sheffield, Jr., Naveen Krishnamurthy, Kapil Sundrani, Rajeev Srinivasa Murthy, Anand Narayanamurthy, Horia Cristian Simionescu, James A. Rizzo
  • Patent number: 9270678
    Abstract: One or more techniques are provided for causing a location of a screen image associated with a resource to be adjusted on a display device. The adjustment may be based at least in part on determining that a control element receives focus. The resource may be associated with an application, such as an email application that may be hosted remotely from a client device. Access to one or more resources may be controlled or mediated. Access rights may be based at least in part on a determination of a geographic location of a client device. When the client device is located in a safe area, the client device may be provided access to the resource. When the client device is not located in a safe area, the client device might not be provided access to the resource or might not be provided full access to the resource.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: February 23, 2016
    Assignee: Citrix Systems, Inc.
    Inventors: Richard Mazzaferri, Martin Duursma, Donovan Hackett, Lee Laborczfalvi
  • Patent number: 9262341
    Abstract: A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: February 16, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Rika Ono, Hitoshi Suzuki
  • Patent number: 9251162
    Abstract: The present invention provides a storage management system and method for managing access between a plurality of processes and a common store. According to the invention, each individual process comprises data processing means, a cache for the temporary storage of data generated by the data processing means, and a control unit for managing the transferral of data between the cache and a common store. The control unit comprises a manager for monitoring the availability of storage locations in the store to receive and store data and for allocating data to available storage locations, an interface for transferring the allocated data to the available storage locations, and a locking arrangement for locking the store during data transfer in order to ensure exclusive access and thereby preserve data integrity.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 2, 2016
    Assignee: FLEXERA SOFTWARE LLC
    Inventor: David Christopher Wyles
  • Patent number: 9244870
    Abstract: According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: January 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takahiro Shimizu
  • Patent number: 9235500
    Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: January 12, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Swaroop Kavalanekar
  • Patent number: 9229801
    Abstract: A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: January 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Uday Chandrasekhar, Jianmin Huang, Steven Sprouse, Nian Niles Yang, Xinde Hu
  • Patent number: 9229850
    Abstract: A method is used in mapping data storage and virtual machines. A logical volume from a data storage system is provided for use by a hypervisor. The hypervisor is queried through a web service to identify a virtual machine of the hypervisor. It is determined that the virtual machine is using the logical volume.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 5, 2016
    Assignee: EMC Corporation
    Inventors: Yidong Wang, Neil F. Schutzman, Russell R. Laporte, Gregory W. Lazar, Deene A. Dafoe, Feng Zhou
  • Patent number: 9223612
    Abstract: Systems and methods are disclosed for object-based commands with quality of service identifiers. In an embodiment, an apparatus may comprise a memory device having a processor configured to store data as objects, each object including an object identifier field to track the object, and a user data field for user data of the object. The processor may be further configured to receive a command including an operation directed to an object, and a quality of service identifier that specifies a level of service associated with the operation. Commands may be directed toward put, get, and delete operations, among others.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: December 29, 2015
    Assignee: Seagate Technology LLC
    Inventors: Timothy R Feldman, James Prescott Hughes, Martin R Furuhjelm
  • Patent number: 9223724
    Abstract: A device of one embodiment includes a host device including a first memory unit and host controller, and memory device. The host controller controls input/output accesses to the first memory unit. The memory device includes a nonvolatile semiconductor memory, second memory unit, protection circuit, and device controller. The second memory unit temporarily stores data to be transferred between the first memory unit and the nonvolatile semiconductor memory. The protection circuit protects data to be transferred from the second memory unit to the first memory unit by converting the data into an incomprehensible format. The device controller switches according to a control program whether or not to protect the data by the protection circuit.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhiro Kondo, Konosuke Watanabe, Kenichi Maeda
  • Patent number: 9208214
    Abstract: An approach is provided to expand attributes included in an SQL expansion clause into a number of selection statements. In the approach, an expansion clause is identified in within a Structured Query Language (SQL) statement with the SQL statement identifying a relational database table. Column attributes associated with the identified relational database table are compared to attributes included in the identified expansion clause. Columns included in the relational database table are then selected based on the comparison. SQL column selection statements are then generated with each of the generated SQL column selection statements corresponding to one of the selected columns. The generated SQL column selection statements are then included in the SQL statement.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventor: Allan T. Chandler
  • Patent number: 9208341
    Abstract: A method and system for synchronizing an encrypted file with a remote storage is disclosed. According to one embodiment, a computer-implemented method comprises providing a user with a user application and an encryption key in a portable memory device. The user runs the user application to securely access to a storage on a cloud storage system. A file is encrypted with the encryption key stored in the portable memory device and synchronized with the cloud storage system.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: December 8, 2015
    Assignee: Brainzquare Inc.
    Inventors: Seon Geun Kang, Jeong Hwan Park
  • Patent number: 9201882
    Abstract: A device may include a network interface for communicating with another device over a network, a storage unit to store content, and a processor. The processor may be configured to receive a request from a user to change usable storage space on the storage unit, send a message that describes the request to a service provider, receive a reply allowing the user to change the usable storage space from the service provider, provide at least one option to the user in response to the reply, receive information from the user selecting a first one of the at least one option, and set a size of the usable storage space to a value corresponding to the first option.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: December 1, 2015
    Assignee: VERIZON PATENT AND LICENSING INC.
    Inventors: Sameer Vasant Gavade, Venkata (Kiran) Adimatyam