Addressing Combined With Specific Memory Configuration Or System Patents (Class 711/1)
  • Patent number: 8935455
    Abstract: An approach to allocating storage that has track managed storage and cylinder managed storage. The approach involves receiving a request to allocate a data set for new data and determining if the size of the new data exceeds a breakpoint value. The size of the new data may be determined by allocating a buffer data set that is the size of the breakpoint value, and writing the new data to the buffer data set. If the new data only partially fills the buffer data set, then the size of the new data is smaller than the breakpoint value. If the new data overfills the buffer data set, then the size of the new data set is larger than the breakpoint value. New data that is larger than the breakpoint value is automatically stored in cylinder managed storage, while new data that is smaller than the breakpoint value is automatically stored in track managed storage.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Neal E. Bohling, Joseph V. Malinowski, David C. Reed, Max D. Smith
  • Patent number: 8908220
    Abstract: An information processing system may include at least an image processing device and includes a receiving unit, a specifying unit, an acquiring unit, and an adjusting unit. The receiving unit receives a print request and identification information. The specifying unit specifies a queue corresponding to image forming device based on the identification information. The acquiring unit acquires the number of jobs stored in the specified queue. The adjusting unit adjusts the number of print services depending on whether the number of acquired jobs is equal to or larger than a predetermined value for the number of jobs set in the identification information and depending on whether the number of print services that process the jobs stored in the queue is equal to or smaller than a predetermined value for the number of print services set in the identification information.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 9, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyasu Miyazawa, Jun Otsuka
  • Patent number: 8873249
    Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Justin P. Bandholz, Brian M. Kerrigan, Edward J. McNulty, Pravin Patel, Peter R. Seidel, Philip L. Weinstein
  • Patent number: 8819474
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Theodore Z. Schoenborn, John V. Lovelace, Christopher P. Mozak, Bryan L. Spry
  • Patent number: 8812765
    Abstract: A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more blocks and stores a data record for each block indicating a plurality of node groups and a selection of the node groups. Each selected node group represents a number of nodes, and selected node groups represent at least one node that has requested access to the block. In response to receiving an access request from a requesting node that may or may not be in a selected node group, the method and system update the data record to indicate the correct selection. If the requesting node is not in any node group, the data record is adjusted to have new node groups, one of which represents the requesting node.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: August 19, 2014
    Assignee: Silicon Graphics International Corp.
    Inventors: Donglai Dai, Randal Passint
  • Patent number: 8813162
    Abstract: An information receiving apparatus includes: a communication unit; a storage unit that stores data; a data acquisition unit that acquires distribution data that are received via the communication unit and stores the distribution data in a prescribed storage area of the storage unit that is determined in advance; and a control unit that, prior to the communication unit receiving the distribution data, performs a storage area securing process that secures a storage area by deleting data that are stored in the prescribed storage area of the storage unit or by transferring the data to another storage area of the storage unit.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 19, 2014
    Assignee: Kyocera Corporation
    Inventor: Saya Shigeta
  • Patent number: 8806162
    Abstract: Visibility of a data storage entity on a first storage system is switched to a replicated data storage entity on a second storage system. Data from the data storage entity is replicated from the first storage system to the second storage system using a common serial number. The data storage entity is hidden from the first storage system by concealing the common serial number. An ejection of the data storage entity from the first storage system is automated, and the replicated data storage entity is introduced to the second storage system.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shay H. Akirav, Shiri Alexander, Yariv Bachar, Evgeny Budilovsky, Elena Drobchenko, Asaf K. Ekshtein, Dov N. Hepner, Aharon Lazar, Ofer Leneman, Itay Maoz, Gil E. Paz, Tzafrir Z. Taub, Neville Yates
  • Patent number: 8799596
    Abstract: Visibility of a data storage entity on a first storage system is switched to a replicated data storage entity on a second storage system. Data from the data storage entity is replicated from the first storage system to the second storage system using a common serial number. The data storage entity is hidden from the first storage system by concealing the common serial number. An ejection of the data storage entity from the first storage system is automated, and the replicated data storage entity is introduced to the second storage system.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shay H. Akirav, Shiri Alexander, Yariv Bachar, Evgeny Budilovsky, Elena Drobchenko, Asaf K. Ekshtein, Dov N. Hepner, Aharon Lazar, Ofer Lenaman, Itay Maoz, Gil E. Paz, Tzafrir Z. Taub, Neville Yates
  • Patent number: 8775734
    Abstract: A virtual disk is comprised of segments of unused capacity of physical computer-readable storage media co-located with computing devices that are communicationally coupled to one another through network communications. The computing devices execute one or more of a client process, a storage process and a controller process. The controller processes manage the metadata of the virtual disk, including a virtual disk topology that defines the relationships between certain ones of the physical computer-readable storage media and a particular virtual disk. The client process provide data for storage to certain ones of the computing devices executing the storage processes, as defined by a virtual disk topology, and also read data from storage from those computing devices. The client process additionally expose the virtual disk in the same manner as any other computer-readable medium.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 8, 2014
    Assignee: Microsoft Corporation
    Inventors: Jeffrey B. Hamblin, Saurabh Gupta, Justin Neddo, Joseph Sherman
  • Patent number: 8775686
    Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: July 8, 2014
    Assignee: Netronome Systems, Incorporated
    Inventor: Gavin J. Stark
  • Patent number: 8775748
    Abstract: One embodiment is a method for tracking data correspondences in a computer system including a host hardware platform, virtualization software running on the host hardware platform, and a virtual machine running on the virtualization software, the method including: (a) monitoring one or more data movement operations of the computer system; and (b) storing information regarding the one or more data movement operations in a data correspondence structure, which information provides a correspondence between data before one of the one or more data movement operations and data after the one of the one or more data movement operations. The “monitoring” may comprise monitoring data movement at one or more of an interface between the host hardware platform and the virtualization software, and an interface between the virtual machine and the virtualization software.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 8, 2014
    Assignee: VMware, Inc.
    Inventors: Osten Kit Colbert, Geoffrey Pike
  • Patent number: 8769147
    Abstract: System, apparatus, and methods for dynamically managing logical path resources are provided. The logical path resources are managed by adding, removing, and establishing logic paths based on specified priority schemes associated with the logical path resources. Information associated with the logical path resources is updated in a logical path resource table.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Juan A. Coronado, Roger G. Hathorn, Bret W. Holley
  • Patent number: 8725965
    Abstract: Systems and methods are provided for storing and restoring digital data. In some implementations, a method is provided. The method includes detecting a remote storage device, prompting the user to use the detected remote storage device for backup operations, receiving a user input to use the detected remote storage device for backup operations, and automatically configuring backup operations using the remote storage device. Other embodiments of this aspect include corresponding systems, apparatus, computer program products, and computer readable media.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: May 13, 2014
    Assignee: Apple Inc.
    Inventors: David Hart, Christopher Wolf, Pavel Cisler, Robert Ulrich, Kevin Tiene, Mike Metas
  • Patent number: 8719466
    Abstract: A method for performing direct memory access includes obtaining, by a application executing on a host, a kernel address space identifier of a first driver kernel memory. The application sends the kernel address space identifier to a second device driver. The second device driver obtains, using the kernel address space identifier, a cookie structure binding the first driver kernel memory to a second device driver address space for the first driver kernel memory. The application sends a request for a direct memory access operation. The request includes a location identifier of a location storing a data object in the first driver kernel memory. Based on the cookie structure, the second device driver performs, using the location identifier, the direct memory access operation to transfer the data object from the first driver kernel memory to a second driver kernel memory.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: May 6, 2014
    Assignee: Oracle International Corporation
    Inventors: Jeffrey David Duncan, Damon Neil Clark
  • Patent number: 8700807
    Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 15, 2014
    Assignee: ASPEED Technology Inc.
    Inventors: Hung-Ju Huang, Shu-An Huang Ho, Jen-Min Yuan
  • Patent number: 8694750
    Abstract: Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 8, 2014
    Assignee: NVIDIA Corporation
    Inventors: Dmitry Vyshetsky, Paul Gyugyi
  • Patent number: 8688925
    Abstract: For optimized communication between two memory-related processes in a computer system, a synchronization function is coupled with an operating system function such that it withholds an output of an operating system message that signals a data end of a file in a memory region of the computer system. It can thus be avoided that a memory read process interrupts the reading of the file because a memory write process has not yet written all data of the file into the corresponding memory region.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: April 1, 2014
    Assignee: Océ Printing Systems GmbH
    Inventor: Herman Lankreijer
  • Patent number: 8682815
    Abstract: The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: March 25, 2014
    Assignee: Google Inc.
    Inventors: Dennis Charles Abts, Daniel Gibson
  • Patent number: 8671265
    Abstract: An access request including a client address for data is received. A metadata server determines a mapping between the client address and storage unit identifiers for the data. Each of the one or more storage unit identifiers uniquely identifies content of a storage unit and the metadata server stores mappings on storage unit identifiers that are referenced by client addresses. The one or more storage unit identifiers are sent to one or more block servers. The one or more block servers service the request using the one or more storage unit identifiers where the one or more block servers store information on where a storage unit is stored on a block server for a storage unit identifier. Also, multiple client addresses associated with a storage unit with a same storage unit identifier are mapped to a single storage unit stored in a storage medium for a block server.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 11, 2014
    Assignee: SolidFire, Inc.
    Inventor: David D. Wright
  • Patent number: 8624916
    Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: January 7, 2014
    Assignee: Nvidia Corporation
    Inventors: Narayan Kulshrestha, Adam Paul Dreyer, Chad D. Walker, Rui M. Bastos
  • Patent number: 8583643
    Abstract: An electronic document references one or more electronic document resources stored on a host device. The host device may indicate in the electronic document that an electronic document is cacheable by a client device. When an electronic document resource is identified as cacheable by the client device, the client device caches the electronic document resource in a database stored in a computer-readable medium of the client device. The client device may also generate an electronic document resource catalog that identifies those electronic document resources that are cached in the database. When the client device next requests the electronic document from the host device, the client device may transmit the electronic document resource catalog to the host device. Upon receiving the electronic document resource catalog, the host device may modify the electronic document so that the electronic document references the electronic document resources cached in the database of the client device.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 12, 2013
    Assignee: Google Inc.
    Inventor: Steven T. Kanefsky
  • Patent number: 8583311
    Abstract: A storage battery control device detects an overhead wire supply current value showing a sum of a current value output from a storage battery and a current value output from a transformer substation, and charging or discharging of the storage battery is controlled so that a charging rate of the storage battery becomes a charging rate target value when the detected overhead wire supply current value is less than a first threshold. In addition, charging or discharging of the storage battery is controlled so that the output voltage of the storage battery control device is maintained at a constant voltage control mode when the detected overhead wire supply current value is greater than or equal to the first threshold.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: November 12, 2013
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Kenji Takao, Katsuaki Morita
  • Patent number: 8578331
    Abstract: In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method includes receiving an identifier, receiving output from a command line utility, and storing the command line utility output in a system storage at a location identified by the identifier. In one illustrative embodiment, command line utility output is stored in a system registry database. In another illustrative embodiment, command line utility output is stored in a shared system memory. The method may be stored in any media that is readable and executable by a computer system.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventor: James McKeeth
  • Patent number: 8566510
    Abstract: A system and method for merging sectors of a flash memory module, the method includes: receiving multiple sectors, each received sector is associated with a current erase block out of multiple (L) erase blocks; accumulating the received sectors in a sector buffer, the sector buffer is stored in a non-volatile memory module; maintaining a merged sector map indicative of a sectors of the sector buffer that have been merged and sectors of the sector buffer waiting to be merged; finding a first sector waiting to be merged according to the merged sector map; merging the first sector and other sectors that belong to a same erase block as the first sector; and updating the merged sector map to indicate that that the first second and the other sectors that belonged to the same erase block were merged.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: October 22, 2013
    Assignee: Densbits Technologies Ltd.
    Inventor: Hanan Weingarten
  • Patent number: 8566669
    Abstract: A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: October 22, 2013
    Assignee: OCZ Technology Group Inc.
    Inventor: Franz Michael Schuette
  • Patent number: 8561078
    Abstract: The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Throughputer, Inc.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 8554980
    Abstract: In one embodiment, a virtual frame director may receive association data regarding a virtual server and a physical server, send instructions to a management module based on the received association data, send a control command to the physical server based on the received association data, and send a notification regarding completion of an association between the virtual server and the physical server. A management module may configure the virtual server and/or a gateway according to the instructions received from the virtual frame director. In one embodiment, a virtual frame director may receive a request message for a server, determine whether the request message for the server meets a policy implemented in the virtual frame director, and perform an action directed by the policy when the request message meets the policy.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: October 8, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: Patrick Glen Bose
  • Patent number: 8538720
    Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ming-Yuan Hsu
  • Patent number: 8527802
    Abstract: A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: September 3, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Thinh Tran, Joseph Tzou
  • Patent number: 8478797
    Abstract: A device maintains, in a database, a plurality of data items, each data item of the plurality of data items being associated with a respective category. The device associates, in the database, a first counter value with each data item, the first counter value indicating a number of times the respective category has been deleted from the database at a time when the data item was stored in the database. The device associates, in the database or another database, a second counter value with the respective category, the second counter value indicating a current value for a number of times the respective category has been deleted from the database. The device selectively deletes, from the database, one or more data items of the plurality of data items from the database based on the first counter values and the second counter value.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: July 2, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Clifford E. Kahn, Roger A. Chickering
  • Patent number: 8468310
    Abstract: One embodiment is a method for tracking data correspondences in a computer system including a host hardware platform, virtualization software running on the host hardware platform, and a virtual machine running on the virtualization software, the method including: (a) monitoring one or more data movement operations of the computer system; and (b) storing information regarding the one or more data movement operations in a data correspondence structure, which information provides a correspondence between data before one of the one or more data movement operations and data after the one of the one or more data movement operations.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: June 18, 2013
    Assignee: VMware, Inc.
    Inventors: Osten Kit Colbert, Geoffrey Pike
  • Patent number: 8467906
    Abstract: In a data center that cools servers using an airflow from a central fan, rather than individual server fans, the cooling needs for each server are met by creating a sufficient pressure differential across each server. Because the pressure differential is the same for all of the servers, it is desirable to operate the data center such that each server needs the same pressure differential for proper cooling. Accordingly, a load balancer assigns tasks to the servers based on the known cooling needs of each server in order to balance the pressure differential needed to cool the server. This information may also be sent to the central fan to ensure that a sufficient pressure is created by the fan. Determining the cooling needs beforehand avoids spikes in server temperature, thereby enabling the servers to operate safely at a temperature closer to their maximum rated temperatures.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: June 18, 2013
    Assignee: Facebook, Inc.
    Inventors: Amir Meir Michael, Michael Paleczny
  • Patent number: 8464025
    Abstract: A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an external memory system or local memories 204—0 to 204—3 according to a thread under control from a host processor. Processor units (PU) arrays 202—0 to 202—3 perform image processing by a different thread from the thread of the SCUs 203—0 to 203—3.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: June 11, 2013
    Assignee: Sony Corporation
    Inventors: Yuji Yamaguchi, Masatoshi Imai, Toshiharu Noda, Naosuke Asari, Tomoo Mitsunaga, Mitsuharu Ohki, Kazumasa Ito, Hidetoshi Nagano, Sumito Arakawa, Kei Ito
  • Patent number: 8458434
    Abstract: Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: June 4, 2013
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Zachary A. Pfeffer, Larry A. Bassel
  • Patent number: 8434092
    Abstract: Techniques for allocating computing resources to tasks include receiving first data and second data. The first data indicates a limit for unblocked execution by a processor of a set of at least one task that includes instructions for the processor. The second data indicates a maximum use of the processor by the set. It is determined whether a particular set of at least one task has exceeded the limit for unblocked execution based on the first data. If it is determined that the particular set has exceeded the limit, then execution of the particular set by the processor is blocked for a yield time interval based on the second data. These techniques can guarantee that no time-critical tasks of an embedded system on a specific-purpose device are starved for processor time by tasks of foreign applications also executed by the processor.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: April 30, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: James Miner, Billy Moon, Mickey Sartin
  • Patent number: 8411103
    Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: April 2, 2013
    Assignee: Nvidia Corporation
    Inventors: Narayan Kulshrestha, Adam Paul Dreyer, Chad D. Walker, Rui M. Bastos
  • Patent number: 8397049
    Abstract: In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: March 12, 2013
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen
  • Patent number: 8395996
    Abstract: Techniques that assist in processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. In this manner, the amount of processing that a CPU of the network device has to perform for incoming FDP packets is reduced. This enables the network device to support newer FDPs with shorter periodic interval requirements.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: March 12, 2013
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Wong, Pedman Moobed
  • Patent number: 8392610
    Abstract: A system, apparatus, and method dynamically manages logical path resources by adding, removing, and establishing logic paths based on specified priority schemes associated with the logical path resources. Information associated with the logical path resources is updated in a logical path resource table.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Juan A. Coronado, Roger G. Hathorn, Bret W. Holley
  • Patent number: 8392619
    Abstract: Systems, methods and computer program products for providing indirect data addressing at an I/O subsystem of an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a control word for an I/O operation. The control word includes an indirect data address for data associated with the I/O operation. The indirect data address includes a starting location of a list of storage addresses that collectively specify the data, the list spans two or more non-contiguous storage locations. Data is gathered responsive to the list. The gathered data is transmitted to a control unit in the I/O processing system.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Daniel F. Casper, Mark P. Bendyk, John R. Flanagan, Catherine C. Huang, Matthew J. Kalos, Ugochukwu C. Njoku, Dale F. Riedy, Gustav E. Sittmann, Harry M. Yudenfriend
  • Patent number: 8386701
    Abstract: In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Raymond Scott Tetrick, Dale Juenemann, Robert Brennan
  • Patent number: 8380914
    Abstract: Example embodiments for providing enhanced addressability for a serial flash memory device may comprise providing an extended addressing mode to enable access to a larger range of memory locations.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Chris Bueb, Todd Legler
  • Patent number: 8335893
    Abstract: A memory management device which is capable of allocating a memory unit accessible at a higher speed to data which is stored in a storage device having memory units different in access speed, without being limited in an storage area. The storage device comprises a BLC flash memory accessible at a predetermined access speed, an MLC flash memory accessible at a lower access speed than the predetermined access speed, a controller, and a RAM. The controller manages the BLC flash memory and the BLC flash memory in units each formed by a plurality of physical pages, and writes data in the physical pages, and the RAM holds page allocation information in which logical pages designated when writing data and the physical pages are associated with each other.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: December 18, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yojiro Tagawa
  • Patent number: 8312213
    Abstract: A method to speed up access to an external storage device for accessing to the external storage device comprises the steps of: (a) during startup of a computer, setting up part of a physical memory of the computer as a cache memory for use by the external storage device, in the form of a continuous physical memory area outside the physical memory area that is managed by an operating system of the computer; (b) upon detection of a request to write data to the external storage device, writing the data to the cache memory; and (c) sending the data written in the cache memory to the external storage device to be saved therein.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 13, 2012
    Assignee: Buffalo Inc.
    Inventor: Noriaki Sugahara
  • Patent number: 8312189
    Abstract: A computer program product, an apparatus, and a method for processing communications between a control unit and a channel subsystem in an input/output processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes: sending a command from the channel subsystem to the control unit to initiate an input/output operation; setting a time period for completion of the operation; and responsive to the operation not completing within the time period, sending a message to determine whether the control unit has an exchange open for the command.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Daniel F. Casper, John R. Flanagan, Catherine C. Huang, Matthew J. Kalos, Louis W. Ricci
  • Patent number: 8291150
    Abstract: A table device includes a match cell number output unit 25 for outputting a match cell number showing a cell PE which outputs a matching signal, and an address decoder 26 for specifying a node from among nodes in a search tree which construct a conversion table, the node corresponding to the match cell number. The table device acquires a data conversion value assigned to the above-mentioned node from a configuration memory 21, and, when the data conversion value is data showing a coded result or the like, outputs the data conversion value to outside the table device, whereas when the data conversion value is a branch code of the search tree, updates the cell PE to which a comparison instruction signal is furnished.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: October 16, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomomi El, Noriyuki Minegishi
  • Patent number: 8290991
    Abstract: A device may maintain, in a database, a plurality of data items, each data item of the plurality of data items being associated with a respective category and supplemental information relating to deletion of the data item. The device may associate a group of counters with at least one of the categories and receive a deletion request corresponding to one of the group of categories, the deletion request including the supplemental information. The device may identify a counter associated with the category corresponding to the deletion request based on the supplemental information. The device may then increment the identified counters and selectively delete the data items based on values of the counters.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: October 16, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Clifford E. Kahn, Roger A. Chickering
  • Patent number: 8286179
    Abstract: A system and method for management of jobs in the clustered environment is provided. Each node in the cluster executes a job manager that interfaces with a replicated database to enable cluster wide management of jobs within the cluster. Jobs are queued in the replicated database and retrieved by a job manager for execution. Each job manager ensures that jobs are processed through completion or, failing that, are re-queued on another storage system for execution.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: October 9, 2012
    Assignee: NetApp, Inc.
    Inventor: Michael Comer
  • Publication number: 20120254496
    Abstract: At least first nodes and second nodes of a decision tree are stored within a memory of an information handling system. The first nodes include a first parent node and first remaining nodes that descend from the first parent node. The second nodes include a second parent node and second remaining nodes that descend from the second parent node. The first nodes are grouped into a first packed node stored in first physically contiguous locations of the memory. The first nodes are sequenced in the first physically contiguous locations according to respective depth levels of the first nodes within the decision tree. The second nodes are grouped into a second packed node stored in second physically contiguous locations of the memory. The second nodes are sequenced in the second physically contiguous locations according to respective depth levels of the second nodes within the decision tree.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 4, 2012
    Applicant: Texas Instruments Incorporated
    Inventor: Goksel Dedeoglu
  • Patent number: 8280983
    Abstract: Distributed searches in a casual server network may be provided. First it may be determined, at an originating server, that a first request cannot be fulfilled by information associated with the originating server. Then, from the originating server, the first request may be posted to a distributed request ring. Next, at a remote server on the distributed request ring, the first request may be received. The remote server may then query for current data on a data store associated with the remote server that may satisfy the first request. The remote server may next write a foreign reference in the data store. The foreign reference may indicate that the originating server requested the current data. Next, at the originating server, a response may be received to the first request from the remote server. The response may include the current data.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: October 2, 2012
    Assignee: Microsoft Corporation
    Inventor: Boaz Lev