Abstract: An image forming apparatus includes a memory that stores therein a control program, a central processing unit that executes the control program stored in the memory, a print engine controlled by the central processing unit, and a unit that is selected from a plurality of units. An identification signal generating unit generates identification data indicating a type of the unit. An exclusive OR unit allocates an exclusive OR data of an address data for the central processing unit to access the memory and the identification data to the memory.

Abstract: One embodiment of the invention relates to the transfer of content between a host computer that issues OAS access requests and a block I/O storage system. Specifically, a host computer may issue an access request for a content unit that identifies the content unit is an object identifier. The request may be received by a second server, which may determine the block address(es) on the block I/O storage system at which the content unit is stored. A request may then be sent to the block I/O storage system to retrieve the content stored at the requested block address(es) and the block I/O storage system may return the content.

Abstract: A system and method for creating a backup of a virtual machine running on a host computer is described herein. The system and method operate by creating a copy or “clone” of a virtual machine running on a first host computer on a second host machine connected thereto. After generation of the clone, a backup of the virtual hard disk of the clone can be obtained in a manner that does not consume any resources of the first host machine. The backup of the virtual hard disk of the clone can then be used as the backup of the original virtual machine.

Abstract: A method, computer program and device for the translation of typed data objects in a heterogeneous computational environment is described. The operating system (or installed shared code libraries) translates typed data objects from a first format (e.g., big-endian) to a second format (e.g., little-endian) if the application sending the object and the application receiving the object utilize different formats. By placing data object format translation capabilities into the operating system, the software development effort required to permit an application (e.g., a user-level application) to execute in a heterogeneous environment is significantly reduced.

Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

Abstract: A device maintains, in a database, a plurality of data items, each data item of the plurality of data items being associated with a respective category. The device associates, in the database, a first counter value with each data item, the first counter value indicating a number of times the respective category has been deleted from the database at a time when the data item was stored in the database. The device associates, in the database or another database, a second counter value with the respective category, the second counter value indicating a current value for a number of times the respective category has been deleted from the database. The device selectively deletes, from the database, one or more data items of the plurality of data items from the database based on the first counter values and the second counter value.

Abstract: A system for controlling access to resources in an apparatus when the apparatus is not active. Emerging technologies may allow information to be accessed in an apparatus memory without the operating system of the apparatus facilitating the access. In such instances, a subsystem in the apparatus may become active upon reception of wireless signals, and may grant direct access to memory. An access control configuration for the subsystem may be implemented in order to control memory access even when other software systems are inactive. The subsystem access control configuration may be configured (e.g., by the user) when the apparatus is active, and may be established (e.g., installed or updated) upon subsystem activation.

Abstract: A system configured for facilitating the sharing of information between apparatuses. An apparatus may include one or more applications that, for example, upon configuration and execution, may yield information that may also be stored in the apparatus. At some point a determination may be made that stored information is to be shared with other users. In order to enable the sharing of this information, global identification information may be assigned by, and obtained from, a remote resource. The global identification information may be used to modify identification information corresponding to the information to be shared so that other apparatuses may locate, and/or request access to, the shared information. Further, the other apparatuses may request transmission of shared information stored in the remote resource using the global identifier, or may receive shared information from the apparatus without explicitly requesting it.

Abstract: Medical data is communicated from a transmitter of an external unit to a receiver of an implantable medical device. The transmitter generates a preamble signal having encoded configuration data that informs the receiver of configuration settings to be used in receiving the medical data. The receiver detects the preamble and validates a modulation pattern of the preamble. Configuration data is decoded from the preamble signal and the receiver configuration is adjusted to receive the medical data.

Abstract: An address management method and a device thereof are provided. The address management method includes checking by a device whether logical addresses are currently being used by external devices; and setting by the device a non-use logical address as a logical address of the device regardless of the type of the device, if the device determines that the non-use logical address exists. Therefore, a device may use all logical addresses regardless of its device type, and may also have a logical address even though all logical addresses corresponding to its device type are currently being used.

Abstract: A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a memory control unit. The memory control unit is commonly connected to the first and second memory devices via a command/address bus and a portion of a data bus, and is connected to the second memory device via another portion of the data bus.

Abstract: An apparatus, system, and method are disclosed for object clone event notification. The apparatus is provided with a logic unit containing a plurality of modules configured to functionally execute the necessary steps of detecting an event on a primary software object, referencing a set of clones of the primary software object, and notifying one or more clones in the set of clones of the event in response to the event. The event may include events occurring on the primary software object, or events occurring on a software object monitored by the primary software object. These modules in the described embodiments include a detection module, a reference module, and a notification module. Beneficially, such an apparatus, system, and method would notify object clones of changes within the software system without requiring resource intensive broadcasts or implementation of a separate notification manager.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: Techniques are provided for assisting in the processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. The processing is performed using dual memory structures that enable receipt of FDP packets by the network device to be decoupled from the processing of FDP packets by the CPU of the network device.

Abstract: An address management method and a device thereof are provided. The address management method includes determining by a device whether all logical addresses corresponding to a type of the device are currently being used by external devices; setting by the device a non-use logical address as a logical address of the device, if it is determined that one of the logical addresses is currently not in use; and setting by the device a predetermined logical address as a logical address of the device, if it is determined that all the logical addresses are currently being used. Therefore, logical addresses may be allocated to a device even if all logical addresses corresponding the type of the device are currently being used.

Abstract: A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device.

Abstract: A method and device are disclosed for an associative and approximate, analog or digital scanning of databases that allows for the asynchronous accessing of data from a mass storage medium. The invention includes providing dedicated analog and digital circuitry and decision logic at the mass storage medium level for determining a key identifying the data of interest, continuously comparing the key to a signal generated from a reading of the data from the mass storage medium with an approximate or exact matching circuit to determine a pattern match, determining a correlation value between the key and the data as it is read in a continuous fashion, and determining a match based upon a preselected threshold value for the correlation value. The pattern matching technique eliminates any need to compare data based on its intrinsic structure or value, and instead is based on an analog or digital pattern. The key and data may be either analog or digital.

Abstract: In one embodiment, a method is provided that may include encrypting, based least in part upon at least one key, one or more respective portions of input data to generate one or more respective portions of output data to be stored in one or more locations in storage. The method of this embodiment also may include generating, based at least in part upon the one or more respective portions of the output data, check data to be stored in the storage, and/or selecting the one or more locations in the storage so as to permit the one or more respective portions of the output data to be distributed among two or more storage devices comprised in the storage. Many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: Apparatus, system, and method including a local resource to transfer information between a first processing unit and a second processing unit; and a global resource to transfer information between said first processing unit and said second processing unit, and to transfer information between said first processing unit and a third processing unit if said local resource is full are described.

Abstract: In one embodiment, the present invention includes a method for determining whether an address map of a system includes support for a read only region of system memory, and if so configuring the region and storing protected data in the region. This data, at least some of which can be readable in both trusted and untrusted modes, can be accessed from the read only region during execution of untrusted code. Other embodiments are described and claimed.

Abstract: A state of an input/output (I/O) operation in an I/O processing system is determined. A request for performing the I/O operation is received from an I/O operating system at a channel subsystem and forwarded to a control unit controlling an I/O device for executing the I/O operation. After a predetermined amount of time passes without receiving indication from the control unit that the I/O operation is completed, an interrogation request is received at the channel subsystem from the I/O operating system for determining the state of the I/O operation. An interrogation command is sent from the channel subsystem to the control unit. A response is received from the control unit, the response indicates a state of the I/O device executing the I/O operation, a state of the control unit controlling the I/O device executing the I/O operation, and the state of the I/O operation being executed.

Abstract: An electronic assembly includes electronic modules connected in a series circuit such that a particular number of input connections of one of the electronic modules is connected with the particular number of output connections of another of the electronic modules. Each electronic module is configured to pass on an information which each electronic module receives on an input side at an nth of each electronic module's input connections to an nth of each electronic module's output connections. The input connections and output connections of each electronic module are arranged in a same geometric arrangement.

Abstract: A storage device includes a storage section, a first control section, a communication section, a second control section and a wireless transmission and reception section. The storage section stores data. The first control section controls reading and writing the data from and into the storage section. The communication section transmits and receives the data to and from a higher-level device via a first transmission line. The second control section transmits and receives the data to and from the first control section and the communication section. The wireless transmission and reception section is provided to face a predetermined direction, and wirelessly transmits and receives data to and from another storage device provided in the predetermined direction under control of the second control section.

Abstract: A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for example). The storage system has a function for adding a virtual port to a physical port. The storage system migrates the virtual port addition destination from a first physical port to a second physical port and transmits a request of a predetermined type which includes identification information on the virtual port of the migration target to the switch unit. The transfer management information is updated by the update function of the switch unit so that the transfer destination which corresponds with the migration target virtual port is the switch port connected to the second physical port.

Abstract: An advertising information display method obtains the terminal location information, which is transmitted from a mobile telephone device, a terminal, retail store location information, which is transmitted from a plurality of retail stores, and advertising information, selects the neighborhood advertising information, which should be transmitted to the mobile telephone device, based on the terminal location information and a plurality of retail store location information, associates the terminal ID with the neighborhood advertising information, transmits the neighborhood advertising information to the mobile telephone device, and displays, on the display of the mobile telephone device, the neighborhood advertising information.

Abstract: A device may include polling logic configured to store a table of received addresses, sequentially receive sensor data from each address in the table via a serial data bus, store the sensor data in a memory, receive an address from a processor via a high speed data bus, and provide stored sensor data from the memory to the processor via a parallel data bus.

Abstract: An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result based on the test on the integrated circuit. Trace logic to generate trace data based on the testing result, the trace data being in a parallel format. A serializer is located on the integrated circuit. The serializer converts the parallel format of the trace data into a serial format. The serializer serially outputs the trace data in the serial format from the integrated circuit.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.

Abstract: An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

Abstract: A fast rasterizer uses a fast memory that has a bit-set port for receiving data and a totally independent readout and clear port for outputting a waveform image. The fast memory is organized into rows and columns corresponding to the rows and columns of a raster display device, with each memory location or cell holding a single bit. The fast memory is divided into parallel sections so that one column of each section may be written into each clock cycle, resulting in the possibility of writing a plurality of columns into the fast memory each clock cycle. Each memory cell is set when a row and column write signal for the cell are asserted, and is read out and cleared when a row and column read signal for the cell are asserted. Row logic using thermometer codes is used to set the row lines for the selected column in each section.

Abstract: A transmitter using pseudo-orthogonal code includes a serial-to-parallel converter for converting serial transmission data into 9-bit parallel data, and a pseudo-orthogonal code memory for receiving the parallel data from the serial-to-parallel converter and outputting 16-bit pseudo-orthogonal code by using the received data as addresses. The pseudo-orthogonal code memory has the relationship of the input address and output code, as expressed in the following equation: c(i)=0.5×((?1)b2?(i1b1)?(i0b0) (?1)b5?i2?(i1b4)?(i0b3) (?1)b8?i3?(i1b7)?(i0b6) (?1)( b2?b5?b8)?i3?i2?(i1(b1?b4?b7))?(i0(b0?b3?b6))) where C(i) is a pseudo-orthogonal code value, i is each bit of the pseudo-orthogonal code, 0?i?15, and b0-b8 are a transmission data bit stream input in the memory as addresses. Accordingly, the transmission efficiency of the transmitter/receiver using orthogonal code can be remarkably improved.

Abstract: A hypervisor prepares a guest region identifier (RID)-physical region identifier (RID) mapping table for dynamically registering and managing items and performs RID conversion using the guest RID-physical RID mapping table. When the mapping table is used, since it is unnecessary to provide a specific information area representing logical partitions (LPARs) corresponding to respective guests in an RID to be converted, there is no limitation concerning the number of LPARs and a problem in operation can be eliminated.

Abstract: A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device that contains a cache management unit, a fragment in the message body of the message is cached. Subsequent requests for the fragment at the cache management unit result in a cache hit. A FRAGMENTLINK tag is used to specify the location in a fragment for an included or linked fragment which is to be inserted into the fragment during fragment or page assembly or page rendering. A FRAGMENTLINK tag may include a FOREACH attribute that is interpreted as indicating that the FRAGMENTLINK tag should be replaced with multiple FRAGMENTLINK tags. The FOREACH attribute has an associated parameter that has multiple values that are used in identifying multiple fragments for the multiple FRAGMENTLINK tags.

Abstract: A memory controller including a type determining module and a page determining module. The type determining module is configured to determine a type of memory to which the memory controller is connected, wherein the memory includes a memory block comprising a plurality of pages, and each page includes a plurality of memory cells. The page configure module is configured to generate a memory map based on the determined type of the memory. The memory map specifies, for each page, (i) a number of memory cells for storing data, and (ii) a number of memory cells for storing overhead. The number of memory cells for storing data and the number of memory cells for storing overhead in a first page is configurable to be different from the number of memory cells for storing data and the number of memory cells for storing overhead in a second page.

Abstract: A method, computer program product, and distributed data processing system that enables host software or firmware to allocate virtual resources to one or more system images from a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, is provided. Adapter resource groups are assigned to respective system images. An adapter resource group is exclusively available to the system image to which the adapter resource group assignment was made. Assignment of adapter resource groups may be made per a relative resource assignment or an absolute resource assignment. In another embodiment, adapter resource groups are assigned to system images on a first come, first served basis.

Abstract: One embodiment of the invention relates to the transfer of content between a host computer that issues OAS access requests and a block I/O storage system. Specifically, a host computer may issue an access request for a content unit that identifies the content unit is an object identifier. The request may be received by a second server, which may determine the block address(es) on the block I/O storage system at which the content unit is stored. A request may then be sent to the block I/O storage system to retrieve the content stored at the requested block address(es) and the block I/O storage system may return the content.

Abstract: A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

Abstract: An article of manufacture, an apparatus, and a method for providing extended measurement word data from a control unit to a channel subsystem of an I/O processing system are disclosed. The article of manufacture includes at least one computer usable medium having computer readable program code logic. The computer readable program code logic performs a method including receiving a command message from the channel subsystem at the control unit, and initiating a timing calculation sequence of a plurality of time values in response to receiving the command message at the control unit. The computer readable program code logic also populates extended measurement word data at the control unit including the plurality of time values, and outputs the extended measurement word data from the control unit to the channel subsystem.

Abstract: The invention relates to a verification of applications in interpreted language of the byte-code type (pseudo-code) loaded on portable electronic devices, in particular a chipcard and a method for verification of an application (31) interpreted by a virtual machine (42), said application being loaded on a portable electronic device (1), comprising at least one processor (2) and one RAM (5). The method comprises carrying out the following after loading said application in the device and before validation thereof, checks in the code of said application by means of a process carried out by the processor (2), characterized in comprising, on starting a sub-program, a step of backing up the actual verification context (200 to 203) in the RAM (5), a step for creation and activation of a new verification context (206 to 209) for the sub-program and a step for restoration of the verification context (200 to 203) previously backed-up.

Abstract: Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

Abstract: A ROM is divided into a first area and a second area. A program is stored in the second area and a jump command to the stored program is stored in a specific address of the second area. A call command for the specific address of the second area is stored in the first area.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method includes receiving an identifier, receiving output from a command line utility, and storing the command line utility output in a system storage at a location identified by the identifier. In one illustrative embodiment, command line utility output is stored in a system registry database. In another illustrative embodiment, command line utility output is stored in a shared system memory. The method may be stored in any media that is readable and executable by a computer system.

Abstract: A data storage enclosure management system of a plurality of service processors is configured to communicate externally via a pair of FC-AL loops. Lead and subsidiary service processors are defined and lead service processors connect to ones of the FC-AL loops with an FC-AL address, and the lead and subsidiary service processors are connected by a secondary communication link. The lead service processor(s) employ an identifier unassociated with the FC-AL address to differentiate communications of the lead service processor from communications of an associated subsidiary service processor, the lead service processor serving as a proxy for the associated subsidiary service processor with respect to the FC-AL address and communicating with the associated subsidiary service processor via the secondary communication link.

Abstract: An input apparatus for using an expansion key in a portable terminal includes an expansion key matrix unit which forms a key matrix through which a plurality of expansion keys are input; an input/output (I/O) expansion chip which, in response to a key input through the expansion key matrix unit, transmits a value of an input port of the input/output (I/O) expansion chip to store in an internal parameter, changes the input port to an output port, and vice versa, reads a value of the changed input port, and transmits the read value to the MSM chip to be stored in the internal parameter; and the MSM chip which recognizes a corresponding expansion key based on the stored parameters.