Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: Systems and methods for connection virtualization in data storage device arrays are described. A host connection identifier may be determined for a storage connection request. A target storage device and corresponding completion connection identifier may be determined for a storage command including the host connection identifier. A command tracker may be stored that associates the storage command with the host connection identifier and the completion connection identifier and the storage command may be sent to the processing queue associated with the completion connection identifier.

Abstract: Apparatuses for address expansion and methods of address expansion are disclosed. Memory region definitions are stored, each comprising attribute data relevant to a respective memory region. In response to reception of a first address a region identifier indicative of a memory region to which the first address belongs is provided. Cache storage stores data in association with an address tag and in response to a cache miss a data retrieval request is generated. Address expansion circuitry is responsive to the data retrieval request to initiate a lookup for attribute data relevant to the memory region to which the first address belongs. The address expansion circuitry expands the first address in dependence on a base address forming part of the attribute data to generate an expanded second address, wherein the expanded second address is part of greater address space than the first address.

Abstract: The subject technology receives a query plan corresponding to a query. The subject technology executes the query based at least in part on the query plan, the executing including: filtering a first set of files that are to be modified by a merge statement, performing a split operation to send information related to a second set of files to a scan set builder operation in a first portion of the query plan and scan back operation in a second portion of the query plan, performing the scan set builder operation to remove the second set of files from the first set of files, performing a table scan operation based on a third set of files, and performing a first union all operation to combine the first set of data with a second set of data as a first set of combined data.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

Abstract: Systems and methods enabling garbage collection operations and normal system operations concurrently. Concurrent operations are performed by configuring a similarity group to permit garbage collection and normal operations. This may include creating a new subgroup in a similarity group for write and deduplication purposes such that an impacted subgroup can be cleaned.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.

Abstract: A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to determine that a first allocation unit has a first portion occupying a first plurality of erase blocks and a second portion sharing a second erase block with a portion of a second allocation unit. The processing device is further to relocate data of the portion of the second allocation unit sharing the second erase block with the second portion of the first allocation unit to another erase block and in response to relocating the data of the portion of the second allocation unit, reclaim the first plurality of erase blocks and the second erase block.

Abstract: A distributed storage system includes non-volatile storage storing portions of a first object. The first object encompasses data having a first range of addresses and each portion includes data for a respective range of addresses that is a proper subset of the first range. A first data structure stores, for each portion, data indicating the respective range of addresses and a pointer to where the portion is stored. The first data structure includes a root tree and a set of trees ordered by creation data such that a last tree is most-recently created. The non-volatile storage stores received write data and a write buffer stores index data pointing to storage locations of the received write data. An index management system stores the index data from the write buffer into the last tree and, if the ordered set is empty, creates a tree in the ordered set before the storing.

Abstract: The present disclosure includes apparatuses and methods related to modifying an operating mode in memory. An example apparatus can include a memory array and a controller coupled to the memory array, wherein the controller includes a register configured to receive a mode register write command and write a value indicative of an operating mode in which the apparatus has reduced power consumption relative to a normal operating mode.

Abstract: A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

Abstract: Techniques for data pattern analysis using deterministic finite automaton are described herein. In one embodiment, a number of transitions from a current node to one or more subsequent nodes representing one or more sequences of data patterns is determined, where each of the current node and subsequent nodes is associated with a deterministic finite automaton (DFA) state. A data structure is dynamically allocated for each of the subsequent nodes for storing information associated with each of the subsequent nodes, where data structures for the subsequent nodes are allocated in an array maintained by a data structure corresponding to the current node if the number of transitions is greater than a predetermined threshold. Other methods and apparatuses are also described.

Abstract: Methods, apparatus, and processor-readable storage media for tracking data mirror differences are provided herein. An example computer-implemented method includes obtaining a request to start tracking data differences between a plurality of data mirror volumes of a storage system, wherein the storage system is configured to apply at least a first data tracking technique that tracks the data differences using one or more bitmap records and a second data tracking technique that tracks the data differences using or more journal records; selecting at least one of the first data tracking technique and the second data tracking technique using one or more selection criteria; and tracking the data differences in accordance with the selected at least one data tracking technique.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

Abstract: Methods, non-transitory machine readable media, and computing devices that provide improved dictionary-based compression are disclosed. With this technology, a first portion of an input data stream is compressed using a first dictionary. A second dictionary is trained when the first dictionary is determined to be stale. The dictionary can be determined to be stale based on a size of the input data stream compressed using the first dictionary or a compression ratio decreasing by a threshold, for example. The first dictionary can be stored with metadata associated with the compressed first portion of the input data stream. Accordingly, this technology improves compression ratios, eliminates the need for reference counting, and facilitates improved reclamation of orphan dictionaries, among other advantages.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.

Abstract: Disclosed is a storage device which includes a nonvolatile memory device and a controller. The controller communicates with a host through a first port, communicates with an external storage device through a second port, and controls the nonvolatile memory device based on first mapping information. The controller is configured to receive second mapping information from the external storage device, receive first write data from the host and to selectively transmit first write data to the external storage device based on the second mapping information.

Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.

Abstract: Embodiments of the present invention provide systems and methods for constructing a plan for creating a cloud service. In one embodiment, a configurator receives a request for one or more services making up a cloud service, and a preliminary plan for the requested services is generated. A service provider determines that it is able to fulfill a requested service, and inserts a sub plan for fulfilling the requested service into the preliminary plan. A final plan is generated, which includes a sub plan from each service provider inserted into the preliminary plan.

Abstract: A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

Abstract: A memory system includes a plurality of memory dies configured to store data; and a controller coupled with the plurality of memory dies through a plurality of channels, wherein the controller decides whether to perform a pairing operation, by comparing the number of pieces of read data to be outputted to an external device, which are included in a first buffer, with an output count reference value, and wherein, in the case where the number of pieces of read data stored in the first buffer is greater than or equal to the output count reference value, the controller gathers other read requests and logical addresses corresponding thereto in a second buffer, and performs the pairing operation.

Abstract: Distributed computing systems, devices, and associated methods of virtual RDMA switching are disclosed herein. In one embodiment, a method includes intercepting a command from an application in a container to establish an RDMA connection with a remote container on a virtual network. In response to the intercepted command, an RDMA endpoint at a physical NIC of a server is created. The method can also include intercepting another command to pair with a remote RDMA endpoint corresponding to the remote container. The intercepted another command contains data representing a routable network address of the remote RDMA endpoint in the RDMA computer network. Then, the RDMA endpoint created at the physical NIC of the server can be paired with the remote RDMA endpoint using the routable network address of the remote RDMA endpoint.

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.

Abstract: The present disclosure relates to handling page faults in a constant time. In particular, a data structure of a fixed height is used to store the page tables, allowing for a constant look up time for a particular page. Further, a virtual address descriptor corresponding to the page is used to obtain and load the data into the corresponding instruction data into the page. The virtual address descriptor is directly accessible from the page obtained from walking the page table. This allows page faults to be handled more efficiently in constant time.

Abstract: A data storage device includes a memory device including a normal data region and a mapping data region, the normal data region being configured to store normal data, the mapping data region being configured to store mapping data; a host request managing device configured to manage a read/write request from a host; a mapping managing device configured to cache a part of the mapping data and to manage mapping information according to a request from the host request managing device; and a memory controller configured to manage an operation of the memory device according to a request from at least one of the host request managing device and the mapping managing device.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.

Abstract: A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.

Abstract: A method for storing transaction records includes receiving, by a transaction log manager, a first commit request for a first transaction record from a first core, copying, based on the first commit request, the first transaction record to a first region of memory, making a first determination that the first region surpasses a space threshold, and copying, based on the first determination, a first plurality of transaction records from the first region to storage, wherein the first plurality of transaction records comprises the first transaction record.

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

Abstract: A system for storing and retrieving configuration data causes time-based and content-based indexes to be stored on a storage service. The system receives a request to identify the value of a property during a time period indicated by the request. The system retrieves, from the storage service, a time-based index associated with the time period. The retrieved time-based index is searched to identify a content index associated with the time period. The system retrieves the content index from the storage service, and searches the content index to identify a value, of the property, that is associated with the time period. The system generates a response to the request based on the results of the search of the content index.

Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.

Abstract: A method, computer program product and system are provided. The method, computer program product and system execute a process for storing an object in an object container that is stored in a persistency of a disk storage. The object container has size criteria whereby objects meeting the size criteria of the object container can be assigned to the object container. The object container can facilitate storing multiple objects to optimize disk storage usage by facilitating the assigning of multiple objects to the same disk storage page.

Abstract: An apparatus includes a processing device configured to generate log records each representing a pointer from a leaf page in a logical address space of a storage system to a virtual block address and comprising a leaf page address of the leaf page. The processing device is also configured to identifying a subset of the log records representing pointers to a given virtual block address to determine a first reference count, and to determine whether the first reference count is different than a second reference count obtained from a given virtual entry of a given virtual block structure that corresponds to the given virtual block address. The processing device is further configured, responsive to determining that the first and second reference counts are different, to modify pointers to the given virtual block address in leaf pages with associated leaf page addresses in the identified subset of the log records.

Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.

Abstract: A data processing system can use a method of fine-grained address space layout randomization to mitigate the system's vulnerability to return oriented programming security exploits. The randomization can occur at the sub-segment level by randomizing clumps of virtual memory pages. The randomized virtual memory can be presented to processes executing on the system. The mapping between memory spaces can be obfuscated using several obfuscation techniques to prevent the reverse engineering of the shuffled virtual memory mapping.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.

Abstract: A data storage device may include a storage that store data in a plurality of physical storage spaces to which physical addresses are assigned, respectively, and a controller that control the storage, wherein the controller includes a mapping table of the physical addresses corresponding to logical addresses managed by a host, and wherein the controller is further configured to read data, in a primary read operation, from a physical storage space of a physical address corresponding to a logical address requested to be read by the host among the plurality of physical storage spaces according to the mapping table, obtain a normal physical address corresponding to the logical address requested to be read through the mapping table when the data read in the primary read operation is erased data; and read data, in a secondary read operation, from a physical storage space of the normal physical address.

Abstract: Methods, systems, and computer storage media for providing data operations using hard links (hard link operations) for files in a file system are provided. Accessing files using hard link operations is based on File_Name-to-File_ID mappings and File_ID-to-File_Object mappings stored in hard link data structures. In operation, a file name for file content is received to perform a data operation. The file content is accessed using the file name. The file name is associated with a hard link data structure having a File_Name-to-File_ID mapping and a File_ID-to-File_Object mapping. The file name is also associated with an alternate file name for the file content. The alternate file name is associated with an alternate hard link data structure having an alternate File_Name-to-File mapping and the File_ID-to-File_Object mapping. The alternate file name is received. The file content is accessed using the alternate file name to perform an alternate data operation on the file content.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, a plurality of blocks. A maximum number of blocks of the plurality of blocks capable of being copied to a new block may be identified. Data from the maximum number of blocks of the plurality of blocks may be copied to the new block.

Abstract: A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.

Abstract: Provided are a computer program product, system, and method for creating a restore copy from a copy of source data in a repository having source data at different point-in-times. All the source data as of an initial point-in-time is copied to a repository. In response to completing point-in-time copies following the initial point-in-time, change information is transmitted to the repository indicating changed data in the source data that changed between the point-in-time of the point-in-time copy and a subsequent point-in-time. For each point-in-time copy, copying changed source data comprising source data indicated in the change information for the point-in-time copy as changed to the repository. A restore request is received to restore the source data as of a restore point-in-time. The source data in the repository as of the restore point-in-time is copied from the repository to a restore copy.

Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory, with the processing device being configured to maintain a content-based signature cache for a plurality of data pages. For each of a plurality of read operations to be directed to a distributed content addressable storage (CAS) system, the processing device determines if a data page targeted by the read operation has a corresponding content-based signature in the content-based signature cache. Responsive to the data page having a content-based signature in the content-based signature cache, the processing device identifies a particular storage node that stores the data page in the distributed CAS system, and directs the read operation to the identified storage node using the content-based signature to specify the data page targeted by the read operation. The processing device illustratively comprises a host device coupled to the CAS system over a network.