Directories And Tables (e.g., Dlat, Tlb) Patents (Class 711/205)
  • Publication number: 20130179638
    Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.
    Type: Application
    Filed: February 26, 2013
    Publication date: July 11, 2013
    Applicant: APPLE INC.
    Inventor: Apple Inc.
  • Patent number: 8484434
    Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: July 9, 2013
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Martin Karlsson, Shailender Chaudhry
  • Patent number: 8473684
    Abstract: A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bret R. Olszewski, Basu Vaidyanathan, Steven W. White
  • Publication number: 20130151809
    Abstract: An arithmetic processing device includes: an processing unit configured to execute threads and output a memory request including a virtual address; a buffer configured to register some of address translation pairs stored in a memory, each of the address translation pairs including a virtual address and a physical address; a controller configured to issue requests for obtaining the corresponding address translation pairs to the memory for individual threads when an address translation pair corresponding to the virtual address included in the memory request output from the processing unit is not registered in the buffer; table fetch units configured to obtain the corresponding address translation pairs from the memory for individual threads when the requests for obtaining the corresponding address translation pairs are issued; and a registration controller configured to register one of the obtained address translation pairs in the buffer.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 13, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Patent number: 8458412
    Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Sailesh Kottapalli, John H. Crawford, Kushagra Vaid
  • Patent number: 8452942
    Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck
  • Patent number: 8447936
    Abstract: A method for managing software modules of at least two operating systems sharing physical resources of a computing environment, but running in different partitions separated by a virtualization boundary comprises accumulating module information in a virtualization subsystem that directs the creation and management of the partitions. The accumulated module information is used across the virtualization boundary to manage the use of the software modules. Also, a method for managing software modules comprises making at least two operating systems aware that they are being hosted in a virtualized computing environment.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 21, 2013
    Assignee: Microsoft Corporation
    Inventors: Douglas A. Watkins, Idan Avraham
  • Patent number: 8433852
    Abstract: In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: April 30, 2013
    Assignee: Intel Corporation
    Inventors: Shiliang Hu, Youfeng Wu
  • Patent number: 8433853
    Abstract: A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: April 30, 2013
    Assignee: VIA Technologies, Inc
    Inventors: Colin Eddy, Rodney E. Hooker
  • Patent number: 8429378
    Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: April 23, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Erich James Plondke, Muhammad T. Rab
  • Patent number: 8429376
    Abstract: A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: April 23, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Erin A. Handgen
  • Publication number: 20130097402
    Abstract: Embodiments of the present disclosure provide a data prefetching method, a node, and a system. The method includes: a first storage node receives a read request sent by a client, determines a to-be-prefetched data block and a second storage node where the to-be-prefetched data block resides according to a read data block and a set to-be-prefetched data block threshold, and sends a prefetching request to the second storage node, the prefetching request includes identification information of the to-be-prefetched data block, and the identification information is used to identify the to-be-prefetched data block; and the second storage node reads the to-be-prefetched data block from a disk according to the prefetching request, and stores the to-be-prefetched data block in a local buffer, so that the client reads the to-be-prefetched data block from the local buffer of the second storage node.
    Type: Application
    Filed: December 7, 2012
    Publication date: April 18, 2013
    Applicant: Huawei Technologies Co., Ltd.
    Inventor: Huawei Technologies Co., Ltd.
  • Patent number: 8417869
    Abstract: A hybrid storage apparatus including a non-volatile memory module, a hard disk module, and a hybrid storage medium controller is provided. The hybrid storage medium controller groups physical blocks of the non-volatile memory module into at least a storage area and a replacement area, and the hybrid storage medium controller configures a plurality of logical blocks for mapping to the physical blocks in the storage area and configures a plurality of logical disk addresses for mapping to physical disk addresses of the hard disk module. The hybrid storage medium controller further configures a plurality of logical access addresses to be accessed by a host system and initially maps a portion of the logical access addresses to the logical blocks and the other logical access addresses to a portion of the logical disk addresses. Accordingly, the hybrid storage apparatus can have improved data access performance and prolonged lifespan.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: April 9, 2013
    Assignee: Phison Electronics Corp.
    Inventor: Ban-Hui Chen
  • Patent number: 8412911
    Abstract: A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 2, 2013
    Assignee: Oracle America, Inc.
    Inventors: Gregory F. Grohoski, Paul J. Jordan, Mark A. Luttrell, Zeid Hartuon Samoail
  • Patent number: 8407450
    Abstract: An electronic device receives satellite signals from positioning information satellites and acquires positioning information and time information. A stored data table comprises a first block of data having a first array of time difference data and a second block of data having a second array of time difference data that is different than the first array of time difference data. A stored memory address table stores the memory address of each of the first and second blocks of data, at least one the blocks of data being stored a plurality of times in the memory address table. The data block corresponding to the acquired positioning information is identified, the memory address corresponding to that data block is read, the data block data indicated by the memory address is acquired, and the time difference data for the segment corresponding to the positioning information is acquired from the data block.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 26, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Oh Jaekwan
  • Patent number: 8402247
    Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 19, 2013
    Assignee: NetApp, Inc.
    Inventors: Garth R. Goodson, Rahul N. Iyer
  • Patent number: 8397049
    Abstract: In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: March 12, 2013
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen
  • Patent number: 8386745
    Abstract: An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables. The selected device table entry for the given request may include a pointer to the set of guest translation tables, and a last guest translation table includes a pointer to the set of nested page tables.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: February 26, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Mark D. Hummel
  • Patent number: 8386744
    Abstract: A method for migrating data to a mass storage system, including receiving an incoming data partition for storage in the mass storage system and allocating logical storage for the incoming data partition in the mass storage system. The method further includes making a determination that the incoming data partition includes only zero data, and, in response to the determination, inhibiting physical storage of the incoming data partition in the mass storage system while maintaining the allocated logical storage for the incoming data partition.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ofir Zohar, Shemer Schwartz, Haim Helman, Ehood Garmiza, Omri Palmon, Efri Zeidner
  • Patent number: 8386748
    Abstract: An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 26, 2013
    Assignee: Apple Inc.
    Inventor: Joseph A. Petolino, Jr.
  • Patent number: 8380951
    Abstract: Various embodiments of a system and method for updating backup configuration information used by backup software to perform backup operations for a storage cluster are described. Backup configuration information specifying a configuration of the storage cluster may be stored. Subsequently, a particular change to the configuration of the storage cluster may be automatically detected. In response to detecting the particular change, the backup configuration information may be automatically updated to reflect the particular change to the configuration of the storage cluster. Subsequent backup operations may then be performed using the updated backup configuration information.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: February 19, 2013
    Assignee: Symantec Corporation
    Inventors: Thomas L. Krinke, II, James P. Ohr
  • Patent number: 8364932
    Abstract: The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: January 29, 2013
    Assignee: VMware, Inc.
    Inventors: Qasim Ali, Raviprasad Mummidi, Vivek Pandey, Kiran Tati
  • Patent number: 8356158
    Abstract: One or more methods and systems of improving performance and reducing the size of a translation lookaside buffer are presented. In one embodiment, the method comprises using a bit obtained from a virtual page number to store even and odd page frame numbers into a single page frame number field of a miniature translation lookaside buffer (mini-TLB). In one embodiment, even and odd page frame number fields are consolidated into a single page frame number field. In one embodiment, the mini-TLB facilitates the use of a buffer or memory of reduced size. Furthermore, in one or more embodiments, aspects of the invention may be found in a system and method that easily incorporates and adapts the use of existing control processor instruction sets or commands of a typical translation lookaside buffer.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: January 15, 2013
    Assignee: Broadcom Corporation
    Inventors: Kimming So, Jane Lu
  • Patent number: 8356020
    Abstract: A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D?1 and 2D for maximum compression. Storage requirements are reduced.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 15, 2013
    Assignee: Green Investment Fund, L.L.C.
    Inventor: Millind Mittal
  • Patent number: 8352708
    Abstract: A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: January 8, 2013
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Yu-Yuan Chen
  • Patent number: 8352706
    Abstract: A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing unit at a time of start-up. When an event occurs so that the master table needs to be updated, difference information before and after update of any one of the forward lookup address translation table and the reverse lookup address translation table is recorded in the first storing unit as a log, thereby reducing an amount of the log.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokuni Yano, Toshikatsu Hida
  • Patent number: 8347063
    Abstract: A method of improving USB device virtualization is proposed that allows giving virtual machines (VMs) direct access to USB devices with a combination hardware and software solutions. The USB host controller replaces device identifiers assigned by the VM with real device identifiers that are unique in the system. The real device identifiers are assigned by the virtual machine monitor (VMM) or the host controller.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Kiran Panesar, Philip Lantz
  • Patent number: 8327112
    Abstract: A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a corresponding physical address page. The processing system also includes a translation lookaside buffer adapted to cache page table information. The processing system also includes memory management software responsive to changes in the page table to consolidate a run of contiguous page table entries into one or more page table entries having a larger memory page size, Y. The memory management software further determines whether the run of contiguous page table entries may be cached in an entry of the translation lookaside buffer that caches multiple page table entries, X, in a single translation lookaside buffer entry.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: December 4, 2012
    Assignee: QNX Software Systems Limited
    Inventor: Brian Stecher
  • Patent number: 8316211
    Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Uday Savagaonkar, Madhavan Parthasarathy, Ravi Sahita, David Durham
  • Patent number: 8316209
    Abstract: A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Wanmo Wong
  • Patent number: 8307183
    Abstract: A recording and/or reproducing method, a recording and/or reproducing apparatus, and an information storage medium are provided. The method of recording data to an information storage medium includes: according to a change in a method of using the information storage medium, rearranging the order of a first information structure with a variable size and a second information structure with a fixed size, both of which are included in management information of the information storage medium, so that the first information structure with the variable size can be positioned following the second information structure with the fixed size; and recording the rearranged management information on the information storage medium. According to the method and apparatus, recording management information can be found in a fixed location of a finalized information storage medium, thereby allowing the recording management information to be found easily and quickly.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Joon-hwan Kwon
  • Patent number: 8301864
    Abstract: A method for performing rapid memory management unit emulation of a computer program in a computer system, wherein address injection space of predefined size is allocated in the computer system and a virtual page number and a corresponding physical page number are stored in said address injection space, said method comprising steps of: comparing the virtual page number of the virtual address of a load/store instruction in a code segment in said computer program with the virtual address page number stored in said address injection space; if the two virtual page numbers are the same, then obtaining the corresponding physical address according to the physical page number stored in said address injection space; otherwise, performing address translation lookaside buffer search, that is, TLB search to obtain the corresponding physical address; and reading/writing data from/to said obtained corresponding physical address.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hua Yong Wang, Kun Wang, Honesty Young
  • Patent number: 8301865
    Abstract: A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: October 30, 2012
    Assignee: Oracle America, Inc.
    Inventors: Gregory F. Grohoski, Paul J. Jordan, Mark A. Luttrell, Zeid Hartuon Samoail, Robert T. Golla
  • Patent number: 8285958
    Abstract: A system, method, and computer program product are provided for copying a modified page table entry to a translation look aside buffer. In use, a page table entry corresponding to an original page associated with original code is identified. In addition, a page mapping in a translation look aside buffer is invalidated by calling a processor instruction that invalidates the page mapping. Further, the page table entry is modified to correspond to a different page associated with different code. Still yet, an instruction of the different code is accessed for prompting a processor to copy the modified page table entry to the translation look aside buffer. Moreover, the modified page table entry is restored to correspond to the original page associated with the original code.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: October 9, 2012
    Assignee: McAfee, Inc.
    Inventor: Ahmed Said Sallam
  • Patent number: 8275598
    Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anatoli S. Andreev, Olaf K. Hendrickson, John M. Ludden, Richard D. Peterson, Elena Tsanko
  • Patent number: 8271750
    Abstract: A data processing system includes a data store having storage locations storing entries which can be used for a variety of purposes, such as operand value prediction, branch prediction, etc. An entry profile store stores profile data for more candidate entries than there are storage locations within the data store. The profile data is used to determine replacement policy for entries within the data store. The profile data can include hash values used to determine whether predictions associated with candidate entries were correct without having to store the full predictions within the profile data.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: September 18, 2012
    Assignee: ARM Limited
    Inventors: Sami Yehia, Marios Kleanthous
  • Patent number: 8271711
    Abstract: A method for a computer including a processor that is capable of counting invalidation of translation lookaside buffers and generating an interrupt at the occurrence of the invalidation, the invalidation being performed by an operating system upon switching between application programs, includes acquiring identification information of application programs from the operating system and storing the identification information as a first list; detecting an interrupt generated from the processor at the occurrence of switching from a first application program to a second application program; and when the interrupt is detected, acquiring the identification information of the first and second application programs from the operating system or the mechanism and comparing the acquired identification information with the first list to determine whether either of the first and second application programs is a program that has been created or disappeared.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Fujitsu Limited
    Inventors: Akira Hirai, Kouichi Kumon
  • Patent number: 8250332
    Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: August 21, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Ajay Ingle
  • Patent number: 8250330
    Abstract: A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.
    Type: Grant
    Filed: December 11, 2004
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Eric N. Lais, Donald R. DeSota, Michael Grassi, Bruce M. Gilbert
  • Patent number: 8250335
    Abstract: The present invention provides for a method, system, and computer program product for managing the storage of data. Data is selectively compressed based on a pre-defined compression policy and metadata is stored for physical storage blocks. A stored compression policy identifies at least one criterion for compression, and physical blocks of data meeting the compression policy are identified. A physical block is selected as a source block for data compression, and one or more physical locations are selected as target locations. Data is read from the source block, compressed, and written to the target locations. Metadata is updated to indicate a mapping between the target locations and the virtual blocks previously mapped to the source block. Extra storage capacity can be freed up until more physical storage is ordered and installed, while more important data, such as recently or frequently accessed data, is retained in an uncompressed and accessible state.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Barry D. Whyte, Geoff Lane, Simon Walsh
  • Patent number: 8239620
    Abstract: A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: August 7, 2012
    Assignee: Mips Technologies, Inc.
    Inventor: James Robert Howard Hakewill
  • Patent number: 8239656
    Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 7, 2012
    Inventors: Guillermo Rozas, Alexander Klaiber, H. Peter Anvin, David Dunn
  • Patent number: 8239652
    Abstract: Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion section is provided in a subsequent stage of the arbitration section. Without waiting for the completion of buffer update, an access is issued in advance at a time when it is assured that update is completed at the completion of address conversion. Thus, influences of waiting buffer update on another master can be eliminated and access latency can be reduced.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: August 7, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuki Soga, Isao Kawamoto, Daisuke Murakami
  • Patent number: 8225071
    Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: July 17, 2012
    Assignee: VMware, Inc.
    Inventors: Xiaoxin Chen, Alberto J. Munoz
  • Patent number: 8225070
    Abstract: An information processing apparatus including a main memory and a processor, the processor includes: a cache memory that stores data fetched to the cache memory; an instruction processing unit that accesses a part of the data in the cache memory sub block by sub block; an entry holding unit that holds a plurality of entries including a plurality of block addresses and access history information; and a controller that controls fetching of data from the main memory to the cache memory, while the access by the instruction processing unit to sub blocks of data in a block indicated by another of the entries immediately preceding the one of the entries, in accordance with order of the access from the instruction processing unit to sub blocks in the block indicated by the another of the entries and access history information associated with the one of the entries.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: July 17, 2012
    Assignee: Fujitsu Limited
    Inventors: Hideki Okawara, Iwao Yamazaki
  • Patent number: 8219780
    Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 10, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James R. Callister, Eric R. Delano, Rohit Bhatia, Shawn Kenneth Walker, Mark M. Gibson
  • Publication number: 20120166756
    Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 28, 2012
    Applicant: Oracle International Corporation
    Inventors: Paul Caprioli, Martin Karlsson, Shailender Chaudhry
  • Patent number: 8209488
    Abstract: A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: June 26, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Balaram Sinharoy, William E. Speight, Lixin Zhang
  • Patent number: 8205030
    Abstract: There is provided a composite type recording apparatus restricting write operations depending on the type of a connected host apparatus, including a recording medium having a first data region, a non-volatile storage medium having a second data region and an identification information table for integrating and managing the first and second data region, an information selection section for selecting positional information having predetermined identification information from the identification information table according to the type of the host apparatus, a conversion section for converting positional information selected by the information selection section into positional information matching the first data region or positional information matching the second data region, a first write section for writing data supplied from the host apparatus in the first data region according to conversion process of the conversion section and a second write section for writing data supplied from the host apparatus in the se
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: June 19, 2012
    Assignee: Sony Corporation
    Inventors: Hajime Nishimura, Takeshi Sasa, Tetsuya Tamura, Kazuya Suzuki
  • Patent number: 8205064
    Abstract: In certain systems, local requests require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request is present. If the associated information is present, a request is placed in an output request queue to service the local request. If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 19, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony F. Vivenzio, Denis J. Foley