Abstract: Mechanisms to protect the integrity of memory of a virtual machine are provided. The mechanisms involve utilizing certain capabilities of the hypervisor underlying the virtual machine to monitor writes to memory pages of the virtual machine. A guest integrity driver communicates with the hypervisor to request such functionality. Additional protections are provided for protecting the guest integrity driver and associated data, as well as for preventing use of these mechanisms by malicious software. These additional protections include an elevated execution mode, termed “integrity mode,” as well as protections on the memory pages that store the guest integrity driver. To prevent spurious alerts associated with the GI driver accessing its own data, the hypervisor maintains two page tables. In one copy, pages storing data for the GI driver are not protected and in the other, those pages are protected. The hypervisor switches the page tables when entering and exiting integrity mode.

Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.

Abstract: A transmitting computer for a vehicle is disclosed, and includes a command circuit, a monitor circuit, and a master circuit. The command circuit receives a real-time signal and executes a first set of instructions to analyze the real-time signal, and generates a plurality of command signals based on executing the first set of instructions. The monitor circuit receives the command signals and the real-time signal. The monitor circuit executes a second set of instructions to analyze the real-time signal and generates a plurality of replica signals based on executing the second set of instructions. The monitor circuit generates an initial reset command in response to determining an initial miscompare between one of the plurality of command signals and the plurality of replica signals. The master circuit is in communication with both the command circuit and the monitor circuit and receives an indication that the initial reset command is generated.

Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

Abstract: According to an aspect of the present disclosure, a kernel space and a user space for execution of instructions is provided in a computer system. A process executes in the user space and multiple modules execute in the kernel space, with the modules also generating events. It is then determined whether the generated events includes a set of events matching a pre-specified pattern representing a malicious process. If such as set of events is determined to be present, the process is notified as a malicious process. The steps of determining and notifying are performed in user space.

Abstract: An apparatus and method is described herein for providing structures to support software memory re-ordering within atomic sections of code. Upon a start or end of a critical section, speculative bits of a translation buffer are reset. When a speculative memory access causes an address translation of a virtual address to a physical address, the translation buffer is searched to determine if another entry (a different virtual address) includes the same physical address. And if another entry does include the same physical address, the speculative execution is failed to provide protection from invalid execution resulting from the memory re-ordering.

Abstract: An apparatus, method, and computer-readable storage medium for allowing a block-addressable storage device to provide a sparse address space to a host computer. The storage device exports an address space to a host computing device which is larger than the storage capacity of the storage device. The storage device translates received file system object addresses in the larger address space to physical locations in the smaller address space of the storage device. This allows the host computing device more flexibility in selecting addresses for file system objects which are stored on the storage device.

Abstract: Associating working sets and threads is disclosed. An indication of a stalling event is received. In response to receiving the indication of the stalling event, a state of a processor associated with the stalling event is saved. At least one of an identifier of a guest thread running in the processor and a guest physical address referenced by the processor is obtained from the saved processor state.

Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Abstract: A method for protecting a computer includes identifying a first pointer in a data structure used by a computer program indicating a first memory address to be accessed, using the pointer, in order to invoke a functionality of the computer. The identified first pointer is replaced with a second pointer indicating a second memory address, different from the first memory address. A security program module traps attempts to access the second memory address during execution of the computer program so as to foil unauthorized access to the functionality of the computer.

Abstract: The subject matter disclosed herein provides methods for reformatting a page due to a rollover. An in-memory array holding a column of data can be maintained. One or more pages can be maintained. Each page can have one or more rows for storing the column of data. The column of data in the in-memory array can be monitored for a change. A rollover can be performed on at least one of the pages based on the change. The rollover can reformat the at least one page by rewriting metadata associated with the at least one page. Related apparatus, systems, techniques, and articles are also described.

Abstract: The present disclosure generally relates to a method and system for efficiently sharing limited memory among multiple processors. Each processor has a local linked list. The local linked list identifies the pages allocated to the specific processor as well as the number of free codewords for each allocated page. Additionally, the local linked list includes the location of the next free codeword(s) for each allocated page. When all codewords are available, the page is considered free and may be sent back to the page pool used by all of the processors. If there are a sufficient number of contiguous free codewords on an allocated page, then new codeword data may be stored in the page. If there is not a sufficient number of contiguous free codewords on any allocated page, then a new page is allocated from the page pool. Thus, efficient allocate of memory resources is achieved.

Abstract: Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.

Abstract: A computer-implemented method includes receiving from a codeset compiler a request for a codeset converter to convert from a source codeset to a target codeset. A mapping table is generated responsive to the request, where the mapping table maps from the source codeset to the target codeset. An applicable codeset converter compiler is selected, from among a plurality of available codeset converter compilers, for compiling a requested codeset converter from the source codeset to the target codeset. The requested codeset converter is compiled with the applicable codeset converter compiler, using a computer processor, responsive to the request. The requested codeset converter is returned to the codeset compiler.

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Abstract: Allocating free space in a database table. Statistics associated with records in a database are received, including an average record byte size for records stored in the database table. A primary free space byte size for record updates is determined, including comparing a preliminary free space byte size to the average record byte size and a byte size of a record subjected to a database operation. Based on the primary free space byte size, free space at the page level of the database table is allocated.

Abstract: Systems, methods, and software can be used to launch an application. In some aspects, a plurality of process classes is configured. Each of the plurality of process classes includes one or more applications. Each of the process classes is configured to be associated with a template process. Each template process is associated with a different randomized memory layout. A launch request for an application is received. A process class that is associated with the application is determined in response to the launching request. The application is launched using the template process associated with the determined process class.

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a control circuit. The control circuit executes data transfer between the host and the first memory and managing translation information indicating a relation between logical location information and physical location information. The logical location information is location information designated from the host. The physical location information is location information physically indicating location in the first memory. The control circuit separates out the translation information into a plurality of levels in a hierarchy. The translation information includes first translation information which belongs to the first level in the hierarchy and second translation information which belongs to the second level in the hierarchy. The size of the first translation information and the size of the second translation information are the same.

Abstract: There is disclosed a technique for use in managing multi-granularity flash translation layers in solid state drives. An SSD comprising a flash translation layer (FTL) table and flash memory space is provided. The FTL table is reconfigured into a plurality of multiple sub-tables, where a first sub-table has a first logical page size and a second sub-table has a second logical page size, the first logical page size being smaller than the second logical page size. The flash memory space is reconfigured into multiple flash memory sub-spaces. The first sub-table is mapped to the first flash memory sub-space the second sub-table is mapped to the second flash memory sub-space.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Abstract: A computer program product for optimizing page table manipulations is provided and includes a computer readable storage medium having program instructions that are readable and executable by a processing circuit to cause the processing circuit to create and maintain a translation table with a translation look-aside buffer (TLB) disposed to cache priority translations, update the translation table upon de-registration of a DMA address, allocate entries in the translation table from low to high memory addresses during memory registration, maintain a cursor for identifying where to search for available entries upon performance of a new registration, advance the cursor from entry-to-entry in the translation table and wrap the cursor from an end of the translation table to a beginning of the translation table and issue a synchronous TLB invalidation instruction to invalidate the TLB upon at least one wrapping and an entry being identified and updated.

Abstract: A resource delivery network and method for distributing content in the network is disclosed herein. The network comprises a plurality of servers arranged in tiers and partitioned. Each server includes a resource store with a set of resources for distribution to a successive tier. Updates to each successive tier are provided by a pull-forward client on servers in the tier. This forward propagation mechanism maximizes resource availability at edge servers in the network. Resources transmitted to the edge tier servers may be transformed, combined, and rendered without taxing lower tier servers. Transformation and pre-rendering of data can be performed by low priority CPU tasks at each layer of the system.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.

Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.

Abstract: A data concurrency module maintains a delta chain for each record that stores the edits made to the flexible record over time. The delta chain stores the edits ordered by a version identifier. When the data concurrency module receives an edit to a record, the data concurrency module compares the version identifier associated with the edit with the most recent version identifier stored in the delta chain for that flexible record. If the version identifiers are different, then the data concurrency module merges the edit with all intervening edits in the delta chain, resolving any conflicts that result from the merging.

Abstract: A data storage device includes a memory and a controller. The memory includes a first partition and a second partition. The controller includes a pattern detector that is configured to detect one or more tags in data from an access device to be stored in the first partition. The controller is configured to generate, in the second partition, one or more links to the data that is stored in the first partition, the one or more links organized according to metadata associated with the one or more tags.

Abstract: According to one embodiment, a memory controller includes a memory, an adjustment part, a writing part and a setting change part. The memory stores first data, that includes a write amount with respect to a plurality of regions in a plurality of nonvolatile memories, and second data that includes a write state corresponding to the plurality of nonvolatile memories. The adjustment part selects the nonvolatile memory based on the first data and the second data. The write part writes the data to be written in the selected nonvolatile memory and updates the first data and the second data. The setting change part changes setting of a usable capacity with respect to at least one of the plurality of nonvolatile memories, based on the first data and the second data.

Abstract: Provided herein are devices, systems, methods and various means, including those related to providing a community internet drive that may utilize a centrally-managed hub as well as storage devices distributed among various networked machines. In some embodiments, the community internet drive can also include features to enable its users to promote and utilize the user's trusted personal relationships while also enabling an open platform for peer-to-peer and/or other types of sharing schemes.

Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: Some embodiments provide a method for a network controller that manages a flow-based managed forwarding element (MFE). The method receives multiple service rules for implementation by the MFE. Each service rule matches over a set of network addresses. At least one network address is in the set of network addresses for at least two service rules. The method groups the network addresses into non-overlapping groups of network addresses, each of which addresses that are all matched by only a same set of service rules. The method generates flow entries that match over the groups of network addresses for the MFE to use to implement the service rules.

Abstract: Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Circuits and methods for initializing a memory. Each row of the memory includes data bits and associated parity bits. A write buffer contains bit values for initializing the memory, and a control circuit performs a first set of write operations that write values from the write buffer to the data bits of the memory without writing values to the associated parity bits. The write buffer performs a second set of write operations that write values from the write buffer to the parity bits associated with the data bits without writing data to the data bits.

Abstract: A method for backing up and recovering data is disclosed. Data representing an allocation of a plurality of backup resources to a plurality of restricted data zones is stored in a storage device. Any of the plurality of backup resources allocated to one restricted data zone is not allocated to another restricted data zone. A user is associated with one of the plurality of restricted data zones. Backup and recovery services are provided to the user using one or more backup resources allocated to the restricted data zone associated with the user. The backup and recovery services provided to the user are segregated from backup and recovery services provided to other users associated with restricted data zones that are different from the restricted data zone associated with the user.

Abstract: A flash memory control technology with high efficiency, which records a logical page table in a random access memory. The logical pages that have been collected from a data-interspersed block into a destination block of a flash memory are recorded in the logical page table. Without accessing a logical-to-physical address mapping table stored in the flash memory, the physical pages in the data-interspersed block corresponding to the logical pages recorded in the logical page table are regarded as containing invalid data.

Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

Abstract: Various aspects facilitate implementing a memory translation table associated with key-based indexing. A table component is configured for generating a memory translation table and a key component is configured for allocating a key associated with a memory access based on a virtual address and a set of access permissions. A descriptor component is configured for generating a descriptor associated with the memory translation table that comprises at least the set of access permissions and a portion of the key.

Abstract: Allocating free space in a database table. Statistics associated with records in a database are received, including an average record byte size for records stored in the database table. A primary free space byte size for record updates is determined, including comparing a preliminary free space byte size to the average record byte size and a byte size of a record subjected to a database operation. Based on the primary free space byte size, free space at the page level of the database table is allocated.

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

Abstract: Methods to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.

Abstract: A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

Abstract: A control device includes: a management information generation unit configured to generate or update logical-physical block address management information with respect to either data to be written to a non-volatile memory or data which has been already written in the non-volatile memory, the logical-physical block address management information indicating association between a logical block address and a physical block address on the non-volatile memory; and an access control unit configured to, during write of the data to the non-volatile memory, control write of the data as well as the logical-physical block address management information to a physical write unit of the non-volatile memory.

Abstract: Systems and computer program products to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.