Abstract: Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group.

Abstract: Method and apparatus for ensuring a most recent version of data is retrieved from a memory, such as a non-volatile flash memory array. In accordance with various embodiments, a controller is adapted to sequentially store different versions of an addressable data block having a selected logical address in different locations within a memory. The controller assigns a revision indication value to each said version, with at least two of said stored versions concurrently sharing the same revision indication value. In some embodiments, the revision indication value constitutes a repeating cyclical sequence count that is appended to each block, or logically combined with a code value and stored with each block. The total number of counts in the sequence is less than the total number of versions resident in the memory.

Abstract: A device for recording information on a storage medium (11) is arranged for formatting the storage medium. The device has receives a format command according to a protocol (ATA/ATAPI). The device has formatting means for formatting a multilayer storage medium according to the format command. The formatting includes recording, on each layer (L0, L1) of the multilayer storage medium, a first control zone (71, 72) at a first radial position on the layer and a second control zone (73, 74) at a second radial position on the layer for forming an annular data zone of a selected size between the control zones. If the format size is smaller than a maximum available size on the storage medium, the control zones are positioned on substantially equal radial positions for forming radially corresponding annular data zones (75, 76). The required format size equals the sum of the selected sizes of each annular data zone.

Abstract: Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

Abstract: A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened.

Abstract: Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits.

Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: A method for automatic snapshot includes obtaining the amount of data written into a source Logical Unit Number (LUN) and performing increment accumulation; and taking a snapshot when a value of the increment accumulation exceeds the upper limit value. An apparatus for automatic snapshot is disclosed. In one embodiment of the invention, snapshots are taken according to the size of a data variable, only two characterizing parameters, an upper limit value and an increment value need to be added, and the determination logic is clear and concise. Thus, system efficiency or resource overload is not affected, the pertinence is strengthened, the resource usage is increased, and the adaptability is strengthened. Furthermore, stored data may be automatically protected with snapshot, and data safety and reliability are greatly improved.

Abstract: A device driver includes an aggregator aggregating data blocks into one or more container objects suited for storage in an object store; and a logger for maintaining in at least one log file for each data block an identification of a container object wherein the data block is stored with an identification of the location of the data block in the container object.

Abstract: A storage device, e.g., an SSD, is configured to enable spanning for a logical block between pages of the device. In one example, a device includes a data storage module to receive data to be stored, wherein the data comprises a plurality of logical blocks, and wherein a size of the plurality of logical blocks exceeds a size of a first page of the device, and a spanning determination module to determine whether to partition one of the plurality of logical blocks into a first partition and a second partition, wherein the data storage module is configured to partition the one of the plurality of logical blocks into the first partition and the second partition and to store the first partition in the first page and the second partition in a second, different page when the spanning determination module determines to partition the one of the plurality of logical blocks.

Abstract: A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache.

Abstract: A design information generating equipment is provided. A control component of the design information generating equipment, when a basic function of the plurality of functions constitutes a requested function, and design information that corresponds to the basic function is stored in a second memory area, uses the stored design information, and, when the design information that corresponds to the basic function of the plurality of functions is not stored in the second memory area, uses a source program corresponding to the basic function of the plurality of functions stored in a first memory area, and performs control so as to generate design information corresponding to the basic function of the plurality of functions and stores the generated design information in the second memory area, and, using the generated design information, reconfigures a design configured to execute the requested function, and executes the requested function with the reconfigurable design information.

Abstract: Methods and systems are provided that may be utilized for spilling in query processing environments.

Abstract: There is provided a method of operating a multipath storage system, the method comprises: identifying a primary storage control port configured to be responsible for a given LBA range and a secondary storage control port configured to have secondary responsibility for the given LBA range; reducing, in a manner unaffecting respective inbound I/O operation, outbound I/O operation related to the given LBA range and occurring at the primary storage control port, thereby causing a situation requiring switching all respective I/O requests to an alternating path; analyzing responsive changes in outbound I/O operation related to the given LBA range and occurring at the secondary storage control port, and verifying operability of switching to the alternating path in accordance with the obtained results.

Abstract: A storage apparatus is disclosed which includes: a memory configured to have a plurality of pages to which data can be written in units of a page, the memory being further configured to have a plurality of pages of write data stored into each page in multi-valued form; and a control section configured to select pages to which to write the data from among the plurality of pages of the memory, the control section being further configured to write to the selected pages of the memory the data of at least two bits in multi-valued form for a plurality of pages including the selected pages; wherein, when writing the plurality of pages of the write data, the control section puts the write data into multi-valued form per page before writing the data to a plurality of different unused pages of the memory on a page-by-page basis.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: receiving a first access command from a host; analyzing the first access command to obtain a first host address; linking the first host address to a physical block; receiving a second access command from the host; and analyzing the second access command to obtain a second host address. For example, the method may further include: linking the second host address to the physical block, wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block. In another example, the method may further include: linking the first host address to at least a page of the physical block; and linking the second host address to at least a page of another physical block.

Abstract: A management system detects a peak time period during which accesses are concentrated on a logical page included in a logical volume, and reallocates this logical page to an appropriate physical page. A management server detects an access variation of each logical volume, and selects a volume with a large access variation as a target volume. The management server measures the access status of each logical page in the target volume, and allocates a logical page to a more appropriate physical page.

Abstract: The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

Abstract: The object of the present invention is to efficiently perform access to a physical block corresponding to a logical block often designated by an access request. To realize it, predetermined number of pieces of logical block information each for access to a physical block corresponding to logical block, until then, designated by an access request is held. In holding the predetermined pieces of logical block information, a piece of logical block information having high priority precede a piece of logical block information having low priority in priority order. In management of the priority order, priority of a piece of logical block information corresponding to a logical block often designated by an access request becomes high. When an access request is received, if logical block information corresponding to the logical block designated by the access request is held, access to the physical block corresponding to the designated logical block is performed based on the held logical block information.

Abstract: A hypervisor runs on a host computer system and defines at least one virtual machine. An address space of the virtual machine resides on physical memory of the host computer system under control of the hypervisor. A guest operating system runs in the virtual machine. At least one of a host operating system and the hypervisor sets parts of the address space of the host computer system corresponding to parts of the address space of the virtual machine to a locked state in which those parts can be read but not written to.

Abstract: A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page of stored data comprising an allocated data space addressable in a second increment of address, pointed to by an address pointer, and comprising obsolete data. The first increment of address is greater than the second increment of address. A portion of stored data in the page buffer may be updated with the data to form an updated page of data. Storage space for the updated page of data may be allocated. The updated page of data may be written to the allocated storage space. The address pointer may be updated with a location of the allocated storage space.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: A storage device and method for updating data stored in a partition of the storage device are provided. In one embodiment, a storage device is provided that contains a logical-to-physical address map and a memory with a first partition storing original data and a second partition. The storage device receives from a host device (i) a command to write updated data to a first logical address and (ii) a signature for verifying integrity of the updated data, wherein the first logical address is mapped to a physical address of the first partition. The storage device then stores the updated data in the second partition instead of the first partition and attempts to verify the signature of the updated data. If the attempt to verify the signature is successful, the storage device updates the logical-to-physical address map to map the first logical address to a physical address of the second partition.

Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

Abstract: A method and apparatus for securely sharing content are provided, which can securely share the content without allowing access by unauthorized third parties. The method of securely sharing content includes a first domain, which has content that requires security among a plurality of domains logically generated on a hardware platform, sharing the content with at least one second domain, and if the second domain intends to write the content in a region in which writing is not permitted, preventing the writing of the content.

Abstract: A computing system includes a flash storage device that loads a boot program from a flash storage of the flash storage device to a random access memory of the flash storage device. A processor of the computing system then accesses the boot program from the random access memory and executes the boot program.

Abstract: Mapping management methods and systems are provided. First, a sub-read command comprising mapping directory number, block offset and page offset is obtained. Then, a specific block mapping table is located from a plurality of block mapping tables according to the mapping directory number, and a first specific entry is located from the specific block mapping table according to the block offset, wherein the first specific entry comprises a mapping mode setting and block information. When the mapping mode setting is a page mapping mode, a second specific entry is located from a page mapped block table according to the block information, and a page mapping table is located corresponding to a specific page mapped block. Thereafter, a third specific entry is located from the page mapping table according to the page offset, and a page of data is located from a storage unit according to the third specific entry.

Abstract: The present invention provides a criterion for determining whether or not to apply de-duplication processing. That is, by setting a reduction effect threshold to control switching the de-duplication between ON and OFF, the present invention allows operation such that the de-duplication is applied for a volume for which a high capacity-reduction effect is provided by the de-duplication processing, and in contrast, the de-duplication is not applied to maintain performance for a volume for which a low capacity-reduction effect is provided by the de-duplication processing.

Abstract: A set of logical extents, each having compressed logical tracks of data, is mapped to a head physical extent and, if the head physical extent is determined to have been filled, to at least one overflow extent having spatial proximity to the head physical extent. Pursuant to at least one subsequent write operation and destage operation, the at least one subsequent write operation and destage operation determined to be associated with the head physical extent, the write operation is mapped to one of the head physical extent, the at least one overflow extent, and an additional extent having spatial proximity to the at least one overflow extent.

Abstract: The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one or more subfields for storing index addresses, and use the remaining subfields for respectively storing line addresses. The second field is handled as one subfield, for example, for storing an index address, and the fourth field is divided into two subfields for storing an index address in one and a line address in the other. Such a configuration manages a form of a block of which data is stored in one entry.

Abstract: An image forming apparatus includes a memory that stores therein a control program, a central processing unit that executes the control program stored in the memory, a print engine controlled by the central processing unit, and a unit that is selected from a plurality of units. An identification signal generating unit generates identification data indicating a type of the unit. An exclusive OR unit allocates an exclusive OR data of an address data for the central processing unit to access the memory and the identification data to the memory.

Abstract: This invention provides a storage system to store data used by computers. A storage system coupled to a computer and a management apparatus, includes storage devices accessed by the computer and a control unit that controls the storage devices, in which the control unit performs the following operations: setting, in the storage devices, a first virtual device including a first logical device; setting a second virtual device which including a second logical device, which is a virtual volume accessed by the computer; allocating an address of the first logical device to the second logical device; and changing the allocation to change storage areas of the virtual volume.

Abstract: A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonging to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonging to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system.

Abstract: The present invention provides for a method, system, and computer program product for managing the storage of data. Data is selectively compressed based on a pre-defined compression policy and metadata is stored for physical storage blocks. A stored compression policy identifies at least one criterion for compression, and physical blocks of data meeting the compression policy are identified. A physical block is selected as a source block for data compression, and one or more physical locations are selected as target locations. Data is read from the source block, compressed, and written to the target locations. Metadata is updated to indicate a mapping between the target locations and the virtual blocks previously mapped to the source block. Extra storage capacity can be freed up until more physical storage is ordered and installed, while more important data, such as recently or frequently accessed data, is retained in an uncompressed and accessible state.

Abstract: A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.

Abstract: A method or system for determining storage location of an isolation region based on a data region sizing specified by a host device. In one implementation, the isolation region comprises a set of storage locations required for isolation of or more data region of the storage device.

Abstract: Methods and systems are provided for geometry-based virtual memory management. The methods and systems use Boolean space algebra operations to manage allocation and deallocation of tiled virtual memory pages in a tiled virtual memory provided by a tiled virtual memory subsystem. A region quadtree may be maintained representing a current allocation state of tiled virtual memory pages within a container. The region quadtree may be used to locate a rectangle or two dimensional (2D) array of unallocated tiled virtual memory pages, and physical memory pages may be mapped to tiled virtual memory pages in the rectangle by updating a lookup table used to translate tiled virtual memory page addresses to physical memory page addresses. A union or intersection of region quadtrees may be performed to generate a new region quadtree representing a new current allocation state of the tiled virtual memory pages.

Abstract: Disclosed is a computer implemented method and computer program product to prioritize paging-in pages in a remote paging device. An arrival machine receives checkpoint data from a departure machine. The arrival machine restarts at least one process corresponding to the checkpoint data. The arrival machine determines whether a page associated with the process is pinned. The arrival machine associates the page to the remote paging device, responsive to a determination that the page is pinned. The arrival machine touches the page.

Abstract: Embodiments of switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory are generally described herein. Embodiments of the invention allow one OS to be suspended into S3 or sleep mode, saving its state to memory and turning off its devices. Then, another sleeping OS can be resumed from another location in memory by switching a memory base addressed to a sequestered memory region and restoring its device state. Other embodiments may be described and claimed.

Abstract: A flag parameter in a digital image decoding is calculated. For a macroblock consisting of M×N blocks, a first operation is performed on M block along a first edge to obtain M first parameters, and a second operation is performed on N blocks along a second edge to obtain N second parameters. The first and second parameters are stored into corresponding locations in a first and a second buffer array. Then a flag parameter corresponding to a given block is calculated according to corresponding values stored in the first and second buffer arrays. Calculation for all of the M×N blocks is performed in the order that neighboring left and upper blocks next to the give block is processed prior to the given block.

Abstract: A method has generating an access address information file from an access-destination address list including addresses of access destinations accessed by a program and access types indicating whether write access or read access is made to the individual addresses, generating a configuration-map constraint information file that includes the plurality of address ranges being included in a memory map that includes access attributes indicating whether read access or write access is permitted in the individual memory areas of the target apparatus, a page ID serving as identification information of the certain address range represented by the page and a constraint represented by an access attribute of the page, and inspecting, for each page ID, whether or not the access type for the page ID included in the access address information file contradicts the constraint represented by the access attribute for the page ID included in the configuration-map constraint information file.

Abstract: A system and method enhances performance of updates to sequential block storage of a storage system. According to an aspect of the invention, a disk array of the storage system is utilized to extend write buffers of the system, thereby rendering a portion of the disk array a disk-based log. To that end, one portion of the disk array is organized into a home location array having a set of sequential home locations for disk blocks. Another portion of the disk array is organized into the disk-based log having a set of log buffers configured to store versions of disk blocks that have yet to be returned to their home locations in the home location array. In addition, non-volatile memory of the storage system is organized as an index configured to provide efficient mappings of disk blocks not yet returned to their home locations.

Abstract: Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

Abstract: In an embodiment, an address watch is established on a memory address while the execution of a first thread of a program is halted. In response to a second thread modifying memory contents at the memory address, encountering the address watch and halting, a determination is made whether a first variable in the program that represents the memory address is displayed on a user interface for the first thread. If the first variable in the program that represents the memory address is displayed on the user interface for the first thread, the value of the first variable is read and displayed on the user interface of the first thread.

Abstract: A data writing method for writing updated data from a host into a memory module is provided. Herein, some physical units of the memory module are gotten to be global random physical units for storing data from the host. The method includes determining whether the updated data is sequential data and determining whether a logical page corresponding to the updated data is a start logical page. The method further includes getting a blank physical unit from the physical units as a new global random physical unit and writing the updated data into the new global random physical unit when the updated data is the sequential data and the logical page corresponding to the updated data is the start logical page. Accordingly, the method can write updated data belonging to the same logical unit into the same physical unit, thereby shortening the time for executing write commands.

Abstract: An integrated device includes at least one data processing device and at least one memory macro accessible by the data processing device. The data processing device and the memory macro are laid out so that a memory address and a power consumption have a correlation.