Abstract: There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.

Abstract: A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data set; selecting a first writing direction or a second writing direction to be a preferred writing direction, wherein when the first writing direction is selected to be the preferred writing direction, the first terminal is a starting point corresponding to the first writing direction, and when the second writing direction is selected to be the preferred writing direction, the second terminal is a starting point corresponding to the second writing direction; and writing the data set into the memory block according to the selected writing direction.

Abstract: A method, system, and computer program manager for a computing system memory in the operation of a computing process. At least one memory segment provides memory resources for the computing process. The memory segment includes a plurality of memory objects, each of the memory objects includes an equal number of bytes and has a predetermined order that associates the address of the memory object in the memory segment to the addresses of the remainder of the plurality of memory objects. A pointer identifies a first memory object from the plurality of memory objects. The first memory object occupies a first ordered position according to the predetermined order. The process allocates the first memory objects from the memory segment during the operation of the computing process. The pointer increments to a second memory object having a second ordered position relative to the first memory object.

Abstract: Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.

Abstract: A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a graphics system composed of multiple clients. Pages that are required to be in the frame buffer memory are never swapped out of that memory. The required page list can be dynamically sized or fixed sized. A tag file is used to prevent page swapping of a page from the frame buffer that is required to make forward progress. A forward progress indicator signifies that a page faulting client has made forward progress on behalf of a context. The presence of a forward progress indicator is used to clear the tag file, thus enabling page swapping of the previously tagged pages from the frame buffer memory.

Abstract: A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.

Abstract: A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.

Abstract: Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for uniquely identifying the oldest version, and (b) at least a most recently updated version of the set of data in a second, distinct memory area, the second memory area including at least one second tag for uniquely identifying the most recently updated version. The invention also relates to a computer arrangement including a processor and such a computer-readable medium, as well as to a method of updating sets of data having such tagged-data structures.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the exponential decimation approach by a probabilistic amount. Recursive decimation selects a portion of the queue and removes elements.

Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

Abstract: A digital camera containing patient images is connected to an uploader computer and the patient's name or history is entered into the uploader computer. The uploader computer then connects to the Internet, connects to the secure host server, uploads the images to the host server and shuts down the Internet connection. After the physician selects a medical facility and the system verifies the physician's user I.D. and password, the host server constructs an HTML web page which includes a list of patients whose images were previously uploaded by the medical facility and are available for viewing. The physician simply selects the name of a patient and the host server displays the patient information and images on the physician's computer. The system is password-protected at all levels and the operator for each medical facility determines who may have access to the medical facility images.

Abstract: A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data occurs within sequential transactions. Each transaction is associated with a block of consecutive memory locations and with a starting address. The interface controller includes at least two address buffers, each for storing any of the starting addresses and any address obtained by incrementation thereof.

Abstract: A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The memory cells selected in parallel correspond to least significant bits of an address which has a range that includes the memory cells.

Abstract: A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes, and the comparator compares the external address to a value. Based on the relationship between the external address and the value, the comparator enables or disables the data transfer. For example, such a memory can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address.

Abstract: A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable memory (CAM) receives the hashed output value, and in response, provides an index value and activates a hit signal if the hashed output value matches an entry of the CAM. A random access memory (RAM) receives the index value from the CAM. The RAM stores a collision resolution value and information associated with the character string in an entry associated with the index value. The RAM provides this information and collision resolution value in response to the index value. Logic circuitry indicates a collision if the hit signal is activated and the collision resolution value provided by the hardware hashing circuit does not match the collision resolution value provided by the RAM.

Abstract: A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus, and accessed from exterior of the package and/or within the package, and a controlling integrated circuit which is provided in the memory system in the package, and when an instruction of data transfer within the memory system is received from exterior of the package, controls an execution of the data transfer to be executed within the memory system such that data of memory cells at addresses of a first memory integrated circuit are read out, and the readout data are written into memory cells at addresses of a second memory integrated circuit.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base address. A fractional shifter is also included and is configured to shift the index value up to three bit places, and output a byte offset. An adder is configured to add the byte offset with the base address and output a final address. Further included is a general purpose shifter that is configured to rotate left and right, and shift left and right. A selector is configured to select either the final address or an output signal from the general purpose shifter.

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

Abstract: The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

Abstract: A data access method uses variable mask data and shift amount to write data into or read data from a data storage zone. The mask data and shift amount are determined according to starting and end data bit addresses in a bit range of the data to be read or written. Therefore, the data access method is applicable to various platforms with various byte endians.

Abstract: A system for sharing a computational resource by buffering multiple requests from multiple devices to a memory (e.g. a multi-port RAM or FIFO) in a single clock cycle. The system includes a memory having a first write port and a second write port. A first request input is coupled to the first write port. A second request input is coupled to the second write port. A controller is coupled to the memory. The controller is configured to control the memory to store a first request into the memory via the first write port and a second request into the memory via the second write port. The first and second requests are received via the first and second request inputs and stored into the memory in one clock cycle. Requests are removed from the memory sequentially at a rate that is determined by the shared computational resource.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.

Abstract: A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer for providing a first binary-coded value defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit receiving the first binary-coded value provided by the base pointer and a second binary-coded value defining a shift value. The binary shift circuit combines the first and second binary-coded values to provide a third binary-coded value defining a second address of an element in the collection differing from the first address by the shift value. A shift-value generator fed by the first binary-coded value generates the second binary-coded value depending on the first binary-coded value, so that a generated shift value takes into account shift values corresponding to first binary-coded values preceding a current first binary-coded value in a prescribed first binary-coded value progression order.

Abstract: In a data transmission system for carrying out data transmission/reception between a primary board and secondary boards by using a data transmission path, which employs a same signal line as an address bus and a data bus mutually, there are provided steps of informing a start address required for data access when the data access is executed from the primary board to the secondary boards, and generating an address used in the data access in the secondary boards based on the start address and a predetermined trigger signal.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a matter as to reduce the overall critical timing path (“hiding the ads”); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops.

Abstract: A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.

Abstract: A system for booting a microprocessor controlled system wherein a basic interface between the processor and peripheral devices is copied from an application and file storage device into random access memory without usage of the microprocessor or need for a non-volatile code storage device.

Abstract: In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory bank may be powered up in advance of when it is needed, to reduce or eliminate delays caused by waiting for the memory bank to power up and become operational. The anticipation may be based on accessing a predetermined location in another memory bank.

Abstract: There is provided an electronic device including: a storage medium in which content data is divided into units of clusters and stored; a link information table that records the link structure of the clusters in the storage medium; a cluster table that records, of the series of clusters constituting the content data stored on the storage medium, the cluster number of clusters at predetermined intervals; and playback means for reading and playing the content data in units of clusters. In playing the content data in reverse, if the cluster number of a target cluster to be read is not recorded in the cluster table, the cluster number of the target cluster is obtained by tracing the link information table from a cluster, of the clusters recorded in the cluster table, previous to the target cluster, and the cluster indicated by the cluster number thus obtained is read.

Abstract: A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of the stack at an entry/exit register interior to the stack. The stack has a lower portion below the entry/exit register for maintaining both actual and speculative return addresses, and an upper portion above the entry/exit register for maintaining return addresses that have been speculatively popped out. A branch history register keeps an ongoing record of the most recent calls and returns. In the event of a pipeline flush, such as would be caused by a branch mispredict, the contents of the branch history register are examined to determine how to adjust the contents of the stack. One or more depth counters keep track of which contents in the branch history register are to be examined.

Abstract: An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for providing fast searches and while reducing address table size used in the processing of communication system (e.g., Internet Protocol (IP), layer-3 switches and ATM switches using E.164 addressing) addresses for identifying the source and destination of each digital packet data.

Abstract: A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: A method for generating a unique device ID for each addressable device in a stack of multiple addressable devices by encoding a device ID for one device in the stack and determining a device ID for each of the other devices based on the device ID of an adjacent device in the stack.

Abstract: A method and apparatus for compressing a reference pattern (RP) with repeated substrings by encoding produce compressed reference patterns (CRPs) with reduce storage requirements. Operation codes and a flag are stored with the CRPs. During comparison of reference elements of the CRP to input elements (IEs) of an input pattern (IP), the operation codes are read and the reference pattern is decoded allowing all reference elements including those of the repeated substrings to be compared to IEs in the IP to determine if the RP appears within the IP.

Abstract: Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

Abstract: A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

Abstract: A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.

Abstract: A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the memory subsystem in conformity with measured metrics to reduce the average latency of the memory subsystem. Counters provided within the memory controller track the number of consecutive row accesses and optionally the number of total accesses over a measurement interval. The number of counted consecutive row accesses can be used to control the closing of rows for subsequent accesses, reducing memory latency. The count may be validated using a second counter or storage for improved accuracy and alternatively the row close count may be set via program or logic control in conformity with a count of consecutive row hits in ratio with a total access count.

Abstract: A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Abstract: A circuit for recording digital waveform data includes (a) a first counter which counts the number of data constituting a first data sequence including a plurality of data different from one another, (b) a second counter which counts the number by which the same data is repeated to constitute a second data sequence, (c) a memory which stores all of data constituting the first data sequence and one of data constituting the second data sequence in this order together with the number counted by the first counter and the number counted by the second counter, and (d) a controller which transmits an address signal to said memory, and controls operation of the first and second counters.

Abstract: A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called “NAM” or “NAM Box” or “NAM Server”) appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called “MAN”) is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).

Abstract: A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register.