Accessing, Addressing Or Allocating Within Memory Systems Or Architectures (epo) Patents (Class 711/E12.001)
  • Patent number: 11875055
    Abstract: A storage device includes; a nonvolatile storage including a first region and a second region, a storage controller controlling operation of the nonvolatile storage, and a buffer memory connected to the storage controller. The storage controller stores user data received from a host device in the second region, stores metadata associated with management of the user data and generated by a file system of the host device in the first region, loads the metadata from the first region to the buffer memory in response to address information for an index node (inode) associated with the metadata, and accesses the target data in the second region using the metadata loaded to the buffer memory.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: January 16, 2024
    Inventors: Junghoon Kim, Seonghun Kim, Hongkug Kim, Sojeong Park
  • Patent number: 11868634
    Abstract: Systems and methods for file management by mobile computing devices. An example method, performed by a computer system, may comprise: storing, by a computer system, a first file having a first size, in a memory; storing, in the memory, a second file derived from the first file, the second file having the second size, the second size being less than the first size; determining that the memory is not sufficient to perform a memory write operation; selecting a third file having a fourth file associated with it, the fourth file derived from the third file; and removing the third file from the memory.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: January 9, 2024
    Inventor: Ruslan Shigabutdinov
  • Patent number: 11871141
    Abstract: The image processing apparatus is provided with an image acquiring unit, an image processing unit, and an image outputting unit. The image processing unit includes a memory unit. The memory unit includes: a plurality of memory regions; a first updating unit configured to sequentially perform a first updating process that updates memory contents of the memory regions using the memory image; a second updating unit configured to sequentially perform a second updating process that updates memory contents of the memory regions using a specific image; and a reading unit configured to sequentially perform a reading process that reads an image stored in the memory regions.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 9, 2024
    Assignee: DENSO CORPORATION
    Inventors: Yuki Yamagami, Akira Egashira
  • Patent number: 11868618
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: January 9, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 11868247
    Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: January 9, 2024
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, James G. Wayda
  • Patent number: 11861370
    Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Roberto Izzi, Luca Porzio, Dionisio Minopoli
  • Patent number: 11862292
    Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-LIen Linus Lu
  • Patent number: 11860811
    Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 2, 2024
    Assignee: Arm Limited
    Inventors: Arthur Brian Laughton, Tessil Thomas, Jacob Joseph
  • Patent number: 11853608
    Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: December 26, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Florian Longnos, Feng Yang, Wei Yang
  • Patent number: 11853167
    Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for backup. The method includes: determining a plurality of buffer periods associated with a plurality of pending backup operations of a plurality of objects, each buffer period being a preprocessing period for a corresponding pending backup operation. The method further includes: determining a plurality of predicted execution durations of the plurality of pending backup operations based on historical execution durations of respective historical backup operations of the plurality of objects. The method further includes: determining priorities of the plurality of pending backup operations based on the plurality of predicted execution durations and the plurality of buffer periods. The method further includes: executing the plurality of pending backup operations based on the priorities.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 26, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Jinru Yan, Mengze Liao, Min Liu, Xiaoliang Zhu, Zheyi Zhu
  • Patent number: 11847021
    Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 19, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 11847355
    Abstract: A storage device is disclosed. The storage device may include storage to store data, which may include a first storage of a first type and a second storage of a second type. The storage device may support a number of device streams, some of which associated with the first storage and some associated with the second storage. The storage device may also include a streaming capabilities analyzer that may inventory the streaming capabilities for the storage device. Finally, the storage device may include a transmitter to transmit the streaming capabilities of the storage device to a storage manager.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: December 19, 2023
    Inventors: Jason Martineau, Changho Choi, Rajinikanth Pandurangan, Jingpei Yang
  • Patent number: 11847321
    Abstract: Disclosed herein are systems and method for adjusting storage volume size of an application instance. A method may include: identifying a first application instance running on a computing device, wherein the first application instance has an assigned first storage volume on a device storage of the computing device; collecting, over a period of time, usage data of the device storage; determining, based on the collected usage data, whether a usage capacity of the first storage volume of the first application instance is reaching a maximum capacity of the first storage volume; in response to determining that the usage capacity of the first storage volume is reaching the maximum capacity of the first storage volume, adjusting a size of the first storage volume by a first amount to accommodate usage of the first application instance.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 19, 2023
    Assignee: CLOUD LINUX SOFTWARE, INC.
    Inventors: Arsenii Pastushenko, Igor Seletskiy, Raushan Myrzashova
  • Patent number: 11847344
    Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.
    Type: Grant
    Filed: May 1, 2022
    Date of Patent: December 19, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11842986
    Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and a first integrated circuit (IC) chip disposed on the package substrate. The first IC chip includes first core circuitry, and first interface circuitry for communicating with the first core circuitry. A second IC chip is disposed on the package substrate and includes second core circuitry and second interface circuitry for communicating with the second core circuitry. The second interface circuitry exhibits a non-matching interface with respect to the first interface circuitry. Interface adapter circuitry couples to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: December 12, 2023
    Assignee: Eliyan Corporation
    Inventor: Farjadrad Ramin
  • Patent number: 11836077
    Abstract: Methods, systems, and devices for dynamically tuning host performance booster thresholds are described. A memory system may include a set of memory devices and an interface configured to communicate commands with a host system coupled with the memory system. The interface may communicate commands to the memory system according to a first command mode associated with a logical address space including a plurality of regions and communicate commands according to a second command mode associated with physical memory address. The memory system may further include a controller that may determine a region activated for the second command mode, receive a first plurality of commands, determine, upon deactivating the region, a first threshold based on a first quantity of read commands serviced according to the second command mode. The controller may activate the region for the second command based on a second quantity of read commands received exceeding the first threshold.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Yanhua Bi
  • Patent number: 11836105
    Abstract: A communication device mounted in each of a plurality of information processing devices connected to a fabric, the communication device comprises: a serial interface that transmits and receives a first packet compliant with a Peripheral Component Interconnect Express (PCIe) standard; a requester unit that acquires the first packet from the serial interface and converts the first packet that has been acquired into a second packet that is transmitted and received via the fabric among a plurality of the information processing devices sharing a memory space that is virtually extended by using a device identifier specific to each of the information processing devices; a fabric communication unit that transmits and receives the second packet via the fabric; and a completer unit that acquires the second packet from the fabric communication unit and generating a response packet to a request included in the second packet that has been acquired.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 5, 2023
    Assignee: NEC CORPORATION
    Inventor: Kiyoshi Baba
  • Patent number: 11837257
    Abstract: An electronic device determines a transfer mode to be used to communicate with a recording medium that has first and second transfer modes. The second transfer mode does not guarantee a minimum transfer speed but a higher transfer speed than the minimum transfer speed in the first mode is capable. If the medium supports the second transfer mode, the device determines that the first transfer mode is to be used when the minimum transfer speed is higher than a necessary transfer speed for data that is to be recorded through the communication with the recording medium and that the second transfer mode is to be used when the minimum transfer speed is not higher than the necessary transfer speed. If the medium does not support the second transfer mode, the device determines that the first transfer mode is to be used.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: December 5, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yuzo Matsui, Jun Otsuki
  • Patent number: 11836357
    Abstract: Optimizing copy operations in a storage array, includes combining, in dependence upon a metadata optimization policy, a plurality of copy operations into a single copy operation and splitting the single copy operation into an optimized set of executable copy operations that copy data based on memory alignment.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: December 5, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Christopher Golden, Scott Smith, Luke Paulsen, David Grunwald, Jianting Cao
  • Patent number: 11836360
    Abstract: Methods, systems, and computer program products for generating multi-dimensional host specific storage tiering are provided herein. A computer-implemented method includes maintaining information of a plurality of storage resources connected to at least one host device; configuring, based at least in part on the information, a plurality of partitions of the storage resources, each partition comprising multiple storage tiers, wherein the plurality of partitions is configured to provide physical migration paths between the multiple storage tiers within each of the partitions; detecting a change to the plurality of storage resources; and reconfiguring the plurality of partitions based at least in part on the detected change.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: December 5, 2023
    Assignee: International Business Machines Corporation
    Inventors: Krishnasuri Narayanam, Sarvesh S. Patel, Kushal S. Patel, Amith Singhee
  • Patent number: 11838601
    Abstract: An advertisement display method of displaying an advertisement transmitted from a server in a terminal of a user including receiving, from the server, first video data being a part of video data of the advertisement, controlling to activate the application in response to selection of the application by the user, displaying a first display based on the first video data in a display region of the terminal while the application is active, receiving, from the server, second video data being different from the first video data included in the video data of the advertisement, based on reception of the first video data, and displaying a second display based on the second video data in the display region, in association with the first display in the display region may be provided.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 5, 2023
    Assignee: LINE CORPORATION
    Inventors: Megumi Tomita, Yusuke Konishi
  • Patent number: 11829615
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a hint calibration operation is needed, select a first hint mode out of a plurality of hint modes, generate one or more hints based on a selected hint mode, and select a hint mode based on one or more of a performance, quality of service, and power consumption of the data storage device. The controller is further configured to iterate through the plurality of hint modes during the hint calibration operation and operate based on the selected hint mode until the controller determines that another hint calibration operation is needed.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11829647
    Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kalpit Bordia, Disha Gundecha, Raviraj Raju
  • Patent number: 11829263
    Abstract: The disclosed technology teaches recovering a first virtual machine or an instance with an Internet Protocol address, a first root volume and one or more data volumes that are corrupted. The first virtual machine is hosted by a first cloud server that hosts plurality of virtual machines. The disclosed technology includes instructing the first cloud server to launch a recovery virtual machine. The recovery virtual machine launches one or more new data volumes based upon captured file system images in one or more snapshots taken of corrupted data volumes of the first virtual machine prior to becoming corrupted. The recovery virtual machine detaches the corrupted data volumes and attaches the new data volumes launched to the first virtual machine. The Internet Protocol address of the first virtual machine remains unchanged.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: November 28, 2023
    Assignee: Rubrik, Inc.
    Inventors: Prateek Pandey, Shashank Jain, Vikas Jain
  • Patent number: 11831907
    Abstract: An image coding method includes: deriving a candidate for a motion vector predictor from a co-located motion vector; adding the candidate to a list; selecting the motion vector predictor from the list; and coding a current block and coding a current motion vector, wherein the deriving includes: deriving the candidate by a first derivation scheme in the case of determining that each of a current reference picture and a co-located reference picture is a long-term reference picture; and deriving the candidate by a second derivation scheme in the case of determining that each of the current reference picture and the co-located reference picture is a short-term reference picture.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: November 28, 2023
    Assignee: SUN PATENT TRUST
    Inventors: Viktor Wahadaniah, Chong Soon Lim, Sue Mon Thet Naing, Hai Wei Sun, Toshiyasu Sugio, Takahiro Nishi, Hisao Sasai, Youji Shibahara, Kyoko Tanikawa, Toru Matsunobu, Kengo Terada
  • Patent number: 11829642
    Abstract: Systems and methods are provided for managing write requests for drives in a cloud storage system. For example, a system can receive a plurality of write requests for writing a first set of data to a first drive of a plurality of drives. The first drive may be powered off. The system can write the first set of data to a cache in response to receiving the plurality of write requests. The system can determine that a number of the plurality of write requests exceeds a predetermined write request threshold. The system can power on the first drive in response to determining that the number of the plurality of write requests exceeds the predetermined write request threshold. The system can write the first set of data stored in the cache to the first drive.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: November 28, 2023
    Assignee: RED HAT, INC.
    Inventors: Gabriel Zvi BenHanokh, Yehoshua Salomon, Orit Wasserman
  • Patent number: 11822693
    Abstract: An electronic device is disclosed, including a sensor module configured to recognize boarding and alighting of a passenger from the vehicle, a network interface configured to communicate with a mobile device disposed in the vehicle, a memory, storing a program including one or more instructions, and a processor. The processor implements a method, including: detecting alighting of the passenger using the sensor module, or when a mobile device disconnects from the network interface, determining, by the processor, a deletion level for data related to personal information of a passenger, the deletion level based on a use history information of the passenger, including a latest use time and a use frequency, and deleting the data from the memory according to the determined deletion level.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsik Ki, Sangchul Ku, Youngil Kim, Junhong Kim, Sanghoon Lee, Woong Lee, Junhyun Yim
  • Patent number: 11823088
    Abstract: Systems and methods for fast and efficient retrieval of NFT ownership information are provided. An exemplary method includes initializing a mirror blockchain by making a copy of an NFT blockchain; initializing an ownership transaction table and an NFT ledger from a mirror NFT blockchain by processing the mirror blockchain from a beginning block to an end block; periodically update the mirror blockchain with new blocks from an NFT blockchain thereby forming a new end block; processing ownership transaction events that modify NFT ownership in the new blocks up to a fixed offset from the new end block; updating the ownership transaction table; updating the NFT ledger; receiving a request for all NFTs owned by a crypto-wallet address; generating a response with the NFTs owned by the crypto-wallet address from the NFT ledger; selecting an NFT group; and verifying the NFT ledger against the NFT blockchain ownership.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: November 21, 2023
    Assignee: Alchemy Insights, Inc.
    Inventors: Benjamin Godlove, Ram Bhaskar, Niveda Krishnamoorthy, Bill Zhu, Alex Miao, Omar Ceja, Josh Zhang, Andrew Yang
  • Patent number: 11824722
    Abstract: An example system includes a first network zone of a mobile system comprising a first interconnected plurality of end points; a second network zone of the mobile system comprising a second interconnected plurality of end points; a converged network device (CND) interposed between the first network zone and the second network zone, wherein the CND is configured to regulate communications between end points of the first network zone and the second network zone; a first mobile system controller on the first network zone; a second mobile system controller on the second network zone; and a network redundancy circuit structured to selectively provide a regulation control command; wherein the CND is further configured to adjust the regulating the communications between end points of the first network zone and end points of the second network zone in response to the regulation control command.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: November 21, 2023
    Assignee: Sonatus, Inc.
    Inventors: Yu Fang, Yixiang Chen
  • Patent number: 11822531
    Abstract: Disclosed is an improved approach to represent RDF data in a database system, where one or more auxiliary tables are maintained for the RDF data. The auxiliary tables advantageously permit a database processing system to process a query using fewer numbers of joins or self-joins.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: November 21, 2023
    Assignee: Oracle International Corporation
    Inventors: Souripriya Das, Matthew Steven Perry, Eugene Inseok Chong
  • Patent number: 11816026
    Abstract: A digital signal processing device includes: a delay means that delays audio data in units of sampling periods; and a control means that writes audio data to a first buffer memory one word at a time in sequence at a sampling period, performs control to burst transfer burst length audio data to a DRAM from the first buffer memory, performs control to burst transfer the burst length audio data to a second buffer memory from the DRAM, and outputs audio data to the delay means from the second buffer memory one word at a time in sequence at the sampling period, in which a delay time of audio data output by the delay means is determined by a combination of a delay time of multiple sampling period units depending on a burst length of the DRAM and a delay time of a sampling period unit of the delay means.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: November 14, 2023
    Assignee: KABUSHIKI KAISHA KAWAI GAKKI SEISAKUSHO
    Inventors: Seiji Okamoto, Tetsuya Hirano
  • Patent number: 11816334
    Abstract: The invention discloses a solid-state drive control device and a learning-based solid-state drive data access method, wherein the method comprises the steps of: presetting a hash table, the hash table comprising more than one hash value, the hash value is used to record and represent data characteristics of data pages in the solid-state drive. Obtaining an I/O data stream of the solid-state drive, and obtaining a hash value corresponding to the I/O data stream in the hash table. Predicting a sequence of data pages and/or data pages that are about to be accessed by a preset first learning model. Prefetching data is performed in the solid-state drive based on an output result of the first learning model. Through the embodiment of the present invention, when predicting prefetched data, learning can be performed in real time to adapt to different application categories and access modes through adaptive adjustment parameters, so that better data prefetching performance can be obtained.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 14, 2023
    Assignee: SHENZHEN DAPU MICROELECTRONICS CO., LTD
    Inventor: Jing Yang
  • Patent number: 11809750
    Abstract: In one example, a system includes a flash memory, a Random-Access Memory (RAM), and a controller. The flash memory stores first and second initial overlays, where the first initial overlay includes a first overlay function and the second initial overlay includes a second overlay function. The controller copies the first initial overlay into the RAM based on the first overlay function being called, swaps the first initial overlay with the second initial overlay based on the second overlay function being called, and monitors functions calls between the first and second overlay functions over a monitoring period. The controller determines whether a number of the function calls is greater than a threshold value, and based at least in part on the number of function calls being greater than the threshold value, re-groups the first and second overlay functions into a new overlay, and stores the new overlay in the flash memory.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Venkatesh Naidu Pamoti, Sabith B N, Disha Parwani
  • Patent number: 11809714
    Abstract: An input/output (I/O) write request directed at a plurality of memory devices having memory cells is received by a processing device. The write request includes a set of data. The processing device appends the set of data to a compound data object. The compound data object comprises one or more sequentially written data objects. The processing device associates the compound data object with one or more groups of memory cells of the plurality of memory devices. The processing device causes the compound data object to be written to the one or more groups of memory cells of the plurality of memory devices.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11809377
    Abstract: A write request is transmitted from a client to a metadata server (“MDS”), wherein the write request comprises an object identifier associated with a data object. An object store location is received for an object store from the MDS. A metadata request is transmitted to the object store using the object store location, wherein the metadata request includes the object identifier. A metadata response is received from the object store. Determine the metadata response contains an object designator. A count associated with a mapping between the object identifier and the object designator is incremented, wherein the mapping resides on an object version manager shared with a second MDS.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 7, 2023
    Assignee: EMC IP Holding Company LLC
    Inventor: Rajiv Desai
  • Patent number: 11809316
    Abstract: An apparatus has processing circuitry (18), and memory access circuitry (35) to control access to a memory system based on memory attribute data identifying each memory region as one of a plurality of region types. A speculation-restricted region type is supported, for which: at least when a first read request is non-speculatively issued to a region of the speculation-restricted type, a subsequent read request is permitted to be serviced using data obtained in response to the first read request; and for a speculatively issued read request to the region of the speculation-restricted type, at least when caching the read data would require allocation of a new entry in the cache, at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, may be prohibited from being performed before the first read request has been resolved as correct.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 7, 2023
    Assignee: Arm Limited
    Inventor: Richard William Earnshaw
  • Patent number: 11803320
    Abstract: A controller of a memory system according to an embodiment manages, for each of a plurality of blocks, first information indicating whether a corresponding block is in use which indicates a state where the data is stored, second information indicating the number of erasures, and third information indicating a waiting time until next erasure. The controller executes first sequential write received from a host, and determines whether to execute processing of leveling the number of erasures for each of the plurality of blocks based on a first difference, a second difference, and a third difference when executing second sequential write received from the host.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 31, 2023
    Assignee: Kioxia Corporation
    Inventor: Tetsuya Yasuda
  • Patent number: 11797406
    Abstract: One or more techniques and/or computing devices are provided for moving a consistency group having a replication relation. For example, a first consistency group of storage objects (e.g., files, logical unit numbers (LUNs), etc.) within first storage may have a replication relationship with a second consistency group within second storage (e.g., the second consistency group is maintained as a synchronously replicated copy of the first consistency group). A volume copy operation, a single file move on demand command, a single file restore command, or other functionality is used to move the first consistency group from the first storage to third storage, such as for load balancing, to create a moved first consistency group within the third storage. A new replication relationship is established between the moved first consistency group and the second consistency group, and the moved first consistency group and the second consistency group are resynchronized.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: October 24, 2023
    Assignee: NetApp, Inc.
    Inventors: Pranab Patnaik, Nagender Somavarapu, Yuedong Mu, Rithin Kumar Shetty, Devang Kundanlal Shah
  • Patent number: 11797498
    Abstract: Systems and methods are provided for migrating a tenant of a database system from a source database instance to a destination database instance. The systems and methods include quiescing the tenant data of the tenant to be migrated from the source database instance to the destination database instance so that no new data is written to the storage of the database system associated with the tenant identifier at the source database instance, transmitting metadata of the tenant to be migrated from the source database instance to the destination database instance, and modifying, at the destination database instance, the metadata of the tenant so that the destination database instance has information to point to groupings of data in the storage for the destination database to access the tenant data.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: October 24, 2023
    Assignee: Salesforce, Inc.
    Inventors: Jameison Bear Martin, Nathaniel Wyatt, Gary J. Baker, Thomas Fanghaenel, Terry Chong
  • Patent number: 11797167
    Abstract: A computing device and method for providing a user interface for summarizing and presenting information regarding dynamic provisioning and deployment of media processing resources, in a manner that is easy and intuitive and analogizes well to conventional physical media processing deployment. Users are not required to understand hypervisor configuration or virtual machine deployment, or switch through various layers and screens to find configuration information or controls, a process that may be particularly slow, complex, and difficult to learn, particularly for media and broadcast engineers unfamiliar with virtualization technologies. Instead, the present user interface improves efficiency of use of the computing environment for media processing, by providing deployment information in a format similar to physical processing deployment.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 24, 2023
    Assignee: GRASS VALLEY CANADA
    Inventor: Ian David Fletcher
  • Patent number: 11797434
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing storage devices. In some implementations, a memory controller receives a logical write request over a logical interface that the memory controller provides for accessing a non-volatile storage device. The logical write request indicates a logical address at which to write data to the non-volatile storage device. In response to receiving the logical write request, the memory controller sends a write request event to a host system. The memory controller receives a physical write command from the host system over a physical interface that the memory controller provides for accessing the non-volatile storage device. In response to receiving the physical write command, the memory controller stores the data in the non-volatile storage device according to the physical write command.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: October 24, 2023
    Assignee: Google LLC
    Inventors: Christopher J. Sabol, Tomasz Jeznach
  • Patent number: 11797214
    Abstract: A method for deleting one or more snapshots using micro-batch processing is provided. The method includes receiving a request to delete the one or more snapshots, identifying one or more middle map extents exclusively owned by the one or more snapshots requested to be deleted, wherein metadata for the one or more snapshots is stored in one or more logical maps having logical map extents mapping logical block addresses (LBAs) to middle block addresses (MBAs) and a middle map having middle map extents mapping MBAs to physical block addresses (PBAs) of physical locations where data blocks are written, adding MBAs of the identified one or more middle map extents in a batch, determining a first micro-batch including a first subset of the MBAs in the batch, the first subset of MBAs being MBAs less than a first upper bound MBA, and using a first transaction to delete the middle map extents corresponding to the first subset of MBAs included in the first micro-batch.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 24, 2023
    Assignee: VMware, Inc.
    Inventors: Pranay Singh, Enning Xiang, Wenguang Wang, Fan Ni
  • Patent number: 11798605
    Abstract: According to one embodiment, there is provided a memory system including a controller, a plurality of memory chips, and a channel. The controller outputs a clock signal, a timing control signal and a data signal. Each of the plurality of memory chips includes at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal and a data output terminal. The channel includes a loop bus which connects the controller and the plurality of memory chips in a ring shape. The controller is able to control operation timings of the memory chips by transmitting the clock signal and the timing control signal to the plurality of memory chips via the channel.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: October 24, 2023
    Assignee: Kioxia Corporation
    Inventor: Kenji Sakaue
  • Patent number: 11789968
    Abstract: Methods and systems for accessing, maintaining, analyzing, and visualizing structured data are presented. The system receives from a requesting computing device, a first request for a first hierarchical record. The system searches a first repository having first structured data. The system determines whether the first hierarchical record is present in the first structured data and creates, based on the first hierarchical record, a snapshot query criterion. The system then searches, based on the snapshot query criterion, a second repository comprising a first snapshot of the first structured data. The system determines whether a second hierarchical record at least partially matches the first hierarchical record.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: October 17, 2023
    Assignee: Veeva Systems Inc.
    Inventors: Piotr Kuchnio, Marius K. Mortensen, Asaf Roll, Zhen Tan
  • Patent number: 11789766
    Abstract: Disclosed herein are systems and method for selectively restoring a computer system to an operational state. In an exemplary aspect, the method may include creating a backup image of the computer system comprising a set of data blocks, detecting that the computer system has begun an initial startup, identifying a subset of the data blocks read from a disk of the computer system during the initial startup. In response to determining that the computer system should be restored, the method may include restoring the subset of the data blocks such that the computer system is operational during startup, and restoring a remaining set of the data blocks from the backup image after the startup of the computer system.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: October 17, 2023
    Assignee: Acronis International GmbH
    Inventors: Alexey Sergeev, Anton Enakiev, Vladimir Strogov, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11789615
    Abstract: A nonvolatile memory scheduling method, system and device, and a computer-readable storage medium. The method includes: obtaining a utilization rate of a current memory space (S101); when the utilization rate is less than a first threshold, determining a first space to be converted of the memory space, converting the first space into a high-speed storage space, and storing data in a conventional storage device into the high-speed storage space (S102); and when the utilization rate is greater than a second threshold, determining a second space to be converted of the high-speed storage space, storing data stored in the second space into the conventional storage device, and converting the second space into the memory space (S103).
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 17, 2023
    Assignee: INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.
    Inventors: Zhen Feng, Dong Zhang, Bingheng Yan
  • Patent number: 11789907
    Abstract: A quantum file attribute service is disclosed. A quantum computing system receives a file metadata command requesting quantum file metadata. It is determined that a quantum file is encompassed by the file metadata command, the quantum file comprising a qubit. Quantum file metadata that identifies information about the quantum file is accessed. The quantum file metadata includes a qubit identifier that identifies the qubit. The quantum file metadata is sent to a destination.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 17, 2023
    Assignee: Red Hat, Inc.
    Inventors: Stephen Coady, Leigh Griffin
  • Patent number: 11790992
    Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 17, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-yuan Tseng
  • Patent number: 11790967
    Abstract: A magnetic domain wall displacement element includes a first ferromagnetic layer, a second ferromagnetic layer extending in a second direction and magnetically recordable, a nonmagnetic layer, and a first conductive part having a first intermediate layer and a second conductive part having a second intermediate layer, in which the first intermediate layer is sandwiched between first and second magnetization regions and exhibiting first and second magnetization directions, the second intermediate layer is sandwiched between a third magnetization region and exhibiting the second magnetization direction and a fourth magnetization region exhibiting the first magnetization direction in the first direction, and an area of the first magnetization region is larger than an area of the second magnetization region and an area of the third magnetization region is smaller than an area of the fourth magnetization region in a cross section in the first direction and the second direction.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 17, 2023
    Assignee: TDK CORPORATION
    Inventors: Shogo Yamada, Tatsuo Shibata, Yugo Ishitani
  • Patent number: 11783185
    Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Joshua Phelps, Peter B. Harrington