Accessing, Addressing Or Allocating Within Memory Systems Or Architectures (epo) Patents (Class 711/E12.001)
  • Patent number: 11573860
    Abstract: A method for verifying a consistency of snapshot metadata maintained in an ordered data structure for a plurality of snapshots in a snapshot hierarchy is provided. The method includes identifying a first plurality of nodes maintained in a first ordered data structure for a first snapshot that is a child of a second snapshot; for a first node of the first plurality of nodes, verifying the first node by checking for the first node in a second node map maintained in memory for the second snapshot, wherein the second node map includes a plurality of verified nodes in a second ordered data structure; and based on whether the first node is in the second node map: adding the first node to a first node map maintained in memory for the first snapshot, wherein the first node map includes verified nodes of the first plurality of nodes; or triggering an alarm.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: February 7, 2023
    Assignee: VMware, Inc.
    Inventors: Enning Xiang, Wenguang Wang, Mrityunjay Kumar
  • Patent number: 11573742
    Abstract: A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11573897
    Abstract: A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 7, 2023
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 11567672
    Abstract: A rollback can be performed after completing an upgrade to components of a virtualized computing environment. When the upgrade is performed, an upgrade bundle having rollback scripts is provided to edges, hosts, and managers in the virtualized computing environment that are to be upgraded. When a rollback is to be performed, the rollback scripts are executed, and the components are rolled back in a reverse order relative to their upgrade order. Data and configuration checking are performed to validate the results of the rollback.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: January 31, 2023
    Assignee: VMWARE, INC.
    Inventors: Prashant Shelke, Dipesh Bhatewara, Suraj Gole, Neha Pratik Dhakate
  • Patent number: 11568947
    Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines. The memory device also includes a peripheral circuit configured to perform a plurality of program loops to program memory cells, among the plurality of memory cells, connected to a selected word line among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit to set a step voltage based on the number of turned off memory cells among the selected memory cells and then apply a program voltage, to which the step voltage is added, to the selected word line in a next program loop, during a verify operation of a program operation and the verify operation included in each of the plurality of program loops.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Jae Woong Kim
  • Patent number: 11567673
    Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Radu Ioan Stoica, Nikolas Ioannou, Roman Alexander Pletka, Nikolaos Papandreou, Charalampos Pozidis
  • Patent number: 11567860
    Abstract: A memory system includes a storage medium and a controller. The storage medium includes a plurality of memory regions. The controller stores data corresponding to a write request into a memory region of a random attribute or a memory region of a sequential attribute among the memory regions and to update logical-to-physical (L2P) information corresponding to the stored data, and updates, when storing the data into the memory region of the random attribute, physical-to-logical (P2L) information corresponding to the stored data within a P2L table of the memory region of the random attribute.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Hye Mi Kang
  • Patent number: 11561723
    Abstract: A storage system performing an overwrite, a host system controlling the storage system, and an operating method of the storage system, wherein the storage system includes a memory device; and a controller that receives new data and an overwrite request from the host system, wherein the overwrite request includes a first logical address for old data and a second logical address for the new data, and performs an overwrite operation by writing the new data corresponding to the second logical address to the memory device and invalidating the old data corresponding to the first logical address according to the overwrite request.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jekyeom Jeon, Jooyoung Hwang, Jeonguk Kang, Junhee Kim, Sunghyun Noh, Keunsan Park, Byungki Lee
  • Patent number: 11561893
    Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: January 24, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Liam Michael Parker
  • Patent number: 11562071
    Abstract: Techniques for detecting malware via scanning for dynamically generated function pointers in memory are disclosed. In some embodiments, a system/process/computer program product for detecting malware via scanning for dynamically generated function pointers in memory includes detecting a dynamically generated function pointer in memory based on an analysis of monitored changes in memory during execution of a malware sample in a computing environment; and generating a signature based on detection of the dynamically generated function pointer in memory, wherein the malware sample was determined to be malicious.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: January 24, 2023
    Assignee: Palo Alto Networks, Inc.
    Inventor: Robert Jung
  • Patent number: 11561717
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data, and the updated delta data is copied to the RAM2. The delta data stored in the RAM2 is copied to the storage unit periodically. The controller tracks which delta data has been copied to the RAM2 and to the storage unit. During a power failure, the delta data and the change log data are copied from the RAM1 or the RAM2 to the storage unit.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 24, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Peter Grayson
  • Patent number: 11557367
    Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Alan J. Wilson
  • Patent number: 11557332
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Patent number: 11556475
    Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
  • Patent number: 11556467
    Abstract: A method is described that includes determining, by a memory subsystem, that a garbage collection process is to be performed on a memory device and selecting a first candidate block stripe for folding into a first target block stripe in response to determining that the garbage collection process is to be performed. The method further includes determining, by the memory subsystem, that a physical-to-logical table stored in the first candidate block stripe is unavailable; reducing a write command rate, which controls a rate at which writes are fulfilled by the memory subsystem, in response to determining that the physical-to-logical table stored in the first candidate block stripe is unavailable; and performing folding of the first candidate block stripe into the first target block stripe using a logical-to-physical table.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 17, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Meng Wei
  • Patent number: 11550508
    Abstract: A semiconductor storage device includes a non-volatile first memory, a second memory that includes a first area for recording data to be recorded in the first memory and a second area for recording data read from the first memory, and a memory controller that controls the first memory.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 10, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Yohei Kato
  • Patent number: 11550816
    Abstract: Systems and methods are provided to manage a replication service of a block storage volume to increase dependability and/or decrease data loss. Each snapshot of a block storage volume can include a point-in-time representation of the volume. Each snapshot may include multiple objects that correspond to one or more blocks of the volume. One or more objects of a snapshot may reference a parent snapshot instead of a block of the volume. Each object of a snapshot may be replicated a number of times based on the number of references by other snapshots. The number of replicas may be based on the number of snapshots referencing the object or the number of unique clients referencing the object. The replication service can manage the replicas of the object and increase or decrease the number of replicas as needed.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: January 10, 2023
    Assignee: Amazon Technologies, Inc.
    Inventor: Shengjie Quan
  • Patent number: 11550617
    Abstract: A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Arun Raghunath, Yi Zou, Tushar Sudhakar Gohad, Anjaneya R. Chagam Reddy, Sujoy Sen
  • Patent number: 11544003
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventor: Jung Ae Kim
  • Patent number: 11537753
    Abstract: A method is disclosed for dynamic control, at file level, of an integrity of a set of files stored in a persistent memory of a computer. The method includes mounting an overlay file system of the Overlayfs type, with a “lower” directory containing the files which is marked as read-only, and with an “upper” directory containing any file resulting from a modification of the files of the “lower” directory by virtue of a copy-on-write mechanism. A denylist of files from the “lower” directory to be excluded from the integrity control is created and maintained. An integrity violation of a file is detected if a copy of said file is identified in the “upper” directory. The method also includes containerization, which natively implements file mounting by overlays of the Overlayfs type.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: December 27, 2022
    Assignee: BULL SAS
    Inventors: Luc Creti, Dominique Tronche, Jean-Michel Lenott
  • Patent number: 11532358
    Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store precondition data. The precondition data can identify a portion of the memory array, specify a predetermined precondition state, or a combination thereof. When the memory device powers on, the memory device can be configured to automatically retrieve the precondition data from the fuse array and/or to write memory cells in the portion of the memory array to the predetermined precondition state before executing an access command.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Anthony D. Veches, Debra M. Bell, James S. Rehmeyer, Robert Bunnell, Nathaniel J. Meier
  • Patent number: 11528705
    Abstract: The embodiments of the invention provide a signal transmission method and apparatus. The method comprises: a first apparatus determines a bandwidth and a quantity of subcarriers of a target channel, wherein the bandwidth and the quantity of the subcarriers of the target channel are determined according to a level and/or a type of terminal equipment using the target channel; and the first apparatus transmits, according to the bandwidth and the quantity of the subcarriers of the target channel, via the target channel, and to a second apparatus, a signal, or receives a signal sent from the terminal device via the target channel, wherein at least one of the first apparatus and the second apparatus is the terminal equipment. The embodiment of the invention can prevent resource wastage.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 13, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Hai Tang
  • Patent number: 11526441
    Abstract: In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory module includes volatile memory, non-volatile memory, and an internal cache. The internal cache is communicably coupled with the volatile memory and the non-volatile memory. Whether to execute a memory access request is determined by operation of the memory module. In response to the inability of the memory access request to be executed, a data transferring process is performed to copy data between the volatile memory and the non-volatile memory via the internal cache.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: December 13, 2022
    Assignee: Truememory Technology, LLC
    Inventor: Igor Sharovar
  • Patent number: 11520507
    Abstract: A system and associated method for generating a test precondition. The system includes a test device and a storage device including user data blocks and system blocks. The test device reads, from the system blocks, an initial system data snapshot stored and represents a factory format; erases the system blocks and the user data blocks; writes data to selected user data blocks; generates system tables associated with the erasing and writing of the selected user data blocks; replaces the initial system data snapshot with the system tables; writes the replaced system tables to the system blocks; and performs one or more tests on the storage device.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: December 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Yahor Zaitsau
  • Patent number: 11520514
    Abstract: A command is transmitted to a storage device to relocate first data that partially fills a first erase block of the storage device and second data that partially fills a second erase block of the storage device to a third erase block of the storage device, wherein the command causes the relocation of the first data and the second data while bypassing sending the data to the storage controller. An acknowledgement that the first data and the second data have been stored at the third erase block is received from the storage device.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: December 6, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Zoltan DeWitt, Gordon James Coleman, Benjamin Scholbrock, Rongjin Qiao
  • Patent number: 11522565
    Abstract: A packed error correction code (ECC) technique opportunistically embeds ECC check-bits with compressed data. When compressed, the data is encoded in fewer bits and is therefore fragmented when stored or transmitted compared with the uncompressed data. The ECC check-bits may be packed with compressed data at “source” points. The check-bits are transmitted along with the compressed data and, at any “intermediate” point between the source and a “destination” the check-bits may be used to detect and correct errors in the compressed data. In contrast with conventional systems, packed ECC enables end-to-end coverage for sufficiently-compressed data within the processor and also externally. While storage circuitry typically is protected by structure-specific ECC, protection is also beneficial for data as it is transmitted between processing and/or storage units.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: December 6, 2022
    Assignee: NVIDIA Corporation
    Inventors: Michael Brendan Sullivan, Jeffrey Michael Pool, Yangxiang Huang, Timothy Kohchih Tsai, Siva Kumar Sastry Hari, Steven William Keckler
  • Patent number: 11520640
    Abstract: The present disclosure provides a method for syncing data of a computing task across a plurality of groups of computing nodes, each group comprising a set of computing nodes A-D, a set of intra-group interconnects that communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C, and a set of inter-group interconnects that communicatively couple a computing node A of a first group of the plurality of groups with a computing node A of a second group neighboring the first group, a computing node B of the first group with a computing node B of the second group, a computing node C of the first group with the computing node C of the second group, and a computing node D of the first group with a computing node D of the second group, the method comprising: syncing across a first dimension of computing nodes using a first set of ring connections, wherein the first set of ring connections are formed using inter-group and intra-group interconnects that communica
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 6, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Liang Han, Yang Jiao
  • Patent number: 11520508
    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 6, 2022
    Assignee: Rambus Inc.
    Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
  • Patent number: 11520665
    Abstract: An intelligent method of handling incremental backups concurrent with load balancing movement. The file system uses placement tags, incremental backup requests and capacity balancing data movement to make intelligent decision to avoid affecting any backup windows for clients or backup apps. The file system tracks capacity balancing file movements inside the cluster. When switching locations of files in a cluster from one node to another, it is performed as an atomic change of switching inode attributes by the file system after the contents of the file have been copied over to the new node. During the file movement for capacity balancing, the file system handles requests for full backups differently than requests for incremental backups. The file system continues to handle virtual systhesis and fastcopy requests on the node that hosts the previous backup to ensure that the incremental backup succeeds with the expected smaller backup window from the client.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 6, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: George Mathew, Xiaohong Wang, Abhishek Rajimwale
  • Patent number: 11513910
    Abstract: Embodiments of a compliance service that will enable users be compliant with all regulatory, industry processes and business needs at all times. The service is available to storage and data protection systems through a set of APIs that will enable such compliance be achieved and maintained with no user intervention and without labor-intensive manual work. The service will also allow storing the configuration of the data protection policies and create alerts when compliance changes. A data backup platform may include a data protection system that integrates with such a service and provides full regulatory/industry compliance.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Yossef Saad
  • Patent number: 11513686
    Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 29, 2022
    Assignee: NVIDIA Corporation
    Inventors: Ram Rangan, Suryakant Patidar, Praveen Krishnamurthy, Wishwesh Anil Gandhi
  • Patent number: 11513493
    Abstract: The present application relates to a data processing method for a numerical control system, a computer device and a storage medium. The method comprises: receiving a data request, the data request carrying a target data identifier; parsing the data request to obtain an interactive type corresponding to the target data identifier; when the interactive type corresponding to the target data identifier is a type corresponding to real-time data, searching for data corresponding to the target data identifier in a shared memory of the numerical control system; transferring the data corresponding to the target data identifier from the shared memory to a data cache of the numerical control system and outputting the data.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 29, 2022
    Assignees: HAN'S LASER TECHNOLOGY INDUSTRY GROUP CO., LTD., SHENZHEN HAN'S SMART CONTROL TECHNOLOGY CO., LTD.
    Inventors: Yuxin Feng, Yan Chen, Yunfeng Gao
  • Patent number: 11507326
    Abstract: A storage device is disclosed. The storage device may include storage to store data, which may include a first storage of a first type and a second storage of a second type. The storage device may support a number of device streams, some of which associated with the first storage and some associated with the second storage. The storage device may also include a streaming capabilities analyzer that may inventory the streaming capabilities for the storage device. Finally, the storage device may include a transmitter to transmit the streaming capabilities of the storage device to a storage manager.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 22, 2022
    Inventors: Jason Martineau, Changho Choi, Rajinikanth Pandurangan, Jingpei Yang
  • Patent number: 11507556
    Abstract: An example computer-implemented method and computer system, each adapted for encapsulating digital data records in multiple, differently structured and unstructured formats, the data records ingested from multiple data storage locations, is described herein. In the method, each ingested data record is separated into a plurality of tuple structures, and for each tuple, the tuple is split into a data part and fieldname part. A pointer is created by combining the fieldname part, a record identifier of the data record, and a database identifier of the storage location where the data record was stored. The pointer is appended to the data part to form a digital stem cell (DSC) that is stored in a single data store, each formed DSC having the same structure.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 22, 2022
    Assignee: ENCAPSA TECHNOLOGY LLC
    Inventor: Christopher B. A. Coker
  • Patent number: 11500668
    Abstract: Systems and methods for supporting page faults for virtual machine network accelerators. In one implementation, a processing device may receive, at a network accelerator device of a computer system, a first incoming packet from a network. The processing device may select a first buffer from a plurality of buffers associated with the network device, and may attempt to store the first incoming packet at the first buffer. Responsive to receiving a notification that the attempt to store the first incoming packet at the first buffer caused a page fault, the processing device may store the first incoming packet at a second buffer. The processing device may receive a second incoming packet, and store the second incoming packet at the first buffer. The processing device may forward, to a driver of the network accelerator device, a first identifiers of the second buffer and a second identifier of the first buffer.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 15, 2022
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11500772
    Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11496525
    Abstract: A network element of an Internet Protocol multimedia subsystem buffers network resource usage information in the cloud. After generating network resource usage information based on an observation of network resource usage, the network element transmits the network resource usage information to a cloud-based storage service for buffering. Once a network resource usage collection function is available, the network element retrieves the network resource usage information from the cloud-based storage service and transmits it to a charging collection function for generation of call detail records.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 8, 2022
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: James Oliver
  • Patent number: 11494077
    Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yasushi Nagadomi
  • Patent number: 11494091
    Abstract: An apparatus comprises a processing device configured to control delivery of input-output operations from a host device to a storage system over selected ones of a plurality of paths through a network. The processing device is further configured to receive first and second data outputs corresponding to a plurality of groups of the storage system, to compute first and second pluralities of checksums for respective ones of the groups based on the first and second data outputs, and to determine for the respective ones of the groups whether given ones of the second plurality of checksums differ from given ones of the first plurality of checksums. The control of delivery of the input-output operations is based at least in part on the determination. The plurality of groups each correspond to a plurality of storage devices and the second data output is received after the first data output.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: November 8, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Rimpesh Patel, Amit Pundalik Anchi
  • Patent number: 11496809
    Abstract: In some embodiments, a method receives a first set of video files at a node that delivers video files to client devices and receives a second set of video files. The second set of video files are predicted to be delivered by the node to a client device during a time period. The node receives a request for a video file from a client device and determines whether the video file is stored in the first set of video files and the second set of video files. When the video file is stored at the node, the node sends the video file from the first set of video files and the second set of video files. When the video file is not stored in the first set of video files and the second set of video files, the node sends a request for the video file to another node.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 8, 2022
    Assignee: HULU, LLC
    Inventors: Xiaocheng Li, Wei Feng, Wenhao Zhang, Jiarui Yang
  • Patent number: 11487476
    Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to receive a first command set, receive a second command set related to a read operation while rejecting a command set related to a write operation or erase operation in response to the first command set, and execute the read operation on the memory cell array in response to the second command set.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yoshikazu Harada
  • Patent number: 11487624
    Abstract: When multiple backup database instances most recently experienced an update is determined. If a most recently updated backup database instance was updated within a defined time period of one or more other backup database instances, a source instance for cloning is selected as the backup database instance that satisfies at least one of a physical or logical proximity criteria relative to a designated database instance. If a difference in update times is greater than the defined time period, e.g., for the two most recent backup database instances, the source instance for cloning is selected to be the most recently updated backup database instance. Cloning to a target instance is performed using the selected backup database instance as a source instance as long as preparatory operations all pass. If not, the source databases are used for the cloning while still being accessible to clients.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 1, 2022
    Assignee: ServiceNow, Inc.
    Inventors: Paul Wang, Xiaoyi Ye, Xuejia Lu, Sridhar Chandrashekar
  • Patent number: 11487730
    Abstract: Embodiments for storage resource utilization analytics using metadata tags by a processor. Storage capacity utilization in the plurality of heterogeneous storage systems may be determined using one or more events indexed into a centralized search index.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deepavali Bhagwat, Nilesh Bhosale, Joseph Dain, James Hewitt, Frank N. Lee, Wayne Sawdon
  • Patent number: 11487701
    Abstract: A request for one or more files is received. It is determined that the requested one or more files have been archived at an archival storage tier. Access to a first portion of the one or more requested files stored at the archival storage tier is requested. Access is provided to the first portion in response to the request. Based at least in part on a metric associated with a utilization of the first portion, it is determined when to request access to a second portion of the one or more requested files stored at the archival storage tier.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 1, 2022
    Assignee: Cohesity, Inc.
    Inventors: Sarthak Agarwal, Anirudh Kumar
  • Patent number: 11487449
    Abstract: A storage system and method for improving utilization of a communication channel between a host and the storage system are provided. In one embodiment, a host sends a request for workload pattern information to the data storage device, and the data storage device provides the requested workload pattern information to the host. Based on that workload pattern information, the host queues commands to be sent to the data storage device to improve utilization of the communication channel between the host and the data storage device. Other embodiments are provided.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avinash Sharma, Abhijit K Rao, Bala Siva Kumar Narala
  • Patent number: 11481157
    Abstract: According to one embodiment, an electronic apparatus includes an interface circuit connectable to a first signal line, a second signal line, and a third signal line, and a controller. Before transmitting data using the first signal line, the controller is configured to transmit a first command using the first signal line while transmitting a first control signal using the second signal line, and transmit a first address using the first signal line while transmitting a second control signal using the third signal line. While transmitting the data using the first signal line, the controller is configured to transmit at least one of a second command and a second address using the second signal line and the third signal line.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 25, 2022
    Assignee: Kioxia Corporation
    Inventor: Tomoaki Suzuki
  • Patent number: 11481118
    Abstract: The present disclosure describes apparatuses and methods for storage media programming with adaptive write buffer release. In some aspects, a media write manager of a storage media system stores, to a write buffer, data received from a host interface. The media write manager determines parity information for the data stored to the write buffer and then releases the write buffer on completion of determining the parity information for the data. The media write manager may then write at least a portion of the data to storage media after the write buffer is released. By releasing the write buffer of the storage media system after determining the parity information, the write buffer is freed more quickly, which may result in improved write buffer utilization and increased write throughput of the storage media system.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 25, 2022
    Assignee: Marvell Asia PTE, Ltd.
    Inventors: Steven A. Klein, Viet-Dzung Nguyen, Gregory Burd
  • Patent number: 11481214
    Abstract: A processor for sparse matrix calculation can include an on-chip memory, a cache, a gather/scatter engine and a core. The on-chip memory can be configured to store a first matrix or vector, and the cache can be configured to store a compressed sparse second matrix data structure. The compressed sparse second matrix data structure can include: a value array including non-zero element values of the sparse second matrix, where each entry includes a given number of element values; and a column index array where each entry includes the given number of offsets matching the value array. The gather/scatter engine can be configured to gather element values of the first matrix or vector using the column index array of the sparse second matrix. In a horizontal implementation, the gather/scatter engine can be configured to gather sets of element values from different sub-banks within a same row based on the column index array of the sparse matrix.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 25, 2022
    Inventor: Fei Sun
  • Patent number: 11475284
    Abstract: An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 18, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Koichi Shirahata, Takashi Arakawa, Katsuhiro Yoda, Makiko Ito, Yasumoto Tomita
  • Patent number: 11474899
    Abstract: An open-channel storage device being configured to be controlled by a host including a bad block manager, the open-channel storage device including a buffer memory and a nonvolatile memory device. An operation method of the open-channel storage device includes performing a normal operation under control of the host, detecting a sudden power-off immediately after a program failure associated with a first data block among a plurality of memory blocks included in the nonvolatile memory device while the normal operation is performed, dumping a plurality of user data stored in the buffer memory to a dump block among the plurality of memory blocks in response to the detected sudden power-off, detecting a power-on, and performing a data recovery operation on the plurality of user data stored in the dump block in response to the detected power-on.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul Kim, Jongwon Lee, Kyungwook Ye, Minseok Ko, Yangwoo Roh, Sung-Hyun Cho