In Block-erasable Memory, E.g., Flash Memory, Etc. (epo) Patents (Class 711/E12.008)
  • Publication number: 20140289447
    Abstract: An apparatus, system, and method are disclosed for storage space recovery. A storage division selection module selects a first storage division for recovery. The first storage division comprises a portion of solid-state storage in a solid-state storage device. A data recovery module reads valid data from the first storage division in response to selecting the first storage division for recovery. The data recovery module stores the valid data in a second storage division of the solid-state storage device. The data recovery module passes the valid data through at least a portion of a write data pipeline for the solid-state storage device without passing the valid data to a host device and/or without routing the valid data outside of a solid-state storage controller for the solid-state storage device.
    Type: Application
    Filed: November 15, 2011
    Publication date: September 25, 2014
    Applicant: FUSION-IO, INC.
    Inventors: David Flynn, Bert Lagerstedt, John Strasser, Jonathan Thatcher, John Walker, Michael Zappe, Stephan Uphoff, Joshua Aune, Kevin Vigor
  • Patent number: 8843699
    Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Moon Cheon, Seon-Taek Kim, Chan-Ik Park, Sung-up Choi
  • Patent number: 8838875
    Abstract: A data processing system that includes a host system and an external data storage device with an erase before write memory device thereon can be operated by sending a file delete command from the host to the data storage device for one or more files stored thereon. The file delete command may specify a logical address and data to be invalidated associated with the deleted file. The data storage device may identify one or more units of memory allocation in the erase before write memory as containing invalid data based on the specified logical address and data to be invalidated. The data storage device may maintain a data structure that associates physical addresses for units of memory allocation in the erase before write memory with indications of whether the units of memory allocation contain invalid data. The data structure may be used to mark units of memory allocation associated with deleted files as containing invalid data.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Ik Park
  • Patent number: 8838877
    Abstract: A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: September 16, 2014
    Assignee: Apple Inc.
    Inventors: Nir Jacob Wakrat, Vadim Khmelnitsky, Daniel Jeffrey Post
  • Patent number: 8838925
    Abstract: A method for securely storing data in a multilevel memory of a portable data carrier. The multilevel memory includes one or several multilevel memory cells (SZ) which can assume respectively at least three levels (E, NE). The at least three levels represent a different data content, regarding which respective levels (E, NE) of a memory cell (SZ) are defined as valid or invalid. The levels (E, NE) of a respective memory cell (SZ) are selectively defined as valid or invalid in dependence on a required security level.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 16, 2014
    Assignee: Giesecke & Devrient GmbH
    Inventor: Wolfgang Rankl
  • Patent number: 8838881
    Abstract: Various embodiments of the present disclosure are generally directed to the accessing of data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a transfer command is received to transfer selected data between a control module and a memory module. The transfer command specifies a target address in the memory module and a sense threshold vector associated with the selected data. The sense threshold vector in the received transfer command is used to sense a programmed state of at least one solid-state memory cell at the target address responsive to the received transfer command. The transfer command may be a read or write command.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: September 16, 2014
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Bernie Rub
  • Patent number: 8838895
    Abstract: A solid state disk (SSD) caches disk-based volumes in a heterogeneous storage system, improving the overall storage-system performance. The hottest data blocks are identified based on two factors: the frequency of access, and temporal locality. Temporal locality is computed using a logarithmic system time. IO latency is reduced by migrating these hottest data blocks from hard-disk-based volumes to the solid-state flash-memory disks. Some dedicated mapping metadata and a novel top-K B-tree structure are used to index the blocks. Data blocks are ranked by awarding a higher current value for recent accesses, but also by the frequency of accesses. A non-trivial value for accesses in the past is retained by accumulating the two factors over many time spans expressed as a logarithmic system time. Having two factors, access frequency and the logarithmic system time, provides for a more balanced caching system.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: September 16, 2014
    Assignee: 21ViaNet Group, Inc.
    Inventors: Letian Yi, Chong (Ethan) Hao, Zaide Liu
  • Patent number: 8838883
    Abstract: A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 16, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • Patent number: 8838916
    Abstract: A method uses a record of I/O priorities in a determination of a storage medium of a hybrid storage system in which to store a file. The method maintains the record of I/O priorities by assigning an I/O temperature value to each request for access to the file based upon an I/O priority level of the process making the request. The method marks the file as hot if the file temperature value is greater than a threshold value. The method stores files marked as hot in a lower latency storage medium of the hybrid storage medium.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mingming Cao, Ben Chociej, Scott R. Conor, Steven M. French, Matthew R. Lupfer, Steven L. Pratt
  • Patent number: 8832359
    Abstract: An in-vehicle apparatus includes: a flash memory; a memory controller for executing an initialization process; a backup power source; a power source; a controller; and a power source controller. According to incompletion of initialization, the controller executes standby/boot process. According to completion of initialization, the controller executes the boot process. According to reception of data backup instruction, the controller stores data in the memory. The power source controller switches to a trigger standby mode. According to trigger, the power source controller inputs the energization instruction to the power source. According to termination of trigger, the power source controller inputs the data backup instruction to the controller. According to completion of backup, the power source controller halts to input the energization instruction, and switches to the trigger standby mode. According to incompletion of backup, the power source controller resets the switch and the power source.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 9, 2014
    Assignee: DENSO CORPORATION
    Inventor: Motoki Kanamori
  • Patent number: 8832356
    Abstract: Provided is a flash memory address translation method that may maintain at least one chip that may be divided based on at least one horizontal bank and at least one vertical channel, and may divide the at least one bank by at least one stripe partition, managing an error of a chip without deterioration in a performance of a small writing.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Hoon Baek, Jin Kyu Kim
  • Patent number: 8832355
    Abstract: A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Limited
    Inventors: Terumasa Haneda, Nina Tsukamoto, Yuji Hanaoka
  • Patent number: 8825938
    Abstract: Redundant solid-state memory devices are used to enhance the operation of a network storage system. To reduce the likelihood of substantially concurrent failure of two or more such memory devices, write allocation decisions are made so as to influence the wear on the various solid-state memory devices, so that not all of the solid-state memory devices wear out at the same rate. This can be accomplished by skewing the wear caused by erases/writes, across the solid-state memory devices, so that the devices experience unequal wear and, therefore, do not all fail at or approximately at the same time. The roles of the various flash devices are adjusted when a solid-state memory device is replaced, such that subsequent write allocation decisions are based on the maintenance history (e.g., replacement history) of the devices as well as the past write history.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: September 2, 2014
    Assignee: NetApp, Inc.
    Inventors: Daniel J. Ellard, Hooman Vassef
  • Patent number: 8825945
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Shashi Kiran Chilappagari, Xueshi Yang, Gregory Burd
  • Patent number: 8825942
    Abstract: A storage apparatus includes one or more memory units each having a plurality of memory blocks to store a file having data corresponding to a plurality of clusters, and a controller to store the file in the memory units such that such that the data of at least two sequential addresses of the clusters are stored in the memory blocks of different memory units.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: September 2, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Kyung-wook Ye, Jeong-uk Kang
  • Patent number: 8825967
    Abstract: A memory device, comprising a first control input port, a second control input port, a third control input port, a data input port, a data output port, an internal memory and control circuitry. The control circuitry is responsive to a control signal on the first control input port to capture command and address information via the data input port. When the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port. When the command is a write command, the control circuitry is responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: September 2, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Pyeon Hong Beom
  • Patent number: 8819328
    Abstract: The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 26, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Paul A. Lassa, David C. Brief
  • Patent number: 8817537
    Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: August 26, 2014
    Assignee: Green Thread, LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 8819334
    Abstract: The present disclosure relates to a data storage system and method that includes at least two solid state devices that can be classified in at least two different efficiency levels, wherein data progression is used to allocate data to the most cost-appropriate device according to the nature of the data.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: August 26, 2014
    Assignee: Compellent Technologies
    Inventors: Lawrence E. Aszmann, Michael J. Klemm, Michael H. Pittelko
  • Patent number: 8812804
    Abstract: A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 19, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven C. Goss, Gregory R. Conti, Narendar Shankar, Mehdi-Laurent Akkar, Aymeric Vial
  • Patent number: 8806156
    Abstract: A storage system comprises a plurality of flash packages comprising a plurality of flash chips, and a storage controller for receiving a first write request from a higher-level apparatus and sending a second write request of write data based on data conforming to this first write request to a write-destination flash package, and demonstrates a capacity virtualization function for causing a storage capacity to appear larger than an actual storage capacity for the higher-level apparatus, and for configuring a storage space using page units. The storage system generates a second VOL (logical volume) based on a first VOL, manages a plurality of VOLs comprising the first VOL and one or more second VOLs generated based on the first VOL as a VOL group, and allocates the same page to areas of the same address of the plurality of VOLs configuring the VOL group.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Masayuki Yamamoto
  • Patent number: 8806116
    Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: August 12, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy
  • Patent number: 8806108
    Abstract: A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Junji Ogawa
  • Patent number: 8806114
    Abstract: A data block may be moved between a first medium and a second medium. The movement of the data block involves measuring the access characteristic of the data block as the data block is stored on the first medium. The performance characteristics of the first medium and the second medium are then determined, in which each performance characteristic has a static performance characteristic component and a dynamic performance characteristic component. Alternatively or concurrently, the static performance characteristic components of the first medium and the second medium may be compared, and the dynamic performance characteristic components of the first medium and the second medium are compared. Accordingly, the data block is moved from the first medium to the second medium when at least one of these comparisons indicate that the second medium is more suitable for storing the data block having the access characteristic than the first medium.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: August 12, 2014
    Assignee: Microsoft Corporation
    Inventors: James R. Hamilton, Vladimir Sadovsky
  • Patent number: 8806170
    Abstract: For a storage apparatus where flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. The storage apparatus includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. The storage controller can form a storage area using a flash memory or a magnetic disk to create a logical volume. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions on the number deletions of the flash memory.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: August 12, 2014
    Assignee: Hitachi Ltd.
    Inventors: Masayuki Yamamoto, Akira Yamamoto, Akira Fujibayashi, Jun Kitahara, Yoshiki Kano
  • Patent number: 8799560
    Abstract: A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: August 5, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Satoru Hanzawa
  • Patent number: 8799605
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory including a plurality of memory cells, and a controller configured to control the nonvolatile memory. At a time of a boot operation, when a request for initialization of the memory device is issued, the controller does not return a response to the request until completion of the initialization, and the controller returns a response to the request when the initialization is completed.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Misao Hasegawa
  • Patent number: 8793430
    Abstract: In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Berhanu Iman, Ali R. Ganjuei
  • Patent number: 8793429
    Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: July 29, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Matthew Call, Lyndon S. Chiu, Robert L. Horn, Lan D. Phan
  • Patent number: 8788537
    Abstract: A computer readable medium stores a program causing a computer to execute a process including receiving an instruction for deleting an information group from a first memory; extracting, from the first memory, information regarding information groups having a parent-child relationship with a target information group to be deleted in accordance with the received instruction; extracting a user identification code associated with the target information group from a second memory; storing an identification code of the target information group, the information regarding the information groups, and the extracted user identification code in association with one another in a third memory; deleting the target information group from the first memory; and changing the structure information stored in the first memory to structure information obtained after the target information group has been deleted from the first memory, by changing the child information group as a child of the parent information group.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: July 22, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Haruki Matsui
  • Patent number: 8788745
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: July 22, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 8782329
    Abstract: A method for performing data shaping is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to contents of data to be written into or read from the Flash memory, generating/recovering an input seed of at least one randomizer/derandomizer; and utilizing the randomizer/derandomizer to generate a random function according to the input seed, for use of adjusting a plurality of bits of the data bit by bit. An associated memory device and a controller thereof are also provided.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: July 15, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 8782331
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokuni Yano, Shinichi Kanno, Hida Toshikatsu, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Patent number: 8782369
    Abstract: A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass migration of data from the fast tier to the slow tier. Data migration is frequently unidirectional with data migrating from the slow to the fast tier, reducing overhead during normal operation.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 15, 2014
    Assignee: LSI Corporation
    Inventors: Anant Baderdinni, Gerald E. Smith, Mark Ish
  • Patent number: 8775720
    Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). A first execution time needed to execute commands in a NVSM command queue is estimated, and a second execution time needed to execute commands in a disk command queue is estimated. An access command is inserted into a selected one of the NVSM command queue and the disk command queue in response to the first and second execution times, and one of the first and second execution times is updated in response to an estimated execution time of the access command.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 8, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alan T. Meyer, William B. Boyle, Mei-Man L. Syu, Virgil V. Wilkins, Robert M. Fallone
  • Patent number: 8775760
    Abstract: A system operation method for controlling a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes a plurality of physical blocks. The system operation method includes following steps. A first signal is received from a host system through a host interface. Whether a system setting of the host interface is to be modified is determined. If the system setting is to be modified, a system parameter is read from the physical blocks, and the system setting is modified according to the system parameter. A second signal is transmitted to the host system to establish a connection recognition between the rewritable non-volatile memory module and the host system. Thereby, the settings of transmission between the host system and the rewritable non-volatile memory module are made more flexible.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Phison Electonics Corp.
    Inventor: Chien-Hua Chu
  • Patent number: 8775758
    Abstract: A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware update in a directory, and a pointer is written to the directory in a location in the memory that is read during boot-up. In another embodiment, a block in a memory of a memory device is allocated for updated file system data comprising a firmware update and a directory. The updated file system data is written into the allocated location in the memory. A pointer is written to the firmware update in the directory, and a pointer is written to the updated file system data in a boot block in the memory, wherein the boot block is read during boot-up.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: July 8, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Andrew Tomlin, Dennis S. Ea, Daniel E. Tuers
  • Patent number: 8775722
    Abstract: Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 8, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven Sprouse, Sergey Anatolievich Gorobets
  • Patent number: 8769243
    Abstract: A data processing method for a memory storage apparatus having physical blocks is provided. The method includes: grouping the physical blocks into a data area, a spare area and a system area; configuring a plurality of logical addresses which would be formatted into a file allocation table area having cluster entry fields, a root directory area having directory entry fields and a file area having clusters; storing a communication file from the Kth cluster of the file area; recording a file description block corresponding to the communication file in the Mth directory entry field and storing an end of cluster chain mark in the cluster entry field corresponding to the last cluster of the clusters where the communication file stores, and K and M are positive integers which are larger than one. Accordingly, the method can prevent the communication file from being overwritten after the memory storage apparatus is formatted.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 1, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Ching-Wen Chang, Huan-Sheng Li
  • Patent number: 8769192
    Abstract: A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 1, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8762626
    Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Omprakash Bisen, Abdulla Pichen
  • Patent number: 8762629
    Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • Patent number: 8756366
    Abstract: A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks having a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 17, 2014
    Assignee: Silicon Motion, Inc.
    Inventors: Jieh-Hsin Chien, Hsiao-Te Chang
  • Patent number: 8751766
    Abstract: A storage system including: a plurality of storage devices; a volatile memory which temporarily stores data; a nonvolatile memory; a battery saving power; a cache control unit which sets, according to battery charging rate of the battery, a part of the data stored in the volatile memory as save target data which are to be saved to the nonvolatile memory when power interruption occurs, and saves the part of the data, which is set as the save target data, to the nonvolatile memory by using power of the battery when power interruption occurs.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 10, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Inoue, Yasuyuki Nagasoe
  • Patent number: 8751727
    Abstract: A storage apparatus includes: a memory allowing an operation to be carried out in order to additionally write new write data into a storage area already used for storing previous write data so as to store the new data in the storage area along with the previous write data; an input/output section configured to receive write data in a write access; and a control section configured to write the write data into the memory on the basis of the write access, wherein, in internal processing based on the write access, the control section carries out an additional-write operation for a storage area already used for storing the previous write data in the internal processing.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: June 10, 2014
    Assignee: Sony Corporation
    Inventors: Keita Kawamura, Shingo Aso
  • Patent number: 8751731
    Abstract: The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Alan Chen, Siamack Nemazie, Dale P. McNamara
  • Patent number: 8751735
    Abstract: A system including a controller in communication with a memory. The memory includes memory cells arranged in memory blocks. Each memory cell is capable of storing a plurality of bits. Each memory block defines a plurality of pages. A page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block. The controller is configured to write data to selected pages in one or more memory blocks. The system includes circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data. The predetermined number is based on one or more of a number of pages in each memory block and a number of bits in the plurality of bits.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 10, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Qun Zhao, Xinhai Kang
  • Patent number: 8745310
    Abstract: A storage apparatus includes a flash memory, a second memory for storing an address translation table, and a control section. The flash memory is formed of multiple pages, each having a spare area, and data are stored on a page-by-page basis. The control section has the functions of: saving the table to the flash memory; when writing/updating data, storing the user data, recording, in the table, a correspondence between a logical page address and an address of a page in which the data is stored, and storing information for identifying the corresponding logical page address in the spare area of the page; when the apparatus is started, detecting pages to which data was written after the most recent saving of the table; and scanning the spare area of each page detected and reproducing a state of the table as updated after the most recent saving to reconstruct the table.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Toshiyuki Nishihara, Kazuyuki Date
  • Patent number: 8745315
    Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: June 3, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 8745357
    Abstract: A method and a corresponding apparatus provide for remapping for wear leveling of a memory. The method is implemented as logic and includes the steps of receiving a memory operation, the memory operation including a logical memory address; dividing the logical address into a logical block address portion, a logical line address portion, and a logical subline address portion; translating the logical block address portion into a physical block address; selecting a line remap key; applying the line remap key to the logical line address portion to produce a physical line address; producing a physical subline address portion; and combining the physical block, line, and subline address portions to produce a physical address for the memory operation.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Joseph A. Tucek, Eric A. Anderson