Abstract: A hypervisor runs on a host computer system and defines at least one virtual machine. An address space of the virtual machine resides on physical memory of the host computer system under control of the hypervisor. A guest operating system runs in the virtual machine. At least one of a host operating system and the hypervisor sets parts of the address space of the host computer system corresponding to parts of the address space of the virtual machine to a locked state in which those parts can be read but not written to.

Abstract: Provided are techniques for migrating a first extent, determining a spatial distance between the first extent and a second extent, determining a ratio of a profiling score of the second extent to the spatial distance, and, in response to determining that the ratio exceeds a threshold, migrating the second extent.

Abstract: A virtualization apparatus is provided. The virtualization apparatus includes a plurality of virtual machines configured to have priority levels, a memory pool configured to be shared between the plurality of virtual machines and store part of data stored in a system memory of each of the plurality of virtual machines, and a memory pool manager configured to process a memory allocation request or a data storage request regarding the memory pool in consideration of the priority levels of the plurality of virtual machines, a guaranteed memory size for each of the plurality of virtual machines, and a size of memory that can be allocated to each of the plurality of virtual machines.

Abstract: A request management system includes a request priority queue module prioritizing requests to be placed in queues based on priorities, and a request priority rule module setting an order of placement of the requests in the queues. The request management system further includes a computerized request monitoring and management module dynamically managing processing of a request from the prioritized requests based on a request processing statistic, the priorities and the order of placement.

Abstract: In response to read and write requests for data blocks at logical storage locations, a block mapping device determines physical storage locations on the storage devices. Read requests switch over secondary storage devices to the active mode when they are in the passive mode. Write requests write data blocks only to the primary storage devices. Secondary storage devices that have not been accessed for a minimum activation time may be switched over from the active to the passive mode to save power consumption and cooling. Data migration and data recall policies control moving of data blocks between the primary and secondary storage devices and are primarily based on threshold values.

Abstract: This invention provides a storage system to store data used by computers. A storage system coupled to a computer and a management apparatus, includes storage devices accessed by the computer and a control unit that controls the storage devices, in which the control unit performs the following operations: setting, in the storage devices, a first virtual device including a first logical device; setting a second virtual device which including a second logical device, which is a virtual volume accessed by the computer; allocating an address of the first logical device to the second logical device; and changing the allocation to change storage areas of the virtual volume.

Abstract: Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine.

Abstract: Disclosed is a computer implemented method and computer program product to prioritize paging-in pages in a remote paging device. An arrival machine receives checkpoint data from a departure machine. The arrival machine restarts at least one process corresponding to the checkpoint data. The arrival machine determines whether a page associated with the process is pinned. The arrival machine associates the page to the remote paging device, responsive to a determination that the page is pinned. The arrival machine touches the page.

Abstract: A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device.

Abstract: A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: A fast masked summing comparator apparatus includes a comparator unit configured to compare a masked first number to a masked sum of a second number and a third number to determine whether the masked sum is equivalent to the masked first number without performing a summation portion of an addition operation between the second number and the third number. The comparator unit may concurrently mask both the sum and the first number using the same mask value.

Abstract: An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.

Abstract: Described techniques increase runtime performance of workloads executing on a hypervisor by executing virtualization-aware code in an otherwise non virtualization-aware guest operating system. In one implementation, the virtualization-aware code allows workloads direct access to physical hardware devices, while allowing the system memory allocated to the workloads to be overcommitted. In one implementation, a DMA filter driver is inserted into an I/O driver stack to ensure that the target virtual memory of a DMA transfer is resident before the transfer begins. The DMA filter driver may utilize a cache to track which pages of memory are resident. The cache may also indicate which pages of memory are in use by one or more transfers, enabling the hypervisor to avoid appropriating pages of memory during a transfer.

Abstract: An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address.

Abstract: A method for managing a virtual memory system configured to allow variable-sized pages is provided. The size of a page is not required to be a power of two. Variable, arbitrarily-sized pages are mapped to a contiguous segment or virtual address space. The method also provides for efficient relocation, insertion, and removal of data in a virtual memory region. The method also provides virtual lookup-tables.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: A storage controller that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption, and a method for controlling such a storage controller are provided. The storage controller includes a plurality of nonvolatile memory modules having a plurality of nonvolatile memory chips for storing data from a host computer, and a nonvolatile memory control unit for controlling data input to and output from the host computer by controlling a power source for the nonvolatile memory modules. When reading or writing data from or to a designated nonvolatile memory module at a specified time in response to a data read/write request from the host computer, the nonvolatile memory control unit controls the power source for only the designated nonvolatile memory module to be turned on.

Abstract: A method and a processing device are provided for mapping a non-page aligned memory buffer to an address space of a process. A beginning portion of a non-page aligned memory buffer and an ending portion of the non-page aligned memory buffer may be copied from respective original memory pages to new memory pages. Unused portions of the new memory pages may be initialized to zeros, ones, or other values. A safe buffer may be created, which resides in the new memory pages and all original memory pages of the non-page aligned memory buffer, except for the original memory pages including either the beginning portion or the ending portion of the non-page aligned buffer. The safe buffer may then be mapped to an address space of a process while avoiding unintended information disclosure.

Abstract: Parallel, coordinated, and optimized access of real Base and Alias DASDs by one or more virtual machines, each utilizing one or more virtual Base and Alias DASDs. Each of a plurality of virtual machines defines a virtual Base DASD device and a modified operating system may coordinate the virtual machine activity on real Base and Alias devices to maximize overall system throughput. In more complex embodiments, one or more virtual machines define one or more virtual Bases and associated virtual Alias devices in which case wherein the embodiments described coordinate their activity on one or more real Base and Alias devices to maximize overall system throughput.

Abstract: A first virtual storage and a second virtual storage share an external LU (Logical Unit) inside an external storage. The first virtual storage comprises a first LU, which comprises multiple first virtual areas and conforms to thin provisioning, and an external capacity pool, which is a storage area based on the external LU, and which is partitioned into multiple external pages, which are sub-storage areas. The second virtual storage comprises a second LU, which comprises multiple second virtual areas and conforms to thin provisioning.

Abstract: A digital signal processing apparatus comprises a main memory, a processing unit, a cache, and a rotate buffer unit. The main memory includes at least R memory banks for storing a plurality of data of digital signal. The cache is coupled between the main memory and the processing unit. The cache includes at least R×R cache units for storing part of data of the main memory to provide to the processing unit. The cache also temporarily stores operation results of the processing unit. The rotate buffer unit is coupled between the main memory and the cache for buffering and rotating the data outputted from each of the memory banks to write to the cache, and the data outputted from part of the cache units to write back to the corresponding memory banks respectively.

Abstract: A method is provided for managing errors in a virtualized information handling system that includes an error detection system and a hypervisor allowing multiple virtual machines to run on the information handling system. The hypervisor may assign at least one memory region to each of multiple virtual machines. The error detection system may detect an error, determine a physical memory address associated with the error, and report that address to the hypervisor. Additionally, the hypervisor may determine whether the memory region assigned to each virtual machine includes the physical memory address associated with the error. The hypervisor may shut down each virtual machine for which a memory region assigned to that virtual machine includes the physical memory address associated with the error, and not shut down each virtual machine for which the memory regions assigned to that virtual machine do not include the physical memory address associated with the error.

Abstract: In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The write multiplexing module further configured to send each segment from the set of segments identified as a trailing segment to a portion of the shared memory mutually exclusive from the lead memory bank.

Abstract: Provided are a method, system, and an article of manufacture, wherein resources corresponding to at least one copy pool are acquired, and wherein the at least one copy pool has been defined for a first primary storage pool of a storage hierarchy. The acquired resources are retained, in response to determining that data cannot be written to the first primary storage pool. The data is written to the at least one copy pool, in response to writing the data to a second primary storage pool of the storage hierarchy.

Abstract: Techniques are described herein that are capable of optimizing (i.e., deduplicating) data in a virtualization environment. For example, optimization designations (a.k.a. deduplication designations) may be assigned to respective regions of a virtualized storage file. A virtualized storage file is a file that is configured to be mounted as a disk or a volume to provide a file system interface for accessing hosted files. In accordance with this example, each optimization designation indicates an extent to which the respective region is to be optimized (i.e., deduplicated). In another example, a virtualized storage file is mounted to provide a virtual disk that includes hosted files. In accordance with this example, optimization designations are assigned to the respective hosted files. In further accordance with this example, each optimization designation indicates an extent to which the respective hosted file is to be optimized.

Abstract: A storage system, method and program product, the system comprising: storage devices; and a controller configured to: provide virtual volumes to a host computer; manage logical units on the storage device and storage pools; allocate, in response to receiving a write request to a virtual volume, a storage region of the storage pools; and store data related to the write request in the storage region allocated, wherein the controller is further configured to: allocate first storage region in first storage pool to first virtual volume based on first size of the first storage region or the first virtual volume; allocate a second storage region in a second storage pool to a second virtual volume of the plurality of virtual volumes based on a second size of the second storage region or the second virtual volume.

Abstract: Content item recommendations are generated for users based on metadata associated with the content items and a history of content item usage associated with the users. Each content item recommendation identifies a user and a content item and includes a score that indicates how likely the user is to view the content item. Based on the content item recommendations, and constraints of one or more caches, the content items are selected for storage in one or more caches. The constraints may include users that are associated with each cache, the geographical location of each cache, the size of each cache, and/or costs associated with each cache such as bandwidth costs. The content items stored in a cache are recommended to users associated with the cache.

Abstract: Controlled partition shut-down is provided within a shared memory partition data processing system including a shared memory partition, a paging service partition, a hypervisor and a shared memory pool within physical memory. The hypervisor manages access to logical pages within the pool and page-out of pages from the pool to external paging storage via the paging service partition. A respective paging service stream exists between the paging service partition and hypervisor for each shared memory partition, with each stream including a stream state. The control method includes: responsive to a shut-down initiating event, notifying the paging service partition to shut down, and determining whether a shared memory partition is currently active, and if so, signaling the hypervisor to complete paging activity for the active memory partition and waiting for its stream state to enter a suspended or a completed state before automatically shutting down the paging service partition.

Abstract: A method begins by a processing module receiving an encoded data slice for storage. The method continues with the processing module obtaining metadata associated with the encoded data slice and interpreting the metadata to determine whether the encoded data slice is to be stored in a first access speed memory or a second access speed memory, wherein the first access speed memory has a higher data access rate than the second access speed memory. The method continues with the processing module storing the encoded data slice in a memory device of the first access speed memory when the encoded data slice is to be stored in the first access speed memory and storing the encoded data slice in a memory device of the second access speed memory when the encoded data slice is to be stored in the second access speed memory.

Abstract: Efficiently determining identical pieces of memory within a computer memory area, which is occupied by a virtual machine manager hosting multiple guests and the computer memory area being logically separated into memory pages of a unique size. Each guest is inspected for its structural characteristics by the virtual machine manager. The structural characteristics of each guest are compared by the virtual machine manager, wherein memory regions of guests having a similar structure are identified; and the identical memory pages are identified by the virtual machine manager by comparing hash values of memory pages located within memory regions of guests having a similar structure, wherein identical memory pages are determined by comparing hash values calculated over the contents of the memory pages.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Abstract: Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.

Abstract: A kernel of the operating system reorganizes a plurality of memory units into a plurality of virtual nodes in a virtual non-uniform memory access architecture in response to receiving a configuration of the plurality of memory units from a firmware. A subsystem of the operating system determines an order of allocation of the plurality of virtual nodes calculated to maintain a maximum number of the plurality of memory units devoid of references. The memory controller transitions one or more memory units into a lower power state in response to the one or more memory units being devoid of one or more references for the period of time.

Abstract: A system for performing storage operations using hierarchically configured storage operation cells. The system includes a first storage manager component and a first storage operation cell. The first storage operation cell has a second storage manager component directed to performing storage operations in the first storage operation cell. Moreover, the first storage manager component is programmed to instruct the second storage manager regarding performance of storage operations in the first storage operation cell.

Abstract: When shifting the condition of a pair of a main volume and a sub-volume from a split condition to a pair condition according to a request from a user, an information processing unit which can access the sub-volume is inquired whether it mounts the sub-volume or not. As a result, if a managing computer receives a notice from the information processing unit that it mounts the sub-volume, the managing computer displays a warning on its display. Thereby, data on the sub-volume can be prevented from being erased by an operation mistake of the user.

Abstract: Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.

Abstract: Embodiments of the present invention are directed to enhancing VPAR monitors to allow an active VPAR to be moved from one machine to another, as well as to enhancing virtual-machine monitors to move active VPARs from one machine to another. Because traditional VPAR monitors lack access to many computational resources and to executing-operating-system state, VPAR movement is carried out primarily by specialized routines executing within active VPARs, unlike the movement of guest operating systems between machines carried out by virtual-machine-monitor routines.

Abstract: A diagnostic tool sends a request format designating a virtual address, which is different from a real address for an EEPROM. When a microcomputer determines that an address designated by the received request format is a virtual address assigned to the EEPROM, the microcomputer executes a process, which is designated by the received request format, with respect to the virtual address assigned to the EEPROM.

Abstract: A storage apparatus comprises a disk device and a disk adapter for controlling the disk device. The disk adapter controls the disk device and forms a data volume and a pool volume, creates a data block for parity data, compresses write data and the created parity data, and stores a number of compressed data blocks equal to or less than a predetermined number and stores compressed parity data that are within a predetermined size in storage areas in an actual volume, and stores the remaining compressed data blocks of a number greater than the predetermined number and compressed parity data that exceed the predetermined size in storage areas in the pool volume corresponding to a virtual volume.

Abstract: A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. A cache of connection structures represents cached paths to the real paging structures. The mapped paging tables are protected using RW-bit. A paging cache is validated according to TLB resets. Non-active paging tree tables can be also protected at the time when they are activated. Tracking of access (A) bits and of dirty (D) bits is implemented along with synchronization of A and D bits in guest physical pages.

Abstract: A method of dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system migrates processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. A hypervisor running on the destination computer system receives a page fault and virtual address of a page for said virtual machine from a processor of the destination computer system and determines if the page is in local memory of the processor.

Abstract: An apparatus generally having a processor, a cache and a circuit is disclosed. The processor may be configured to generate (i) a plurality of access addresses and (ii) a plurality of program counter values corresponding to the access addresses. The cache may be configured to present in response to the access addresses (i) a plurality of data words and (ii) a plurality of address information corresponding to the data words. The circuit may be configured to record a plurality of events in a file in response to a plurality of cache misses. A first of the events in the file due to a first of the cache misses generally includes (i) a first of the program counter values, (ii) a first of the address information and (iii) a first time to prefetch a first of the data word from a memory to the cache.

Abstract: The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also includes adding the physical registers corresponding to the first set of architected registers to the set of rename registers.

Abstract: Described techniques increase runtime performance of workloads executing on a hypervisor by executing virtualization-aware code in an otherwise non virtualization-aware guest operating system. In one implementation, the virtualization-aware code allows workloads direct access to physical hardware devices, while allowing the system memory allocated to the workloads to be overcommitted. In one implementation, a DMA filter driver is inserted into an I/O driver stack to ensure that the target guest physical memory of a DMA transfer is resident before the transfer begins. The DMA filter driver may utilize a cache to track which pages of memory are resident. The cache may also indicate which pages of memory are in use by one or more transfers, enabling the hypervisor to avoid appropriating pages of memory during a transfer.

Abstract: In one embodiment, a mechanism for virtual logical volume management is disclosed. In one embodiment, a method for virtual logical volume management includes writing, by a virtual machine (VM) host server computing device, a control block to each of a plurality of network-capable physical storage devices and mapping, by the VM host server computing device, physical storage blocks of the plurality of network-capable physical storage devices to virtual storage blocks of a virtual storage pool by associating the physical storage blocks with the virtual storage blocks in the control block of the network-capable physical storage device housing the physical storage blocks being mapped.

Abstract: A system is described for creating compact aggregation working areas for efficient grouping and aggregation using multi-core CPUs. The system implements operations including computing a running aggregate for a group within a business intelligence (BI) query, and identifying a location to store running aggregate information within an aggregation working area of a cache. The aggregation working area includes first and second data structures. The first data structure stores running aggregate information that is associated with a group that is accessed frequently relative to a threshold. The second data structure stores running aggregate information that is associated with a group that is accessed infrequently relative to the threshold. The operations also include storing the running aggregate information in either the first or second data structure of the aggregation working area based on a characterization of the group as a frequently or infrequently accessed group.

Abstract: Paging memory from random access memory (‘RAM’) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.