Abstract: A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash table system comprises inserting the entry into the first hash table, and, when the first hash table reaches a threshold load factor, flushing entries into the second hash table. Flushing the first hash table into the second hash table may comprise sequentially flushing the first hash table segments into corresponding second hash table segments. When looking up a key/value pair corresponding to a selected key in the hash table system, the system checks both the first and second hash tables for values corresponding to the selected key. The first and second hash tables may be divided into hash table segments and collision policies may be implemented within the hash table segments.

Abstract: Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.

Abstract: A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer.

Abstract: A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received.

Abstract: A system is described for providing scalable in-memory caching for a distributed database. The system may include a cache, an interface, a non-volatile memory and a processor. The cache may store a cached copy of data items stored in the non-volatile memory. The interface may communicate with devices and a replication server. The non-volatile memory may store the data items. The processor may receive an update to a data item from a device to be applied to the non-volatile memory. The processor may apply the update to the cache. The processor may generate an acknowledgement indicating that the update was applied to the non-volatile memory and may communicate the acknowledgment to the device. The processor may then communicate the update to a replication server. The processor may apply the update to the non-volatile memory upon receiving an indication that the update was stored by the replication server.

Abstract: A data processing apparatus comprises a monolithic integrated circuit having a data processor, a non-volatile memory storing at least one security code, and at least one interface at the boundary of the integrated circuit via which communication with the data processor can occur. Processing by the data processor of data received at the at least one interface is controlled by the at least one security code.

Abstract: In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing device. That is, the associative cache implements a fully associative map between a predetermined set of addresses and data values, employing only a single tag fetch comparison.

Abstract: In one embodiment, a cache memory includes a data array having N ways and M sets and at least one fill buffer coupled to the data array, where the data array is segmented into multiple array portions such that only one of the portions is to be accessed to seek data for a memory request if the memory request is predicted to hit in the data array. Other embodiments are described and claimed.

Abstract: Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss.

Abstract: A tiled memory and a method of power management within the tiled memory provides efficient use of energy within a computer storage, which may be a spiral cache memory. The tiled memory is power-managed by placing tiles in a power-saving state, which may be a state in which storage circuits are powered-down and network circuits are powered-up, so that for serially-connected tiles, information can still be forwarded by a tile in the power-saving state. The tiles may be power managed under direction of a central controlled, which sends commands to the tiles to enter and leave the power-saving state, or the tiles may self-manage their power-saving state according to activity measured at the individual tiles. Activity may be measured at the tiles of a spiral cache by comparing a hit rate and a push back rate to corresponding thresholds. The measurements may be used with either tile-managed or centrally-managed techniques.

Abstract: Aspects relate to systems and methods for implementing a hash function using a stochastic and recurrent process, and performing arithmetic operations during the recurrence on portions of a message being hashed. In an example method, the stochastic process is a Galton-Watson process, the message is decomposed into blocks, and the method involves looping for a number of blocks in the message. In each loop, a current hash value is determined based on arithmetic performed on a previous hash value and some aspect of a current block. The arithmetic performed can involve modular arithmetic, such as modular addition and exponentiation. The algorithm can be adjusted to achieve qualities including a variable length output, or to perform fewer or more computations for a given hash. Also, randomizing elements can be introduced into the arithmetic, avoiding a modular reduction until final hash output production.

Abstract: A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address.

Abstract: A method of configuring a unified cache includes identifying unified cache way assignment combinations for an application unit. Each combination has an associated error rate. A combination is selected based at least in part on the associated error rate. The unified cache is configured in accordance with the selected combination for execution of the application-unit.

Abstract: An instruction cache system includes an instruction-cache data storage unit that stores cache data per index, and an instruction cache controller that compresses and writes the cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data. The instruction cache controller calculates a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.

Abstract: An information processing system includes: a data processing unit that executes verification processing for a content recorded in a disk and reproduces the disk-recorded content under a condition that the verification succeeds, wherein the data processing unit randomly selects hash units, which are objects of collation, from among a plurality of hash units formed with component data items of the content, reads the selected hash units sequentially from the disk, calculates hash values, and collates the calculated hash values with collation hash values; and the data processing unit executes reading sequence determination processing so as to determine a reading sequence in which the selected hash units are sorted according to recording positions in a disk, and reads the selected hash units according to the determined reading sequence.

Abstract: A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.

Abstract: A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.

Abstract: A method for selecting a hash function, a method for storing and searching a routing table and devices thereof are provided. The method for selecting a hash function includes: hashing data to be hashed by using a current alternative hash function; decoding a hash result; accumulating decoded results until no carry occurs during the accumulation; and selecting a current alternative hash function with no carry generated as a formal hash function. The method for storing a routing table includes: dividing the routing table into a next-level node pointer portion and a prefix portion for being stored; and selecting a hash function by using the above method for selecting a hash function. The method for searching a routing table includes: directly searching an IP address to be searched according to a directly stored length of a next-level node pointer portion for storing the routing table; and reading a prefix node according to a searched result.

Abstract: A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic receives an address and predicts in which one of the cache ways the data associated with the address is likely to be stored. The way prediction logic causes an enabling signal to be supplied only to the way predicted to contain the requested data. The remaining (N?1) of the cache ways do not receive the enabling signal. The power consumed by the cache is thus significantly reduced.

Abstract: At least two devices having different characteristics are provided as one file system, and the file system stores a file in a device according to the file purpose. In file system operation, a device characteristic acquiring unit acquires characteristic information of the respective devices by using a device characteristic database, a device characteristic acquiring interface, and stores the information in the device characteristic holding. In file operation for preparing file management information in file storing process, a file purpose interpreting unit interprets the purpose and attribute of the file and registers a characteristic flag representing the characteristic of the file in the file management information. In file operation for actually writing a file, a storage device decision unit decides a file storage location device on the characteristic flag in the file management information and information of the device characteristic holding unit to perform a device free region securing process.

Abstract: Machine-readable media, methods, apparatus and system for detecting a data access violation are described. In some embodiments, current memory access information related to a current memory access to a memory address by a current user thread may be obtained. It may be determined whether a cache includes a cache entry associated with the memory address. If the cache includes the cache entry associated with the memory address, then, an access history stored in the cache entry and the current memory access information may be analyzed to detect if there is at least one of an actual violation and a potential violation of accessing the memory address.

Abstract: Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates that a plurality of non-dedicated cache sets within the cache should operate as spill cache sets or receive cache sets. The cache controller sets the plurality of non-dedicated cache sets to spill an evicted cache line to an associated cache set in another cache in the event of a cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the spill cache sets. The cache controller sets the plurality of non-dedicated cache sets to receive an evicted cache line from another cache set in the event of the cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the receive cache sets.

Abstract: An apparatus, system, and method are disclosed for validating that correct data is read from a storage device. A read request receiver module receives a read storage request to read a data segment of a file or object stored on a data storage device. The storage request includes one or more source parameters for the data segment. The source parameters include one or more virtual addresses that identify the data segment. A hash generation module generates one or more hash values from the virtual addresses. A read data module reads the requested data segment and returns one or more data packets and corresponding stored hash values stored with the data packets. The stored hash values were generated from a data segment written to the data storage device that contains data of the data packets. A hash check module verifies that the generated hash values match the respective stored hash values.

Abstract: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.

Abstract: Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache. For each request, the system makes a prediction of a way in which the cache line resides based on a corresponding entry in the way prediction table. The system then checks for the presence of the cache line in the predicted way. Upon determining that the cache line is not present in the predicted way, but is present in a different way, and hence the way was mispredicted, the system increments a corresponding record in a conflict detection table. Upon detecting that a record in the conflict detection table indicates that a number of mispredictions equals a predetermined value, the system copies the corresponding cache line from the way where the cache line actually resides into the predicted way.

Abstract: The present invention relates to an IF address lookup apparatus using a Bloom filter and a multi-hashing architecture that includes a buffering means that outputs a prefix of an inputted address having the number of bits reduced by one bit whenever a control signal is received at the time of outputting the prefix of the inputted address; a hashing hardware that generates a plurality of hashing indexes by hashing the prefix (hereinafter, referred to as “output prefix”) outputted from the buffering means; a Bloom filter that determines whether or not the output prefix is an entry of the hash table by using the plurality of hashing indexes; and a processor that includes the hash table and an overflow table and outputs a prefix that matches the output prefix by searching entries of locations of the hash table indicated by the plurality of hashing indexes and entries stored in the overflow table when a Bloom filter's determination result is positive and outputs the control signal to the buffering means when the ma

Abstract: A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a dual hash technique to rapidly store and/or retrieve connection state information for cached connections in a plurality of index tables that are indexed by hashing network protocol address information with a pair of irreducible CRC hash algorithms to obtain an index to the memory location of the connection state information.

Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Abstract: A multi mode cache system that uses a direct mapped cache scheme for some addresses and an associative cache scheme for other addresses.

Abstract: Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with said memory, calculating one or more matches between said events and said data stored in one or more cache-lines of said cache, storing event time stamps of events associated with said matches, generating one or more priority values based on said event time stamps, concurrently transmitting said data to said memory based on said priority values.

Abstract: A cache memory system controlled by an arbiter includes a memory unit having a cache memory whose capacity is changeable, and an invalidation processing unit that requests invalidation of data stored at a position where invalidation is performed when the capacity of the cache memory is changed in accordance with a change instruction. The invalidation processing unit includes an increasing/reducing processing unit that sets an index to be invalidated in accordance with a capacity before change and a capacity after change and requests the arbiter to invalidate the set index, and an index converter that selects either an index based on the capacity before change or an index based on the capacity after change associated with an access address from the arbiter, and the capacity of the cache memory can be changed while maintaining the number of ways of the cache memory.

Abstract: The present invention comprise methods and systems for enforcing allowable hardware configurations. The present invention utilizes shadow registers, which act as gatekeepers for actual sensitive configuration registers. An attempted write to the actual sensitive configuration registers is first stored in a corresponding shadow register and is subsequently validated via a cryptographic hash register before the values are passed to the actual configuration register.

Abstract: A system and method for address space layout randomization (“ASLR”) for a Windows operating system is disclosed. The address space layout includes one or more memory regions that are identified and then a particular implementation of the system randomizes the identified memory region in order to prevent any software vulnerabilities.

Abstract: A novel method is described for applying various hash methods used in conjunction with a query with a Group By clause. A plurality of drawers are identified, wherein each of the drawers is made up of a collection of cells from a single partition of a Group By column and each of the drawers being defined for a specific query. A separate hash table is independently computed for each of the drawers and a hashing scheme (picked from among a plurality of hashing schemes) is independently applied for each of the drawers.

Abstract: An input data enlarging unit (100) derives a first enlargement unit output and a second enlargement unit output that are uniquely specified by input data (103) to output the same. The first enlargement unit output and the second enlargement unit output are elements of output data set B which forms a group. An ?-? hash function calculation unit (101) receives as input the first enlargement unit output to calculate an h? function which is specified by hash-function-specifying data (104) and an element of the H? function set. The function set H? is such that the number of h?H ? which satisfies h(x)?h(y)=d for an arbitrary element d of the output data set B and two different elements x and y of the output data set B is equal to or smaller than |H?|·?. An adding unit (102) adds together the result of calculation of the function H? and the second enlargement unit output to output a result of the addition.

Abstract: An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).

Abstract: A data processing apparatus is disclosed that comprises: at least one data processor for processing data; a set associative cache for storing a plurality of values to be processed by said data processor, each value being identified by an address of a memory location within a memory storing said value, said set associative cache being divided into a plurality of cache ways; a data store comprising a plurality of storage locations for storing a plurality of identifiers, each identifier identifying a cache way that a corresponding value from said set associative cache is stored in and each having a valid indicator associated therewith, said plurality of identifiers corresponding to a plurality of values, said plurality of values being values stored in consecutive addresses such that said data store stores identifiers for values stored in a region of said memory; current pointer store for storing a current pointer pointing to a most recently accessed storage location in said data store; offset determining circuit

Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Abstract: Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

Abstract: The present invention relates to a memory device, in particular, to a memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a cache data injection into the particular cache line triggered by a bus-actor.

Abstract: A method and system that aggregates data associated with one or more entities from different data sources are provided. The data sources include documents, web pages, or images that have information about one or more entities. The information is extracted from the data sources based on criteria that define the entities. The extracted information is utilized to generate a hash identifier that corresponds to each entity and one or more storage locations. The one or more storage locations and associated hash identifiers are utilized to store the extracted information corresponding to the entities, and the extracted information for each entity is structured as a virtual page that is stored in an index having references to the data sources. The index storing the virtual pages is notified or updated when the associated data sources are modified.

Abstract: Data processing apparatus comprising: a chunk store containing specimen data chunks, a manifest store containing at least one manifest that represents at least a part of a data set and that comprises at least one reference to at least one of said specimen data chunks, a sparse chunk index containing information on only those specimen data chunks having a predetermined characteristic, the processing apparatus being operable to process input data into input data chunks and to use the sparse chunk index to identify at least one of said at least one manifest that includes at least one reference to one of said specimen data chunks that corresponds to one of said input data chunks having the predetermined characteristic.

Abstract: A cache system includes a cache having a plurality of cache units, a prediction table and a hashing module. The prediction table is utilized to store way information of at least one cache unit corresponding to at least one accessing address, and the hashing module generates a hashing value corresponding to a target accessing address and reads way information from the prediction table or writes the way information to the prediction table by using the hashing value as an index.

Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Abstract: A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.

Abstract: A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication.

Abstract: Various systems and methods for implementing a Galois-based incremental hash module are disclosed. For example, a method involves computing a first hash of a first string of an input stream. The first hash is computed by performing one or more Galois mathematical operations upon portions of the first string. A second hash of a second string, which overlaps the first string, can then be computed by processing the first hash.

Abstract: A method and system for dynamically determining hash values for file transfer integrity validation. In response to a request for a transfer of a data file between a first computing system and a second computing system, the first computing system loads a first portion of the data file to a buffer. The first computing system determines a first hash function value based on the first portion. The first computing system loads a second portion of the data file portion to the buffer and determines a second hash function value incrementally based on the first and second data file portions. The first and second data file portions are non-overlapping portions of the data file being transferred.

Abstract: A relay unit inputs data and an index. A cache management unit determines whether or not a space area to cache data exists. In the case where there is a space area, the cache management unit caches data. An identifier generating unit generates an identifier corresponding to contents of the cached data. The identifier is registered in a cache data table in association with the data. The identifier is registered in a cache index table in association with the index. In the case where there is no space area, the cache management unit secures a space area. The cache management unit unregisters an identifier associated with the data which was cached in the secured area.

Abstract: A processor cache memory subsystem includes a cache memory having a configurable associativity. The cache memory may operate in a fully associative addressing mode and a direct addressing mode with reduced associativity. The cache memory includes a data storage array including a plurality of independently accessible sub-blocks for storing blocks of data. For example each of the sub-blocks implements an n-way set associative cache. The cache memory subsystem also includes a cache controller that may programmably select a number of ways of associativity of the cache memory. When programmed to operate in the fully associative addressing mode, the cache controller may disable independent access to each of the independently accessible sub-blocks and enable concurrent tag lookup of all independently accessible sub-blocks, and when programmed to operate in the direct addressing mode, the cache controller may enable independent access to one or more subsets of the independently accessible sub-blocks.