Abstract: A method is provided for use in a storage processor, the method comprising: receiving a write request, the write request including a request to store user data in an array that includes a plurality of solid-state drives (SSD); executing the write request by: identifying metadata that is associated with the write request, and writing the user data and the metadata to different data streams that are opened on the plurality of SSDs; wherein writing the user data and the metadata to different data streams causes: (i) the user data to be stored in one or more first erase units of any of the plurality of SSDs, and (ii) the metadata to be stored in one or more second erase units of any of the plurality of SSDs, such that no part of the metadata is stored on any of the one or more first erase units, and no part of the user data is stored on any of the one or more second erase units.

Abstract: Selectively masking data in messages is provided. A masking expression is retrieved from a schema. The masking expression corresponds to a particular attribute within related messages generated by a producer application and sent to an immutable datastore for consumption by a consumer application of the computer that is registered to receive the messages related to a particular topic from the immutable datastore. A particular attribute value is masked only in those messages received from the immutable datastore that contain the particular attribute value during a time period when the particular attribute value is associated with the masking expression.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: According to one embodiment, a magnetic disk device comprises magnetic disks, heads, and a controller. The controller does not allocate logical addresses to sectors of a first area to be specified in such a manner as to correspond to a defect existing in a predetermined recording area, the first area being within the predetermined recording area constituted of a plurality of cylinders adjacent to each other in the magnetic disks, and uniquely allocates logical addresses to sectors of a second area other than the first area. The controller makes allocation of logical addresses to the sectors of the second area different from each other according to the number of defects existing in the predetermined recording area.

Abstract: Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Abstract: A system, method, and machine-readable storage medium for analyzing a state of a data object are provided. In some embodiments, the method includes receiving, at a storage device, a metadata request for the data object from a client. The data object is composed of a plurality of segments. The method also includes selecting a subset of the plurality of segments and obtaining a segment state for each segment of the subset. Each segment state indicates whether the respective segment is accessible via a backing store. The method further includes determining a most restrictive state of the one or more segment states and sending state information to the client in response to the metadata request, the state information being derived from the most restrictive state.

Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; at least one actuator mechanism configured to position at least a first head proximate to a first disk surface and a second head proximate to a second disk surface; and one or more processing devices. The one or more processing devices are configured to: assign logical tracks to physical tracks of the disk surfaces such that a respective logical track comprises: at least a portion of sectors of a primary physical track, the primary physical track being on the first disk surface; and at least a portion of sectors of a donor physical track, the donor physical track being on the second disk surface. The one or more processing devices are configured to perform, using the first head and the second head, a data access operation with at least one of the logical tracks.

Abstract: A data transmission method and device for data transmission between an internal memory of a system-on-chip and an external memory coupled to the system-on-chip. The method is executed by a processor of the system-on-chip, including steps of: adding execution information of at least one data transmission task to be executed to a task queue; sending execution information of one data transmission task in the task queue to a direct access device for the direct access device to execute the data transmission task; and receiving an interrupt request sent by the direct access device, where the interrupt request is used to indicate completion of the execution of the data transmission task, so that the processor sends execution information of a next data transmission task to be executed in the task queue to the direct access device.

Abstract: Intelligent responses to errors in a storage system, including: after a first attempt to read data from a first set of resources in a storage system results in an error, determining whether to issue a second attempt to read data from the first set of resources in a storage system; responsive to determining not to issue the second attempt to read data from the first set of resources in a storage system, retrieving the data from a second set of resources in the storage system; and responsive to determining to issue the second attempt to read data from the first set of resources in a storage system, issuing a second read attempt to read the data, wherein the error correction effort level associated with the second attempt is increased relative to the error correction effort level associated with the first attempt.

Abstract: The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.

Abstract: The present disclosure describes methods and systems for reading data from a flash memory. A method can include receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request contains a logical address of the data. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage devices. The method also includes identifying an on-die SRAM storage of a flash memory die containing logical-to-physical (L2P) information and searching the L2P information to obtain a physical address of the data that corresponds to the logical address. The method further includes retrieving the data from a flash memory array of the flash memory die using the physical address.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

Abstract: A memory system is provided. The memory system includes a compare circuit and a control circuit. The compare circuit determines, in response to a number of detected error bits in a read data from a first memory array, whether a fail word address associated with the detected error bits is in an error table. The control circuit increments a counter value corresponding to the fail word address when the fail word address is in the error table, and further compares the counter value with a threshold value to replace memory locations, corresponding to the fail word address, in the first memory array with backup memory locations in a second memory array.

Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

Abstract: Provided is a monitoring apparatus comprising: a selection unit configured to select, among a plurality of state values corresponding to measurement values from a plurality of sensors for monitoring states of a plurality of facilities, a state value that has changed by an amount equal to or greater than a predetermined change width or change rate during a predetermined time length period; a sort unit configured to sort at least one state value selected, according to a change width or a change rate; and a display processing unit configured to perform processing to display an information screen corresponding to the at least one state value sorted.

Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

Abstract: Systems and methods are disclosed for processing and executing queries in a data intake and query system. The data intake and query system receives raw machine data at an indexing system, and stores at least a portion of the raw machine data in buckets. Based on a determination that the size of multiple buckets satisfies a threshold size, the data intake and query system converts the buckets to non-editable buckets and stores the data in a remote shared storage system.

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a main memory, a processor configured to generate commands for accessing data stored in the main memory, a scheduler configured to store the commands and output the commands according to a preset criterion, a cache memory configured to cache and store data accessed by the processor among the data stored in the main memory, and a hazard filter configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduler upon receiving the write command, and provide the write command to the main memory.

Abstract: Systems and processes are disclosed to preserve data integrity during a storage controller failure. In some examples, a storage controller of an active-active controller configuration can back-up data and corresponding cache elements to allow a surviving controller to construct a correct state of a failed controller's write cache. To accomplish this, the systems and processes can implement a relative time stamp for the cache elements that allow the backed-up data to be merged on a block-by-block basis.

Abstract: A specialized in-memory database health check process is utilized to resolve dependencies in a resource indicating requirements for an instance of an in-memory database. Specifically, when an instance of an in-memory database is created in response to a request, a list of one or more component handlers are obtained. These component handlers are modular functions, separate from each other but potentially dependent on one or more other component handlers, and act to validate various requirements listed in a resource for the request. Each of the component handlers are executed individually during execution of a Reconcile function. To the extent that the execution of any component handlers in the list is unsuccessful, the Reconcile function is rerun for another iteration. These iterations continue until all component handlers report back as successful. Instance creation is then considered successful and the instance of the in-memory database can be utilized by users.

Abstract: Provided herein may be a data storage device and a method of operating the same. The data storage device may include a memory device including a plurality of first data areas and a temporary data area, a buffer memory configured to temporarily store the data received from a host, and a memory controller configured to receive a first write request for writing the data and consecutive logical addresses from the host and write, upon occurrence of a trigger event that requires the data to be written to the memory device, the data to either the temporary data area or a first data area selected based on first data area information included in the first write request, depending on whether a size of the data is less than a preset reference size.

Abstract: A memory system may transfer a reference write size for a memory device to a host, and, when receiving, from the host, a write request for first data having a size corresponding to a multiple of the reference write size, may directly write the first data to the memory device without caching the first data in a write cache.

Abstract: Systems, devices, and methods for proportionally balancing power during wireless communication are provided. The disclosures provide for an integrated radio in which the functionality of an active radio and a passive radio are integrated into a single radio, with the active and passive radios each being configured to operate in three different modes: active, passive, and backscatter. Based on power and communication link information, the integrated rode is able to balance the modes at which the two radios are operated, thereby optimizing power consumption of the device into which the integrated radio is incorporated. The resulting systems, devices, and methods lead to ultra-low power consumption that enables these communication techniques to enhance computing devices from smartwatches to laptops. Devices incorporating the integrated radios, and methods for power-proportionally exchanging data, among other systems, devices, and methods, are also provided.

Abstract: Technologies are provided for supporting storage device write barriers. A host computer can be configured to transmit a write barrier command to a storage device to indicate that one or more data access commands should be processed before one or more other data access commands are processed. For example, a host computer can transmit one or more data access commands to a storage device. The host computer can then transmit a write barrier command to the storage device. The storage device can be configured to receive the write barrier command and to associate a write barrier with the one or more data access commands. The host computer can continue to transmit additional data access commands to the storage device. However, the storage device will not process the additional data access commands until after the one or more data access commands associated with the write barrier have been processed.

Abstract: A computer-implemented method, according to one approach, includes: initiating an I/O request using a primary cache, where the I/O request includes supplemental information pertaining to an anticipated workload of the I/O request. Performance characteristics experienced by the primary cache while satisfying the I/O request are also evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache. However, in response to determining to not satisfy a remainder of the I/O request using the secondary cache, a remainder of the I/O request is satisfied using the primary cache.

Abstract: Techniques are provided for data size based replication. In an example, a replication daemon registers to receive notifications about data changes from a protocol driver. The replication daemon can maintain a counter for each of one or more replication policies, where a counter tracks how much data has changed that corresponds to a replication policy, since the prior replication for that replication policy. Where the daemon receives a notification for the protocol driver, it can determine whether the notification applies to any replication policy, and update any counters accordingly. Where an amount of data changed since the prior replication exceeds a threshold for a replication policy, a replication can be started. Upon successful completion of the replication, the corresponding counter can be reset.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system may configure a plurality of map cache pools for caching map data of different types, respectively, within a map cache in which the map data is cached, configure a timer in a first map cache pool among the plurality of map cache pools, and write map data cached in the first map cache pool in the memory device based on the timer.

Abstract: A storage control device includes: an auxiliary cache memory that is a nonvolatile memory; a volatile memory; and a processor configured to execute a saving control process after a predetermined failure occurs, the saving control process being configured to (a) cause a writing control process to stop writing of data stored in the auxiliary cache memory to the storage medium, (b) secure, in the auxiliary cache memory, a storage region for storing the management information of the volatile memory, (c) generate a copy of management information of the volatile memory in the storage region, and (d) cause the writing control process to execute control to write first data stored in the volatile memory to the auxiliary cache memory or the storage medium based on the management information of the auxiliary cache memory.

Abstract: An information handling system may include a host system processor and a storage resource communicatively coupled to the host system processor. The storage resource may be configured to, responsive to receiving a command from the host system processor relating an address range of the storage resource, create an entry in a drive status table stored in a persistent storage area of the storage resource, the entry setting forth information indicative of the address and a completion status of the command and update a status of the address range in the drive status table as steps of the command are completed by the storage resource, such that, if a drive event occurs preventing full completion of the command, the host system processor may access the drive status table to determine a status of the command, and take a remedial action based on the status of the command.

Abstract: A method for determining check sums for a buffer memory for a processor, the method including a step of reading in a data unit of the buffer memory marked as changed by an access of the processor, a step of ascertaining a check sum for the data unit using a check sum unit of the buffer memory and a step of supplementing the data unit with the check sum and marking the data unit as changed with a valid check sum.

Abstract: In some examples, error recovery in volatile memory regions may include determining, during a save operation that includes saving of data to a primary location, that an error occurred with respect to the save operation. Based on a determination that the error occurred with respect to the save operation, an error location may be determined, and a determination may be made as to whether the error location maps to a volatile memory region. Based on a determination that the error location maps to the volatile memory region, a reserved location may be identified for saving the data. The data may be saved from the primary location to the reserved location. Further, metadata may be updated to indicate usage of the reserved location as the primary location for the saved data.

Abstract: A non-transitory computer-readable storage medium may include instructions that cause a system to perform operations, the operations may include receiving an operation associated with data and managing storage of the data on a first storage medium of an electronic device and in a cache on a second storage medium of the electronic device based on the operation and a cache policy. The cache policy may be based on one or more characteristics of the data that include a duration since a previous access of the data.

Abstract: A system, method and apparatus to provide data recovery capabilities during an emergency power failure event. A non-volatile storage system is provided to be coupled with a host computer system. The non-volatile storage system includes an embedded non-volatile memory array for persistently storing data and an embedded volatile memory array for temporarily storing the data before committing the data to the non-volatile memory array. The non-volatile storage system provides a normal operating data path transferring data from the volatile memory array to the non-volatile memory array during normal operating condition. The normal operating data path includes data processing blocks. The non-volatile storage system also provides an emergency data path for transferring data from the volatile memory array to the non-volatile memory array during an emergency power loss condition. The emergency data path excludes the data processing blocks.

Abstract: Techniques for storing data received by a data storage system involve performing inline compression on received data and storing resulting compressed data in segments of contiguous physical address space of a file system. Each segment spans multiple contiguous physical addresses and stores data of multiple contiguous logical addresses of a file. Each segment has an extent list that provides a location within that segment of the compressed data for each logical address.

Abstract: Embodiments disclosed herein provide systems and methods for performing video recorder failover. In a particular embodiment, a system for handing a failover of a first Network Video Recorder (NVR) is provided. The system includes a second NVR that receives a video stream and temporarily stores an amount of the video stream to the temporary storage, wherein the amount of the video stream stored in the temporary storage at any given time corresponds to a duration of time sufficient to accommodate a failover of the first NVR to the second NVR. In response to a detection of a failure of the first NVR, the second NVR records the video stream to the second long-term storage and transfers at least a portion of the video stream stored in the temporary storage to the second long-term storage.

Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.

Abstract: A system and method for storage and retrieval of pervasive and mobile content is provided. System may be comprised of a controller and a plurality of storage devices. Plurality of storage devices may include a first storage device located in a first geographic location and a second storage device located in a second geographic location. The controller may be operably connected to each storage device. The controller may also be capable of locating a first storage device containing data and transferring the data between the first storage device and a second storage device. The second storage device may be capable of transferring data to a host, which may be operably connected to the second storage device.

Abstract: A method is described for transmitting program codes to a program memory in a controller, particularly in a motor vehicle, having the following operations: a) connecting an interface in a controller to a programming appliance which contains the program codes, setting all the memory cells of the program memory in the controller to a standard value, compressing the program code in the programming appliance on the basis of a lossless data compression process, transmitting the compressed program code to the controller, decompressing the received program code in the controller, and storing the decompressed program code in the program memory in the controller.

Abstract: A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

Abstract: An apparatus and method to enable a fast cache shutdown is disclosed. In one embodiment, a cache subsystem includes a cache memory and a cache controller coupled to the cache memory. The cache controller is configured to, upon restoring power to the cache subsystem, inhibit writing of modified data exclusively into the cache memory.

Abstract: Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second processing unit are coupled to the main memory. The first processing unit includes a cache and logic. The cache is configured to store data from the main memory. The logic is configured to maintain an entry in a directory of the cache. The entry indicates whether either of the first processing unit and the second processing unit accesses a data object of a cache line for which the first processing unit is a home node.

Abstract: A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

Abstract: A method for protecting an operation sequence executed by a portable data carrier from spying out, wherein the data carrier has at least a processor core, a main memory and a cache memory with a plurality of cache lines. The processor core is able to access, upon executing the operation sequence, at least two data values, with the data values occupying at least one cache line in the cache memory and being respectively divided into several portions so that the occurrence of a cache miss or a cache hit is independent of which data value is accessed. A computer program product and a device have corresponding features. The invention serves to thwart attacks based on an evaluation of the cache accesses during the execution of the operation sequence.

Abstract: A cache memory unit includes: a cache memory; an early write-back condition checking unit for checking whether an early write-back condition has been satisfied; and an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus.

Abstract: A non-volatile memory system includes a memory section having a non-volatile cache portion storing data in a binary format, a primary user data storage section that stores user data in multi-state format, and an update memory area where the memory system stores data updating user data previously stored in the primary user data. The memory system allows a maximum number of blocks for use in the update memory area. When the memory system receives updated data corresponding to user data already written into the primary user data storage section, it determines whether a block of memory is available in the update memory area. In response to determining that a block of memory is not available in the update memory area, the system determines a block of the update memory to remove from the update memory; copies the data content of the determined update block into the cache portion of the memory section; and subsequently writes the updated data into the update memory.

Abstract: An input/output control system of an information processing apparatus that includes a first storage area and a second storage area and carries out an input/output processing using a part or whole of the first storage area as a cache.

Abstract: Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

Abstract: A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags. The memory controller also includes a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller. Input to the determining includes an upstream identification tag included in the received data packet. If the received data packet is determined to be in response to a request from the memory controller, then the received data packet is matched to the request, thereby allowing the memory controller to operate with indeterminate data response times.