Configuration Or Reconfiguration (epo) Patents (Class 711/E12.084)
  • Patent number: 9009440
    Abstract: A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage capacity of the storage system by changing the mapping to map more or less logical block addresses to space in the physical storage media and thereby destroy or create excess logical blocks, and by changing the unusable block data to correspondingly change the excess logical blocks marked as unusable.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Duncan Beadnell, Don Harwood
  • Patent number: 9009423
    Abstract: A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: April 14, 2015
    Assignee: NovaChips Canada Inc.
    Inventor: Roland Schuetz
  • Patent number: 9003101
    Abstract: A non-volatile storage subsystem is described which identifies performance-sensitive commands and heterogeneous performance characteristics of portions of a non-volatile storage media, and matches the performance sensitivity of the commands with an available physical write address corresponding to performance characteristics appropriate for the performance sensitivity of the command. A command can be considered performance sensitive if it originates from a host or a preferred host among a plurality of hosts, or if the command designates a frequently accessed logical address. Performance characteristics of the storage device can be determined by physical architectures of the storage media such as the distance from the axial center of a disk media, or the architecture technology of a solid-state array. Performance characteristics can also be determined dynamically and heterogeneous performance can be encouraged by internal maintenance policies of the subsystem.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert M. Fallone, William B. Boyle
  • Patent number: 9003156
    Abstract: The system utilizes a plurality of layers to provide a robust storage solution. One layer is the RAID engine that provides parity RAID protection, disk management and striping for the RAID sets. The second layer is called the virtualization layer and it separates the physical disks and storage capacity into virtual disks that minor the drives that a target system requires. A third layer is a LUN (logical unit number) layer that is disposed between the virtual disks and the host. By using this approach, the system can be used to represent any number, size, or capacity of disks that a host system requires while using any configuration of physical RAID storage.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Archion, Inc.
    Inventor: James A. Tucci
  • Patent number: 8996796
    Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Swamy Gowda
  • Patent number: 8990539
    Abstract: A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. Notably, the block allocation structures of a vvol are sized to the vvol, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the vvols. The file system layout extends the file system layout of a conventional write anywhere file layout system implementation, yet maintains performance properties of the conventional implementation.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: March 24, 2015
    Assignee: NetApp, Inc.
    Inventors: John K. Edwards, Blake H. Lewis, Robert M. English, Eric Hamilton, Peter F. Corbett
  • Patent number: 8990474
    Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 24, 2015
    Assignee: Altera Corporation
    Inventor: James L. Ball
  • Patent number: 8954705
    Abstract: A memory space management method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. In the memory space management method, a first area and a second area are configured. An authentication information is received from a host system, and whether the authentication information matches a predetermined authentication information is determined. If the authentication information does not match the predetermined authentication information, a counting value is updated. If the counting value matches a predetermined number, a first procedure is executed. In the first procedure, a third area is configured, wherein the capacity of the third area is a sum of the capacity of the first area and at least a portion of the capacity of the second area. The third area is provided to the host system to be accessed. Thereby, the memory space of the rewritable non-volatile memory module is effectively used.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Phison Electronics Corp.
    Inventor: Ching-Wen Chang
  • Patent number: 8949520
    Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: February 3, 2015
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton
  • Patent number: 8935505
    Abstract: A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: January 13, 2015
    Assignee: Round Rock Research, LLC
    Inventor: Douglas Alan Larson
  • Patent number: 8898418
    Abstract: A provisioning apparatus operable with a virtualisation layer in a server, for provisioning a storage volume associated with a physical storage device to a virtual server in a storage area network. The provisioning apparatus includes a discovery component for transmitting a request to the virtual server to identify one or more storage volumes, and a receiving component for receiving a first unique identifier associated with the or each located storage volume from the virtual server. A comparing component determines from configuration data associated with the or each located storage volume a second unique identifier associated with the each of the located storage volumes. A comparing component compares the or each first unique identifier received from the virtual server with the or each of the second unique identifier associated with the configuration data to find a matching identifier.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Stephen P. Strutt
  • Patent number: 8892843
    Abstract: A computational device receives a request to create a logical unit. In response to determining that adequate space is not available to create the logical unit in a first type of storage pool, a determination is made as to whether a first indicator is configured to allow borrowing of storage space from a second type of storage pool. In response to determining that the first indicator is configured to allow borrowing of storage space from the second type of storage pool, the logical unit is created in the second type of storage pool The logical unit is moved from the second type of storage pool to the first type of storage pool, in response to determining that free space that is adequate to store the logical unit has become available in the first type of storage pool.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jorge D. Acuna, Fahad Mahmood, Dhaval K. Shah
  • Patent number: 8880792
    Abstract: A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: November 4, 2014
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Arnold S. Weksler, Rod D. Waltermann, John Carl Mese, Nathan J. Peterson
  • Patent number: 8880841
    Abstract: Embodiments of the present invention provide an approach to forecast a potential demand for partitioned/sharded data and to distribute the data among a set of data partitions based on forecasted demand to optimize network characteristics (e.g., network bandwidth) and/or expedite data retrieval. For example, the data may be distributed among the partitions based on a quantity of trends/requests/hits on the data, so that requests for the data can be balanced among the partitions geographically.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ryan G. DeJana, Lisa Seacat DeLuca, Soobaek Jang, Daniel C. Krook
  • Patent number: 8874839
    Abstract: An electronic system, and a method and an apparatus for saving data of the electronic system are provided. The electrical system includes a central processing unit (CPU), a temperature sensor, a first controller, a second controller, a first storage device and a second storage device. When the CPU enters a suspend mode and the first controller detects a temperature of the electronic system to be lower than a threshold value through the temperature sensor, the second controller notify the application program to trigger the CPU to enter a hibernation mode, and operation data is moved from the first storage device to the second storage device.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 28, 2014
    Assignee: Getac Technology Corporation
    Inventor: Chia-Chang Chiu
  • Patent number: 8862821
    Abstract: A portable device includes n (n?2) electrical sockets, each of which is configured to accommodate and to electrically engage a removable external memory card; an input device for selecting accommodated and electrically engaged external memory cards for data reading; and an output device for outputting information that is derived from or related to data read from such selected electrically engaged external memory cards. The information may pertain to digital content of the selected external memory card, to the identity of the selected external memory card, or to the storage capacity of the selected external memory card.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 14, 2014
    Assignee: Sandisk IL Ltd.
    Inventor: Eitan Mardiks
  • Patent number: 8862840
    Abstract: A distributed storage management apparatus includes a monitoring unit configured to monitor a request pattern of each storage node of a plurality of storage nodes configured to distributively store data and at least one replica of the data; a group setting unit configured to receive a request and classify the plurality of storage nodes into a safe group and an unsafe group based on the monitored request pattern of each storage node; and a request transfer unit configured to transfer the received request to the safe group.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Pyung Lee
  • Patent number: 8856482
    Abstract: Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Terry M. Grunzke
  • Patent number: 8832369
    Abstract: Remote RAID system configuration may be implemented in an embedded and out-of-band manner using an information handling system configured, for example, as a RAID server. The remote RAID configuration may be implement, for example, on a RAID server system in the condition as it is supplied directly out-of-the-box to a user without requiring downloading of any additional software or firmware, without requiring presence of a management framework and plug in, and/or in a manner that is operating system (OS)-independent or that requires no OS to be present on the server. The RAID server may then be remotely reconfigured one or more times thereafter.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: September 9, 2014
    Assignee: Dell Products, LP
    Inventors: Weijia Zhang, Patrick O. Boyd, Vance E. Corn, William C. Edwards
  • Patent number: 8819377
    Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: August 26, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Patent number: 8799616
    Abstract: A method and system for binding a preferred CPU to a virtual partition of a computer is disclosed. In one embodiment, a preferred CPU for a virtual partition of a computer is determined upon a receipt of a request to assign a CPU to the virtual partition. Then, the preferred CPU is assigned to the virtual partition when the preferred CPU is available for assignment. Further, the preferred CPU is retained in the virtual partition when the virtual partition is rebooted.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 5, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Anjali Anant Kanak, Mohan Parthasarathy, Chandrashekhara Anandamurthy
  • Patent number: 8775760
    Abstract: A system operation method for controlling a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes a plurality of physical blocks. The system operation method includes following steps. A first signal is received from a host system through a host interface. Whether a system setting of the host interface is to be modified is determined. If the system setting is to be modified, a system parameter is read from the physical blocks, and the system setting is modified according to the system parameter. A second signal is transmitted to the host system to establish a connection recognition between the rewritable non-volatile memory module and the host system. Thereby, the settings of transmission between the host system and the rewritable non-volatile memory module are made more flexible.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Phison Electonics Corp.
    Inventor: Chien-Hua Chu
  • Patent number: 8769236
    Abstract: Oftentimes, computer files, information packets, and the like share identical data portions that cause duplicate storing. The files and/or packets can be logically divided and checks can be performed to determine if there are shared portions. If shared portions exist, then as opposed to making a duplicate copy of information, a pointer can be produced that identifies where the portion is saved. In addition, pointers can be used in compression of information such that a compressed file can identify an original copy—the original copy can be used to decompress the information.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: July 1, 2014
    Assignee: Microsoft Corporation
    Inventors: James R. Hamilton, Ruston Panabaker, John Mark Miller, William J. Westerinen
  • Patent number: 8762678
    Abstract: The system utilizes a plurality of layers to provide a robust storage solution. One layer is the RAID engine that provides parity RAID protection, disk management and striping for the RAID sets. The second layer is called the virtualization layer and it separates the physical disks and storage capacity into virtual disks that minor the drives that a target system requires. A third layer is a LUN (logical unit number) layer that is disposed between the virtual disks and the host. By using this approach, the system can be used to represent any number, size, or capacity of disks that a host system requires while using any configuration of physical RAID storage.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: June 24, 2014
    Assignee: Archion, Inc.
    Inventor: James A. Tucci
  • Patent number: 8756398
    Abstract: A method of partitioning a page of an electronic memory includes creating a first sub-page by interleaving a first user data section of the page with another section of a spare area of the page excluding a specified address in a section of the spare area that stores a bad block marker. The method also includes creating the sub-pages by interleaving the user data sections with sections of the spare area excluding the specified address until a last sub-page is to be created. Further, the method includes creating the last sub-page by interleaving a last user data section with the section of the spare area that includes the specified address in an interleaving sequence that retains the bad-block marker at the specified address.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 17, 2014
    Assignee: Synopsys Inc.
    Inventor: Gregor Uhlaender
  • Patent number: 8756382
    Abstract: The present invention relates to methods and systems for efficiently accessing data stored on a data storage device. The data storage device may comprise various types of media, such as shingled media and non-shingled media, alone or in combination. The data storage device may employ a logical block address space for specifying location of blocks of data stored on the data storage device. In addition, pre-determined sequential ranges of logical block addresses are grouped together and may be referenced collectively. In some embodiments, each type of media type may be partitioned into sections for containing different sizes of collections. Each collection of logical block addresses may be allocated to an arbitrary logical slot. Each logical slot may then be linked to a physical slot on the data storage device.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 17, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marcus A. Carlson, David C. Pruett
  • Patent number: 8756396
    Abstract: Systems, methods, and other embodiments associated with managing memory are described. According to one embodiment, an apparatus includes a converter that dynamically converts a structure of a data representation stored in a memory, where the structure is selectively converted between a sparse format and a non-sparse format.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: June 17, 2014
    Assignee: Toshiba Corporation
    Inventors: Arvind Pruthi, Shailesh Shiwalkar
  • Patent number: 8732424
    Abstract: A hybrid storage apparatus having a plurality of storage devices and a method of sharing resources therein. The hybrid storage apparatus can include a plurality of storage device controllers to respectively control a plurality of storage devices that employ different writing methods, a system controller to exchange information with the storage device controllers such that the plurality of storage devices are controlled in one system and in an integrated manner, a reset signal generation unit to output a reset signal that is in a first logic state via an output terminal when a power supply voltage used in the system is equal to or greater than a reference voltage, and a connection unit to electrically connect the output terminal of the reset signal generation unit to a reset signal input terminal of the system controller and to reset signal input terminals of the storage device controllers.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: May 20, 2014
    Assignee: Seagate Technology International
    Inventors: Ki-cheol Lee, Byung-wook Kim, Hwa-jun Kim
  • Patent number: 8713253
    Abstract: A modular storage system includes a modular storage system module, or “brick,” housing a disk drive array containing computer data. Each brick includes a backplane, fan(s) and a skin and has self-describing attributes that allow external control logic to auto-configure for each brick. The brick backplane includes a non-volatile memory device, such as a serial EEPROM, that can maintain and provide static and dynamic information regarding the brick and any disk drives in the disk drive array housed in the brick. The bricks can be attached to one or more base stations implementing and/or incorporating application-specific features and/or functions. Each base station also includes means for supplying power to the bricks and the disk drives contained in the bricks, RAID or other disk drive array control logic. Mounting apparatus ensures that a brick mounted to a base station, is immobilized, thus protecting the brick and electrical connection between the brick and the base station.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 29, 2014
    Assignee: Guidance-Tableau, LLC
    Inventor: Robert C. Botchek
  • Patent number: 8683161
    Abstract: A mass storage device and method that utilize storage memory and a shadow memory capable of increasing the speed associated with copying data from one location to another location within the storage memory without the need to access a host computer for the copy transaction. A controller of the mass storage device receives a file copy request for a file to be copied between first and second locations within the storage memory. Data from the first location within the storage memory is then loaded into a shadow memory means of the mass storage device, and then the data is written from the shadow memory means to the second location within the storage memory.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: March 25, 2014
    Inventor: Franz Michael Schuette
  • Patent number: 8683171
    Abstract: A storage system connected to a computer and a management computer, includes storage devices accessed by the computer, and a control unit for controlling the storage devices. A first-type logical device corresponding to a storage area set in at least one of the storage devices and a second-type logical device that is a virtual storage area are provided. The control unit sets at least two of the first-type logical devices different in a characteristic as storage areas included in a storage pool through mapping. The first-type logical device stores data by allocating a storage area of the second-type logical device to a storage area of the first-type logical device mapped to the storage pool. The characteristic of the second-type logical device can be changed by changing the allocated storage area of the second-type logical device to a storage area of another first-type logical device.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: March 25, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Yoshiaki Eguchi
  • Publication number: 20140068219
    Abstract: A mechanism is provided for optimizing free space collection in a storage system having a plurality of segments. A collection score value is calculated for least one of the plurality of segments. The collection score value is calculated by determining a sum, across tracks in the segment, of the amount of time over a predetermined period of time during which the track has been invalid due to a more recent copy being written in a different segment. Segments are chosen for free space collection based on the determined collection score value.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Bruce McNutt
  • Publication number: 20140068139
    Abstract: A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Patent number: 8667244
    Abstract: In one implementation, a data set including a plurality of data values having an order is stored at a memory having a plurality of memory locations. Each data value from the data set stored a current memory location of that data value from the plurality of memory locations. Each data value from the data set is periodically moved from the current memory location of that data value from the plurality of memory locations to a next memory location of that data value from the plurality of memory locations. The next memory location of each data value from the plurality of memory locations is the current memory location of that data value from the plurality of memory locations after the moving. The plurality of data values is then provided in the order to a client in response to a request for the data set.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ted A Hadley, Susan K Langford
  • Patent number: 8661224
    Abstract: A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver. The memory management module determines a main memory configuration for at least some of the plurality of memory modules. The memory management module also determines physical addresses for the main memory configuration and determines a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmadreza Rofougaran, Timothy W. Markison
  • Publication number: 20140052953
    Abstract: A storage system and a method for managing a memory capable of storing metadata related to logical volume sets, are disclosed. A memory quota is assigned to a metadata related to a logical volume set. The size of a memory currently consumed by the metadata is monitored. Upon exceeding a threshold by the size of the monitored memory, at least one restraining action related to memory consumption by the metadata is applied.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Applicant: INFINIDAT LTD.
    Inventors: Ido BEN-TSION, Efraim ZEIDNER
  • Patent number: 8650378
    Abstract: A determination is made as to whether a first indicator is configured to allow borrowing of storage space to a first type of storage pool from a second type of storage pool. In response to determining that the first indicator is configured to allow borrowing of storage space from the second type of storage pool, a logical unit is created in the second type of storage pool and a listener application is initiated. The listener application determines that free space that is adequate to store the logical unit has become available in the first type of storage pool. The logical unit is moved from the second type of storage pool to the first type of storage pool, in response to determining, via the listener application, that free space that is adequate to store the logical unit has become available in the first type of storage pool.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jorge D. Acuna, Fahad Mahmood, Dhaval K. Shah
  • Patent number: 8639906
    Abstract: A determination is made as to whether a first indicator is configured to allow borrowing of storage space to a first type of storage pool from a second type of storage pool. In response to determining that the first indicator is configured to allow borrowing of storage space from the second type of storage pool, a logical unit is created in the second type of storage pool and a listener application is initiated. The listener application determines that free space that is adequate to store the logical unit has become available in the first type of storage pool. The logical unit is moved from the second type of storage pool to the first type of storage pool, in response to determining, via the listener application, that free space that is adequate to store the logical unit has become available in the first type of storage pool.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jorge D. Acuna, Fahad Mahmood, Dhaval K. Shah
  • Publication number: 20130346724
    Abstract: A region of memory is logically divided into a number of segments, each of which is logically divided into a number of blocks. Blocks are allocated sequentially. A head pointer and a tail pointer demarcate the section of allocated blocks. As allocated blocks are added, the tail pointer is moved so that it remains at the end of the section of allocated blocks. If the tail pointer is within a threshold distance of the head pointer, then the head pointer is moved from its current position to a new position, and the allocated blocks between the current and new positions are freed (deallocated and/or erased). Thus, writes to the memory can be performed sequentially, and blocks can be freed in advance of when they are actually needed.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: SYMANTEC CORPORATION
    Inventors: Dilip Madhusudan Ranade, Niranjan Pendharkar, Anindya Banerjee
  • Publication number: 20130339605
    Abstract: A computerized method of collaborating storage space across multiple devices according to file usage patterns of the devices. The method comprises receiving access to a plurality of storage media each having a storage space and managed by at least one of a plurality of devices, identifying for each of the plurality of devices at least one usage pattern of at least one of a plurality of file types, creating a virtually contiguous storage pool mapping physical memory addresses of the plurality of storage media, setting a file distribution policy of storing each of a plurality of data files stored in the plurality of storage media in the virtually contiguous storage pool according to a match between a file type and at least one usage pattern, and collaborating storage space across the plurality of storage media managed by the plurality of devices according to the file distribution policy.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Factor, Boaz Mizrachi, Gal Shachor
  • Patent number: 8612712
    Abstract: A daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. By predicting command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM is programmable to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: December 17, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Douglas Alan Larson
  • Patent number: 8601228
    Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with the type of access. Accordingly, when an application with specific memory access needs is initiated, the memory access profile that is most optimized for that particular access need is utilized to configure access to the memory device. The configuration may be effected for a portion of the memory device, a partition of the memory device, or even one single access location on the memory device.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: December 3, 2013
    Assignee: Memory Technologies, LLC
    Inventors: Jani Hyvonen, Kimmo J. Mylly, Jussi Hakkinen, Yevgen Gyl
  • Patent number: 8583892
    Abstract: A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. Notably, the block allocation structures of a vvol are sized to the vvol, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the vvols.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: November 12, 2013
    Assignee: NetApp, Inc.
    Inventors: John K. Edwards, Blake H. Lewis, Robert M. English, Eric Hamilton, Peter F. Corbett
  • Patent number: 8572336
    Abstract: A storage control apparatus of the present invention is able to duplicatively manage data in a cache memory even during maintenance work. When a memory package CMPK3 specified by a user is removed from the apparatus 1 (S2), a microprocessor 2 changes a pair that has been configured using CMPK2 and CMPK3 to a pair of CMPK2 and a free area of a CMPK1. As a result, received data (S5) is respectively written to multiple cache memories (S6, S7), and duplicatively managed.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: October 29, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Fujii, Sumihiro Miura
  • Patent number: 8560762
    Abstract: Storage devices can retain information through application of a charge upon the storage device. However, applying the charge upon the storage device can be change physical characteristics of the charge and ultimately increase a likelihood of device failure. Therefore, a determination can be made on how to apply the charge based upon analysis of the device, of data for retention, and the like. Raw data can be analyzed and/or estimations can be made to determine the charge.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 15, 2013
    Assignee: Microsoft Corporation
    Inventors: Ruston Panabaker, Robert Patrick Fitzgerald, William J. Westerinen
  • Patent number: 8560799
    Abstract: Multiple types of storage devices which have different performance are appropriately allocated to multiple virtual volumes in accordance with the performance requirements of the respective virtual volumes. In cases where, among virtual volumes 82 for which response times have been specified, there is a [virtual volume] that has a shortage of pages to which SSDs 70 should be allocated and that does not satisfy the performance requirement when its Tier boundary value ? is adjusted to Tier boundary value ?? and, if unallocated pages as the pages to which SSDs 70 should be allocated do not exist, Tier boundary value ? or Tier boundary value ? of another virtual volume is adjusted to Tier boundary value ?? or the Tier boundary value ??, and pages to which SSDs 70 are allocated are secured in the virtual volume 82 for which the Tier boundary value has been adjusted.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: October 15, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Nasu, Hirokazu Ikeda, Yoshiaki Eguchi, Toshimichi Kishimoto
  • Patent number: 8554998
    Abstract: Systems, methods, and computer readable media for managing digital media in a memory storage device associated with a mobile smart device are disclosed. According to one aspect, the subject matter described herein includes a method for configuring a rewriteable non-volatile memory for presentation of media by a selected media presentation device model. The method includes providing a rewriteable non-volatile memory configuration interface through which a user can select at least one media file and one of a plurality of media presentation device models.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: October 8, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Adam Jeffrey Mashaal, Hagai Heshes, Yaron Sheba, Michael Scott McMurdie, Gregory Louis Stevens, John Anthony Becker, Erez Zvi Testiler, David Domenick Marini
  • Patent number: 8555006
    Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Jeddeloh, Ralph James
  • Publication number: 20130262811
    Abstract: Exemplary embodiments provide high-speed memory devices such as high-speed DRAM resources in a storage system for external computers. In accordance with an aspect of the invention, a computer system comprises: a computer which includes an internal memory and an external memory, the external memory being provided by a storage system coupled to the computer; and a controller operable to manage a virtual memory space provided by the internal memory and the external memory. The controller is operable to add a logical unit provided by the storage system, to the external memory included in the virtual memory space, based on a usage level of the virtual memory space. The controller is operable to release a logical unit provided by the storage system, from the external memory included in the virtual memory space, based on the usage level of the virtual memory space.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: HITACHI, LTD.
    Inventor: Yuichi TAGUCHI
  • Patent number: 8549250
    Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) having associated device type information is serially interconnected. A serial input (SI) containing a device type (DT) and a device identifier (ID) is fed to one device of the serial interconnection. Upon a match between the fed DT matches the DT of the device, the fed ID is latched in a register of the device and an ID for another device is generated, which is then transferred to the next device in the serial interconnection. Otherwise, ID generation is skipped. These steps are performed in all devices. Thus, sequential IDs are generated for the different device types and also the total number of each device type is recognized. If the fed DT is “don't care”, sequential IDs are generated for all devices and the total number of the devices is recognized.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 1, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventors: Hong Beom Pyeon, HakJune Oh, Jin-Ki Kim