Abstract: A stream computer comprises a plurality of interconnected functional units. The functional units are responsive to a data- stream containing data and tokens. The data is to be operated on by one or more of the plurality of interconnected functional units.

Abstract: A method and apparatus for eliminating memory contention in a computation module is presented. The method includes, for a current operation being performed by a computation engine of the computation model, processing that begins by identifying one of a plurality of threads for which the current operation is being performed. The plurality of threads constitutes an application (e.g., geometric primitive applications, video graphic applications, drawing applications, etc.). The processing continues by identifying an operation code from a set of operation codes corresponding to the one of the plurality of threads. As such, the thread that has been identified for the current operation, one of its operation codes is being identified for the current operation. The processing then continues by determining a particular location of a particular one of a plurality of data flow memory devices based on the particular thread and the particular operation code for storing the result of the current operation.

Abstract: An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Abstract: A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.

Abstract: A method for generating an asynchronous controller includes a process controller formation step S100 of forming a signal transition graph representing a state of change in input/output signals of a plurality of process controllers PC1˜PC4 for outputting control signals necessary for executing a process corresponding to a node in a data flow graph showing a performance sequence between a plurality of nodes each representing a process and a plurality of processes, a process sequencing controller formation step S400 of forming a signal transition graph of a process sequencing controller PSC according to a performance sequence of the process controllers PC1˜PC4 from the data flow graph, and a logic synthesis step S500 of generating an asynchronous controller in a logic synthesis program, by using the state of change in the input/output signals on the signal transition graph of the process controllers PC1˜PC4 formed in the process controller formation step S100 and the state of change in the inpu

Abstract: A method and apparatus for the data-driven synchronous parallel processing of digital data, which temporally separates the processes of instructions distributions and data requests from the process of actual data processing. The method includes the steps of: dividing the stream of digital data into data packets, consecutively distributing instructions to data processing units before their execution, consecutively synchronously processing data packets by multiple data processing units processing in parallel, and synchronization of parallel multiple data processing units by data tokens attached to the data packets.

Abstract: A data driven information processor circulates a data packet therein, while in accordance with a previously prepared data flow program the processor performs a plurality of types of operation including performing an arithmetic operation on data and accumulating a result of the arithmetic operation in an accumulation operation performed repeatedly. The accumulation operation is performed in the information processor only at a product-sum operation portion. While the operation is being performed, a data packet having stored therein data to be accumulated is not required to circulate round a loop formed of other components of the information processor. The accumulation operation can thus be performed fast.

Abstract: The data driven type information processing system has a branch unit and a junction unit in the input and output stages thereof, and includes a plurality of data driven type processors between the branch unit and the junction unit. The branch unit, the junction unit and the plurality of data driven type processors are coupled to one another via transmission paths. Each of the data driven type processors can process a unique instruction system. The junction unit collects data packets provided via the transmission paths and outputs the collected data packets to the outside of the system. In operation, when a data packet is provided to the system, the branch unit receives the data packet provided thereto and, according to an instruction code within the received data packet, selects a transmission path connected to a data driven type processor that can process an instruction system corresponding to the instruction code, and sends out the received data packet to the selected transmission path.

Abstract: A system and method of optimizing transmission of a program to multiple users over a distribution system, with particular application to video-on-demand for a CATV network. The system includes, at a head end of the CATV network a scheduling and routing computer for dividing the video program stored in long term fast storage or short term fast storage into a plurality of program segments, and a subscriber distribution node for transmitting the program segments in a redundant sequence in accordance with a scheduling algorithm. At a receiver of the CATV network there is provided a buffer memory for storing the transmitted video program segments for subsequent playback whereby, in use, the scheduling algorithm can ensure that a user's receiver will receive all of the program segments in a manner that will enable continuous playback in real time of the program.

Abstract: An initial value of read address is set in a first initial address register; an initial value of write address is set in a second initial address register; and the number of data to be accumulated by an accumulator and the frequency of repetition of accumulation are set in an accumulator count register. A controller controls the timing of output of an initial read address from a first memory controller, the timing of initialization by an initializer, and the timing of output of an initial write address from a second memory controller. Reading of data, accumulation and writing of data proceed in parallel in each cycle of accumulation.

Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for pipelining of data between the two clock domains. Plural synchronizer stages each include a data register (601, 602, 603, 604, 605) and a synchronizer circuit (611, 612, 613, 614, 615). The synchronizer circuit synchronizes a first domain write request signal to the second clock signal. A write pointer (625) enables one synchronizer stage to write first domain data upon receipt of said first domain write request signal (321). The write pointer thereafter increments to indicate a next synchronizer stage in a circular sequence. A read pointer (635) enables an indicated read stage to recall data from the corresponding data register upon output synchronization with the second clock signal. The read pointer thereafter increments to indicate the next synchronizer stage in the circular sequence.

Abstract: An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Abstract: A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the pipeline operation device, a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit are arranged. To perform an operation while an operation result of each of the pipeline units is being written into the register, translating an instruction to the pipeline operation unit is interlocked when the writing of the operation result of the pipeline operation unit overlaps with the writing of the operation result of the non-pipeline operation unit.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool displays an interface that enables the programmer to define a region divided into multiple blocks, wherein each block is formed of a set of values associated with a function, and to define sets of the blocks, each block in a set having a state reflected by a designated portion of the program that when executed transforms the values forming the block based on the function. The interface also records any dependencies among the blocks, each dependency indicating a relationship between two blocks and requiring the portion of the program associated with a first block of the relationship to be executed before the portion of the program associated with a second block of the relationship.

Abstract: The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.

Abstract: A packet generation unit 17 divides a plurality of generated clocks to generate clocks with different frequencies, selects any of the frequencies, sets destination information and data depending on a selected clock rate and generates a data packet that stores the setting result. An input/output control unit 11 taken the data packet generated by the packet generation unit 17 and sends it to a program storage unit 12 or a data memory interface unit 15 according to the destination information. As a result, information can be internally processed in a predetermined frequency without depending on an outside clock. When the outside clock is slow, information can be internally processed in a higher-rate frequency. On the contrary, when the outside clock is too fast to internally process information, information can be internally processed in a lower-rate frequency to secure a processing time.

Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

Abstract: An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the information is described. The method includes identifying lines of data to be written, determining a unique start code to be used for that data, and embedding that start code into that data. When the proper number of lines of data have arrived in peripheral device memory, the pending operation is executed.

Abstract: An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the number of inputs of an instruction; a waiting data storage region that stores N(N≧2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of the packet as the address; a unit that calculates the address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instruction inputs; and a unit that performs the waiting process in response to the select signal.

Abstract: A method and apparatus for manipulating data from a processor on a stack memory is disclosed. The method and apparatus comprises aligning a stack pointer (104) in the stack memory (110) to a first memory address (126). The method further comprises incrementing the stack pointer (104) to a second memory address (128). The method further comprises saving data from a register (102) into the stack memory (110) at the second memory address (128). The method further comprises aligning the stack pointer (104) to a next even address if at an odd address when the saving step is complete. The method further comprises performing processor operations. The method further comprises unaligning the stack pointer (104) from the even address back to the odd address. The method further comprises restoring data from the stack memory (110) into the register (102). The method further comprises decrementing the stack pointer (104) from the second memory address (128) to the first memory address (126).

Abstract: A system in which a personal computer sends messages into a TCP/IP network using a conventional dial-up link and downloads data from the TCP/IP network using a high-speed one-way satellite link. A preferred embodiment uses a conventional SLIP provider to connect to the TCP/IP network and uses a commercial software TCP/IP package that has a standard driver interface. A spoofing protocol compensates for the long propagation delays inherent to satellite communication.

Abstract: When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by dividing the multiple-precision data by every 32 bits in accordance with the memory word length of an accumulation memory, and a group of 32 memory words each having 32 bits of the accumulation memory is treated as the multiple-precision data. Accordingly, in the data-driven processor, a usual memory region can serve as an accumulator for multiple-precision data without having to provide any accumulator dedicated to multiple-precision data in the data-driven processor. In addition, since the multiple-precision data is divided into independent single-precision data each having 32 bits, operations for all data can be performed concurrently. Thus, a parallel processing capability of the data-driven processor can be maximized.

Abstract: A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the “H” level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.

Abstract: In a data driven information processor, an operation apparatus includes a data select unit and a flag select unit selecting information according to the value of flag data in an input data packet. The data select unit selects the processed result for each data in the input data packet or the data itself. The flag select unit selects the flag data set with a value according to the processed result or the flag data of the input data packet. The selected information is stored in the input data packet, which is output to a program storage unit. Accordingly, the processed result can be obtained for certain data selected out of a plurality of data in the data packet to be reflected in the subsequent operation process without dividing the data packets.

Abstract: The invention relates to computer science, in particular, to computer systems using data flow control over computations and to the further inclusion of processing means utilizing the von Neumann principle of computation resulting in an improvement of performance and a decrease in the volume (size) of associative memory.

Abstract: A data processing system and method of monitoring the performance of a data processing system in processing data requests, where said data processing system processes data requests within a multilevel memory hierarchy. At least one token is passed with a data request along a particular path within the multilevel memory hierarchy. The time duration for the token to completely pass along the particular path is stored if expected conditions are encountered along the particular path within the multilevel memory hierarchy, such that the performance of said data processing system requesting data along that particular path under the expected conditions is determined and is available for subsequent performance monitoring.

Abstract: An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.

Abstract: The invention relates to computer science, in particular, to a computer system comprising a processor, an input-output switch, an instruction loading switch, instruction memory, and a data access unit which uses the dataflow principle of computation. Performance is increased by decreasing the volume of associative memory by means of the introduction of the use of a fragment routine processor to process segments of the program which are better processed by von Neumann principles of computation.

Abstract: A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes and that execute a long type register branch instruction are provided. Thus, a register branch instruction can be executed with three instructions rather than five instructions unlike with a related art reference.

Abstract: The compilation of source code to a primary and a secondary processor. The method relates to reconfigurable secondary processors, and is especially relevant to secondary processors which can be reconfigured to some degree during execution of code. Selective extraction of dataflows from the source code is followed by transformation of the extracted dataflows into trees. The trees are then matched against each other to determine minimum edit cost relationships for transformation of one tree into another, where these minimum edit cost relationships are determined by the architecture of the secondary processor. A group or a plurality of groups of dataflows is determined on the basis of said minimum edit cost relationships and for each group a generic dataflow capable of supporting each dataflow in that group is created.

Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: The present invention provides an efficient streamlined pipeline for a counterflow pipeline processor with a renaming table. The counterflow pipeline includes an execution pipe having multiple instruction stages forming an instruction pipe, a plurality of result stages forming a result pipe, and a corresponding plurality of comparator/inserters. Each comparator/inserter couples an instruction stage to a corresponding result stages. The counterflow pipeline also includes a register exam stage with the renaming table. The renaming table has entries for associating each register value of an instruction with a unique renamed register number (RRN), thereby eliminating the need for arbitration and housekeeping (killing of stale register values), as instructions and their respective register values counterflow in the streamlined counterflow pipeline. An RRN counter, such as a modulo counter, is coupled to the renaming table and provides unique RRNs for assignment to new register values.

Abstract: An asynchronous stack apparatus and method is provided that reduces power consumption that maintains a constant response time regardless of the number of stored items. The asynchronous stack apparatus uses a token and control circuits to indicate a current tope of stack and process data input/output. The asynchronous stack apparatus includes a communication device, a plurality of storage units and a token control circuit.

Abstract: A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1) Adjacent stages are also connected via a validation line (IN.sub.-- VALID, OUT.sub.-- VALID) and an acceptance line (IN.sub.-- ACCEPT, OUT.sub.-- ACCEPT), and in some embodiments also via an extension bit line (IN.sub.-- EXTN, OUT.sub.-- EXTN). Input data is transferred from any stage to the following device on every complete period of both clock signals only if both the validation and acceptance signals in the respective latch are in an affirmative state, whereby data is transferred between stages regardless of the state of the validation and acceptance signals in other stages. A two-wire interface is thus formed between the stages.

Abstract: A method and apparatus for handling outgoing communication requests in an information handling system in which outgoing communication packets are accumulated into a block that is written to an input/output (I/O) device. For each I/O device there is generated a blocking factor representing a predetermined number of packets that are accumulated before the block is written to the I/O device, as well as a push interval representing a maximum period of time for which any packet in the block can be stalled. Upon the arrival of a new outgoing packet, the packet is added to the block, and the block is written to the I/O device if either the block now contains the predetermined packets or any packet in the packet has been waiting for more than the push interval. A timer running asynchronously with the arrival of outgoing requests periodically pops to write the block to the I/O device if it has been waiting overlong, even if no new requests have arrived.

Abstract: A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The functional blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplexer logic. The data dependency logic receives address signals for a group of instructions and passes dependency information output to the tag assignment logic. The tag assignment logic provides tag information output to the register file port multiplexer logic. The tag assignment logic is arranged on opposite sides of a center channel, so that the tag information output is laid-out in the center channel and is fed directly to the register file port multiplexer logic in a substantially straight path. The register file port multiplexer logic directs the tag information output to a register file address port of a register file.

Abstract: A counterflow pipeline is provided which includes an instruction pipeline having a plurality of stages for transmitting instruction packets in a first direction and a result pipeline having a plurality of stages for transmitting result packets in a second direction opposite the first direction. Each of the result pipeline stages corresponds to an instruction pipeline stage, the associated instruction and result pipeline stages being part of a counterflow pipeline stage. Arbitration logic coupled between the instruction and result pipelines facilitates the movement of instruction and result packets in the stages of the instruction pipeline and result pipeline, respectively, using a four-phase level signaling protocol. The arbitration logic prevents instruction and result packets from passing each other in their respective pipelines by inhibiting them from being simultaneously released from adjacent counterflow pipeline stages. Thus, any necessary interaction between the two data packets may take place.

Abstract: An instruction accelerator which includes a processor and an associative memory. The processor is coupled to receive a stream of instructions and a corresponding stream of instruction identifier values. The instructions include at least one non-quick instruction which has a first associated data set which must be accessed prior to executing the non-quick instruction. A memory, which is coupled to the processor, stores one or more instruction identifier values and one or more associated data sets. The memory receives the stream of instruction identifier values. When a current instruction identifier value in the stream of instruction identifier values matches an instruction identifier value stored in the memory, an associated data set is accessed from the memory.

Abstract: A control apparatus and method is provided for controlling operations of functional units in systems. The control apparatus and method implement a set of operations that can include dependencies between the functional units of a system to complete each operation. For example, in an asynchronous digital processor, self-timing and inter-block communication are used to implement a self-timed scheduler. The self-timed scheduler and method implement an instruction set using a plurality of functional units of the asynchronous digital processor. A scheduler can include a scheduler decoder that decodes each instruction to generate functional unit schedule and control information, a communication device and a plurality of scheduler functional unit controllers, wherein each of the scheduler functional unit controllers corresponds to one of the plurality of functional units of a system.

Abstract: A programmable circuit and method for a data processing apparatus is provided that allows an entire instruction or instruction set to be modified. According to the present invention, the instruction can be modified, for example, during initialization or execution. The programmable circuit for a data processing apparatus can include a plurality of functional units, each functional unit performing a set of prescribed operations. A programmable circuit that is capable of modifying an entire instruction. A controller that decodes a current instruction to perform a corresponding instruction task using the plurality of functional units and a communications device coupling the functional units, the programmable circuit and the controller.

Abstract: IEEE compliant floating point unit mechanism allows variability in the execution of floating point operations according to the IEEE 754 standard and allowing variability of the standard to co-exist in hardware or in the combination of hardware and millicode. The FPU has a detector of special conditions which dynamically detects an event that the hardware execution of an IEEE compliant Binary Floating Point instruction will require millicode emulation. The complete set of events which millicode may emulate are predetermined early in the design process of the hardware. An exception handling unit assist millicode emulation by trapping the result of an exceptional condition without invoking the trap handler. When an exceptional condition is detected during execution, the IEEE 754 standard requires two different actions under control of a mask bit. If the mask bit is on, the result is written into an FPR and the trap handler is invoked.

Abstract: An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

Abstract: A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.

Abstract: The relationships among predicates are tracked globally by uniformly treating both control flow and explicit predicates by mapping them to a single connected partition graph. This allows for the analysis of predicate relations based on the scope of an entire procedure. This predicate analysis can be invoked by various phases of compiler optimization without being constrained by an incremental update of any persistent data structures.

Abstract: A method for processing user-input that may include a command to abort a previously requested operation and typed-ahead data entered in anticipation of completion of the previously requested operation is disclosed. The user-input is represented by a value queued in a first queue by an operating system. According to the present invention, the value is removed from the first queue and examined to determine if it represents a command to abort the previously requested operation. If the value represents a command to abort the previously requested operation, the previously requested operation is aborted. If the value does not represent a command to abort the previously requested operation, the value is queued in a second queue, and, after completion of the previously requested operation, the value is removed from the second queue and associated with a display window to which user-input is focused at that time.