Decoding Instruction To Accommodate Variable Length Instruction Or Operand Patents (Class 712/210)
  • Patent number: 7373483
    Abstract: An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies register address extensions, the register address extensions indicating the extended registers, where the extended registers cannot be specified by an existing instruction set, and where the existing instruction set includes the x86 instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set, and where the extended prefix tag includes opcode F1 (ICE BKPT) in the x86 instruction set. The extended register logic is coupled to the translation logic.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 13, 2008
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7366876
    Abstract: In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: April 29, 2008
    Assignee: Analog Devices, Inc.
    Inventors: Charles P. Roth, Ravi P Singh, Gregory A. Overkamp, Tien Dinh
  • Patent number: 7360061
    Abstract: A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12. The instruction decompression circuit decompresses compressed instruction data CID recovered from the compressed instruction data memory and forms program instructions which are supplied to the instruction cache. The program instructions are compressed in blocks of program instructions with an associated mask value where the bit values within the mask indicate whether corresponding bit slices within the blocks of program instructions are to be represented by a default bit value or a separately specified by bit slice specifier values. This technique is particularly well suited to VLIW processors.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: April 15, 2008
    Assignee: ARM Limited
    Inventors: Vladimir Vasekin, Andrew Christopher Rose
  • Patent number: 7353368
    Abstract: A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Michael Chow, Elango Ganesan, John William Phillips, Nazar Abbas Zaidi
  • Publication number: 20080077773
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 27, 2008
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • Publication number: 20080072016
    Abstract: A method for processing a variable length code comprising: determining a first address; decoding opcodes from the at least one table starting at a first address; in response to each of the opcodes: receiving a portion of a sequence of bits, the sequence of bits comprising a first variable length code; receiving S from the second table at the current address; flushing S bits in the sequence of bits; receiving T corresponding to one of the stages; determining a value of a set of T bits in the sequence of bits; receiving D from the second table at the current address; and computing the next address, the next address being the sum of the current address, D, and the value of the set of T bits; and retrieving the next opcode, the next opcode being retrieved from the next address; and determining the decoded syntax element.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 20, 2008
    Applicant: NEMOCHIPS, INC.
    Inventor: Danian GONG
  • Patent number: 7343473
    Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: March 11, 2008
    Assignee: Transmeta Corporation
    Inventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
  • Patent number: 7343471
    Abstract: Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit (42) includes a decompression section (44) and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer (52) identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit (46) fetches an instruction to be executed from the position identified by the cache pointer.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: March 11, 2008
    Assignee: PTS Corporation
    Inventor: Nigel Peter Topham
  • Patent number: 7340590
    Abstract: The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer instruction and a lesser width consumer instruction, a greater width source register is substituted for the source register specified by the lesser width producer. If there is a register dependency between a lesser width producer instruction and a greater width producer instruction, the greater width consumer instruction is replaced by multiple helper instructions. One or more of the helper instructions merge lesser width registers aliased onto the source registers specified by the greater width consumer instruction, into temporary registers. Another helper instruction executes the greater width consumer instruction using the temporary registers instead of the original source registers.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: March 4, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Rabin Sugumar, Sorin Iacobovici, Chandra M. R. Thimmannagari
  • Patent number: 7340588
    Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Erik R Altman, Michael Gschwind, David A. Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman
  • Patent number: 7337302
    Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: February 26, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Sugako Ohtani, Hiroyuki Kondo
  • Patent number: 7328328
    Abstract: An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: February 5, 2008
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7305542
    Abstract: Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventor: Venkateswara Rao Madduri
  • Patent number: 7301541
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: November 27, 2007
    Assignee: Microunity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 7290120
    Abstract: A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor based on the inventive architecture has a power-saving fetch and decoding unit for fetching and decoding program instructions. The fetch and decoding unit has a program instruction memory which receives a sequential program instruction address addressing the next program instruction memory line which is to be read, having at least one program instruction memory line which can store an indicator flag, a long program instruction index, a short program instruction and a first source register address. A directory memory receives the long program instruction index (6) addressing the next directory memory line which is to be read.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: October 30, 2007
    Assignee: Infineon Technologies AG
    Inventor: Lorenzo DiGregorio
  • Patent number: 7290153
    Abstract: Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a present instruction, and at least one subset instruction decoder configured to determine whether the present instruction potentially needs a register. A memory element is also included and is configured to hold data from a previous instruction. A selector is included and configured to output either the previous instruction or the decoded present instruction, based on the subset instruction decoder.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: October 30, 2007
    Assignee: VIA Technologies, Inc.
    Inventor: Richard Duncan
  • Patent number: 7284115
    Abstract: A processor supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden to 64 bits for instructions having an implicit stack pointer reference and for near branch instructions. The overriding of the default operand size may occur without requiring an operand size override encoding in these instructions. In one embodiment, the instruction set specifying the instructions may be a variable byte length instruction set (e.g. x86), and the operand size override encoding may be a prefix byte which increases the instruction length.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: October 16, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Kevin J. McGrath
  • Patent number: 7263621
    Abstract: The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word length select for indicating a present instruction's word length, and a first selector for routing the instruction into the 16-bit decoder when the present instruction is 16-bits long. The first selector is also configured to route a previous instruction into the 16-bit decoder, maintaining the 16-bit decoder's present state. A second selector is configured to route the instruction into the 32-bit decoder when the present instruction is 32-bits long. The second selector is also configured to route a past instruction into the 32-bit decoder to maintain the 32-bit decoder's present state.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: August 28, 2007
    Assignee: VIA Technologies, Inc.
    Inventor: Richard Duncan
  • Patent number: 7254696
    Abstract: A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 7, 2007
    Assignee: Alacritech, Inc.
    Inventors: Millind Mittal, Mehul Kharidia, Tarun Kumar Tripathy, J. Sukarno Mertoguno
  • Patent number: 7246218
    Abstract: A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: July 17, 2007
    Assignee: VIA Technologies, Inc.
    Inventors: Boris Prokopenko, Timour Paltashev, Derek Edward Davout Gladding
  • Patent number: 7228403
    Abstract: A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Petra Leber, Jens Leenstra, Wolfram Sauer, Dieter Wendel
  • Patent number: 7216218
    Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Broadcom Corporation
    Inventor: Sophie Wilson
  • Patent number: 7216138
    Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner. A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Prasad Modali, Chien-Yu Huang, legal representative, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar, Hsien-Cheng E. Hsieh, deceased
  • Patent number: 7213129
    Abstract: A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: Fred Gruner, Mike Morrison, Kushagra Vaid
  • Patent number: 7206921
    Abstract: A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: April 17, 2007
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Simcha Gochman
  • Patent number: 7194602
    Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Kishida, Masaitsu Nakajima
  • Patent number: 7149879
    Abstract: A processor and method of automatic instruction mode switching between N-bit and 2N-bit instructions by using parity bit check. The processor and method includes an instruction input device having a memory for storing a plurality of 2N-bit words, an instruction fetch device fetching a 2N-bit word from the memory, and a mode switch logic determining whether the 2N-bit word fetched by the instruction fetch device is two (N-P)-bit instructions or one 2(N-P)-bit instruction to accordingly switch the processor to corresponding N-bit or 2N-bit mode, wherein when the 2N-bit word fetched is even parity, the 2N-bit word is determined as two (N-P)-bit instructions if two N-bit words included in the 2N-bit word are on the even parity state, or determined as a 2(N-P)-bit instruction if the two N-bit words are on the odd parity state.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: December 12, 2006
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Bor-Sung Liang
  • Patent number: 7133040
    Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Srinivas Chennupaty, Robert S. Dreyer, Michael A. Julier, Katherine Kong, Larry Mennemeier, Ticky S. Thakkar
  • Patent number: 7120779
    Abstract: A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction encoding whilst maintaining backwards compatibility with that legacy encoding.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: October 10, 2006
    Assignee: ARM Limited
    Inventor: David James Seal
  • Patent number: 7103754
    Abstract: A computer architecture that provides the definition of a 20 bit signed displacement value used to form the operand storage address.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Check, Brian B. Moore, Timothy J. Slegel
  • Patent number: 7089393
    Abstract: A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into the coprocessor 10 and also specifying data processing operations to be performed upon operands within those loaded data words to generate result data words. The specified coprocessor processing operations may be a sum of absolute differences calculation for a row of pixel byte values. The result of this may be accumulated within an accumulate register 22. A coprocessor memory 18 is provided within the coprocessor 10 to provide local storage of frequently used operand values for the coprocessor 10.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: August 8, 2006
    Assignee: ARM Limited
    Inventors: Paul Matthew Carpenter, Peter James Aldworth
  • Patent number: 7080235
    Abstract: A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and originates from a translation of a program code is compressed and stored as a sequence of associated program words. The invention also relates to a processor system for carrying out this method. The aim of the invention is to increase operating speed in an application-specific manner while retaining a low program word width. To this end, as regards the method, a program word contains a first characteristic of a primary instruction word and instruction word parts which differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the characteristic.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: July 18, 2006
    Assignee: Systemonic AG
    Inventor: Matthias Weiss
  • Patent number: 7069422
    Abstract: A shift left with carry instruction minimizes the number of instructions required for implementing a binary search. A multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator, wherein the analysis machine implements a binary search by executing a shift left with carry instruction to minimize the number of instructions required for the binary search. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: June 27, 2006
    Inventors: Richard P. Modelski, Michael J. Craren
  • Patent number: 7069420
    Abstract: In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 27, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
  • Patent number: 7069423
    Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: June 27, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
  • Patent number: 7062634
    Abstract: A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: June 13, 2006
    Assignee: STMicroelectronics Limited
    Inventors: Trefor Southwell, Peter Hedinger
  • Patent number: 7051189
    Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: May 23, 2006
    Assignee: ARC International
    Inventor: Peter Warnes
  • Patent number: 7051190
    Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 23, 2006
    Assignee: Intel Corporation
    Inventors: Nicholas G. Samra, Stephen J. Jourdan
  • Patent number: 7047396
    Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: May 16, 2006
    Assignee: Ubicom, Inc.
    Inventors: David A. Fotland, Roger D. Arnold, Tibet Mimaroglu
  • Patent number: 7043627
    Abstract: In view of a necessity of alleviating factors obstructing an effect of SIMD operation such as in-register data alignment in high speed formation of an SIMD processor, numerous data can be supplied to a data alignment operation pipe 211 by dividing a register file into four banks and enabling to designate a plurality of registers by a single piece of operand to thereby enable to make access to four registers simultaneously and data alignment operation can be carried out at high speed. Further, by defining new data pack instruction, data unpack instruction and data permutation instruction, data supplied in a large number can be aligned efficiently. Further, by the above-described characteristic, definition of multiply accumulate operation instruction maximizing parallelism of SIMD can be carried out.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: May 9, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takehiro Shimizu, Fumio Arakawa
  • Patent number: 6996700
    Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: February 7, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6970993
    Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: November 29, 2005
    Assignee: ZiLOG, Inc.
    Inventors: Bruce L. Troutman, Russell B. Lloyd, Randal Q. Thornley
  • Patent number: 6968430
    Abstract: A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: November 22, 2005
    Assignee: LSI Logic Corporation
    Inventor: Asheesh Kashyap
  • Patent number: 6968402
    Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: November 22, 2005
    Assignee: Intel Corporation
    Inventors: David R. Jackson, Stephen W. Kiss, Miles F. Schwartz
  • Patent number: 6961844
    Abstract: A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: November 1, 2005
    Assignee: LSI Logic Corporation
    Inventors: Charles H. Stewart, Asheesh Kashyap
  • Patent number: 6957320
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: October 18, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Cheryl D. Senter, Johannes Wang
  • Patent number: 6952745
    Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert
  • Patent number: 6944749
    Abstract: A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an identification segment and an instruction segment. The method also includes using the assembler to reorder the instructions by separating identification segments from instruction segments, grouping all identification segments of the execution package together, and grouping all instruction segments of the execution package together. The method uses the processor to decode identification segments of the instructions at the same time, and adds a length of each identification segment together to calculate a total length of the execution package.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 13, 2005
    Assignee: Faraday Technology Corp.
    Inventor: Shan-Chyun Ku
  • Patent number: 6922737
    Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: July 26, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masami Maeda, Yoshihiro Asaka, Hidetoshi Sakaki, Masaru Tsukada
  • Patent number: 6907516
    Abstract: Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. Such splitting takes into consideration the correlation between common fields in different instructions as well as the correlation between different fields in the same instruction. Another pre-processing reschedules binary instructions to improve the degree of local sequential correlation without affecting dependencies between instructions. Yet another pre-processing act replaces common operation codes in the instruction with a symbols from a second alphabet, thereby distinguishing between operation codes that have a particular value, and other portions of the instruction that just happen to have the same value.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: June 14, 2005
    Assignee: Microsoft Corporation
    Inventors: Darko Kirovski, Milenko Drinic, Hoi Huu Vo