Decoding Instruction To Accommodate Variable Length Instruction Or Operand Patents (Class 712/210)
  • Patent number: 6499097
    Abstract: The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two size instruction from power of two size instruction data, and control logic for controlling the selection logic.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: December 24, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Graham R. Murphy, Frank C. Chiu
  • Patent number: 6496922
    Abstract: A method and apparatus for providing a stateless multiplatform instruction set architecture (ISA) for use in a computer system having a processor and memory storing a control program for implementing the invention. The system is used to statelessly execute instructions authored to correspond to a variety of different ISA's on a unitary platform. The ISA of the invention uses a very long instruction word (VLIW) architecture with 64-bit instructions, of which several high-order bits are reserved for an ISA identifier tag. When the processor receives an instruction for execution, it inspects the instruction to determine from the ISA identifier tag to which original, native ISA the instruction corresponds. If the corresponding ISA is the native VLIW ISA for the processor, then the instruction is routed to the instruction dispatch unit of the processor, and thence to at least one functional unit for execution.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: December 17, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Paul Borrill
  • Patent number: 6496923
    Abstract: The invention provides a system and method which can be used for pre-decoding one-byte instruction prefixes and branch instruction indicators. A static line detect generates a number of instruction indicators. Further, a prefix and branch decode unit combines at least two of the number of instruction indicators, and a pre-decode unit decodes the combined instruction indicators. Embodiments of the invention decode one byte prefixes without additional cycle penalty and generate one and two byte branch indications early.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: December 17, 2002
    Assignee: Intel Corporation
    Inventors: Frederick Russell Gruner, Bharat Zaveri
  • Patent number: 6493819
    Abstract: A microprocessor includes general purpose registers which may be accessed or updated in portions. Dependencies may be created between an instruction which updates only a portion of a destination register and a subsequent instruction which requires a larger portion of that destination register, inclusive of the smaller updated portion, as a source. To resolve such dependencies between instructions, a determination is made upon decode of an instruction whether it updates only a portion of a destination or the entire destination. If only a portion of the destination is updated by the instruction, a read of the destination is done prior to execution of the instruction and the data read from the destination is merged with the results of the instruction execution. The merged data is then conveyed as the results of the instruction execution.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: December 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric W. Mahurin, Scott A. White, Michael T. Clark
  • Publication number: 20020169946
    Abstract: Embodiments of systems, methods, and computer program products are provided for compressing a computer program based on a compression criterion and executing the compressed program. For example, a computer program may be compressed by scanning an initial computer program to identify one or more uncompressed instructions that have a high frequency of use. A storage mechanism, such as a data structure, may then be populated with the identified uncompressed instructions. A compressed computer program may be generated by respectively replacing one or more of the identified uncompressed instructions with a compressed instruction that identifies a location of the corresponding uncompressed instruction in the storage mechanism. Additional compression of the computer program may be achieved by scanning the compressed computer program to identify one or more uncompressed instructions that have a high frequency of use when at least a portion of their instruction operand is ignored.
    Type: Application
    Filed: December 13, 2000
    Publication date: November 14, 2002
    Inventors: Martin T. Budrovic, David J. Kolson
  • Publication number: 20020156996
    Abstract: A method, cache controller, and computer processor provide a parallel mapping system whereby a plurality of mappers processes several inputs simultaneously. The plurality of mappers are disposed in a pipelined processor upstream from a multiplexor. Mapping, tag comparison, and selection by the multiplexor all occur in a single pipeline stage. Data does not wait idly to be selected by the multiplexor. Instead, each instruction of a first instruction set is read in parallel into a corresponding one of the plurality of mappers. This parallel mapping system implementation reduces processor cycle time and results in improved processor efficiency.
    Type: Application
    Filed: April 18, 2001
    Publication date: October 24, 2002
    Applicant: MIPS Technologies, Inc.
    Inventors: Ryan C. Kinter, David A. Courtright
  • Patent number: 6466930
    Abstract: A data processing method evaluates expressions, including temporally-scoped operands, to produce temporally-scoped results. Each of the temporally-scoped operands and results includes a sequence of one or more value instances, each value instance including a data item, a start time, and an end time, the start time and end time defining a time span in which the data item is valid. An expression involving a binary operator is evaluated by scanning each of the operands of the binary operator and generating a value instance in the result, in respect of each time span in which each operand has a constant value.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: October 15, 2002
    Assignee: International Computers Limited
    Inventor: Paul Anton Richardson Gardner
  • Publication number: 20020144088
    Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.
    Type: Application
    Filed: February 28, 2002
    Publication date: October 3, 2002
    Applicant: Conexant Systems, Inc.
    Inventors: Moataz Ali Mohamed, Chien-Wei Li, John R. Spence
  • Publication number: 20020144084
    Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
    Type: Application
    Filed: May 24, 2002
    Publication date: October 3, 2002
    Inventors: Shuichi Takayama, Nobuo Higaki
  • Patent number: 6460116
    Abstract: A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to expand variable-length instructions to create fixed-length instructions by padding instruction fields within each variable-length instruction with constants until each field reaches a predetermined maximum width. The fixed-width instructions are then stored within the instruction cache and output for execution when a corresponding requested address is received. The instruction cache may store both variable- and fixed-width instructions, or just fixed-width instructions. An array of pointers may be used to access particular fixed-length instructions. The fixed-length instructions may be configured to all have the same fields and the same lengths, or they may be divided into groups, wherein instructions within each group have the same fields and the same lengths.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: October 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Rupaka Mahalingaiah
  • Publication number: 20020129224
    Abstract: A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction.
    Type: Application
    Filed: December 18, 2001
    Publication date: September 12, 2002
    Applicant: IBM
    Inventors: Petra Leber, Jens Leenstra, Wolfram Sauer, Dieter Wendel
  • Patent number: 6442676
    Abstract: A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 27, 2002
    Assignee: Bull HN Information Systems Inc.
    Inventor: Russell W. Guenthner
  • Patent number: 6438680
    Abstract: When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each of selectors (211, 214, and 215) and an exchange circuit (216) so that a memory access unit (3) that has already executed a preceding sub instruction can execute the following sub instruction.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: August 20, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Yamada, Isao Minematsu
  • Patent number: 6434693
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address-collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 13, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Cheryl D. Senter, Johannes Wang
  • Patent number: 6430677
    Abstract: A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 6, 2002
    Assignee: BOPS, Inc.
    Inventors: Gerald G. Pechanek, Edwin F. Barry
  • Patent number: 6425070
    Abstract: The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: July 23, 2002
    Assignee: Qualcomm, Inc.
    Inventors: Qiuzhen Zou, Gilbert C. Sih, Inyup Kang, Quaeed Motiwala, Deepu John, Li Zhang, Haitao Zhang, Way-Shing Lee
  • Publication number: 20020095564
    Abstract: One embodiment of the present invention provides a system for executing variable-size computer instructions, wherein a variable-size computer instruction includes an action component that specifies an operation to be performed and a data component of variable size that specifies data associated with the operation. The system operates by first retrieving the variable-size computer instruction from a computing device's memory. The system then decodes the variable-size computer instruction by separating the variable-size computer instruction into the action component and the data component. Next, the system stores the action component in a first store and the data component in a second store so they can be reused without repeated decoding. Finally, the system provides a first flow path for the action component and a second flow path for the data component.
    Type: Application
    Filed: November 30, 2000
    Publication date: July 18, 2002
    Inventors: Stepan Sokolov, David Wallman
  • Patent number: 6415376
    Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: July 2, 2002
    Assignee: Conexant Sytems, Inc.
    Inventors: Moataz A Mohamed, Chien-Wei Li, John R. Spence
  • Patent number: 6412063
    Abstract: For use in a processor having a pipeline of insufficient width to convey all operands of a given multiple-operand instruction concurrently, a system for, and method of, processing the multiple-operand instruction. In one embodiment, the system includes: (1) node creation circuitry that creates at least first and second nodes for the multiple-operand instruction, the first node being empty and containing at least one of the operands and (2) node transmission circuitry, coupled to the node creation circuitry, that transmits the first and second nodes sequentially through the pipeline. All the operands are subsequently concurrently available within an execution stage of the pipeline for execution of the multiple-operand instruction.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: June 25, 2002
    Assignee: VIA-Cyrix, Inc.
    Inventor: Nicholas G. Samra
  • Publication number: 20020078325
    Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
    Type: Application
    Filed: December 11, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Publication number: 20020078324
    Abstract: A microprocessor for processing various assembler codes, in which a parameter that designates the respective assembler code is provided in the microprocessor and, in dependence on how the parameter is set, a different relative addressing takes place. A method of relative addressing in the microprocessor is also disclosed in which, dependent on an operating state or parameter for the respective assembler code, relative addresses are differently determined.
    Type: Application
    Filed: August 10, 2001
    Publication date: June 20, 2002
    Inventors: Holger Sedlak, Oliver Kniffler
  • Publication number: 20020073300
    Abstract: A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 13, 2002
    Inventors: Eiji Kubo, Tetsuya Nakagawa, Kosaku Aida, Nobuya Kasai, Mark Walton
  • Patent number: 6405303
    Abstract: A microprocessor configured to decode a plurality of instruction bytes in parallel is disclosed. The microprocessor may comprise a plurality of single-byte decoder/execution units that are configured to receive instruction bytes and cross-talk to determine instruction boundaries and instruction field boundaries. Once and instruction has been identified, a determination is made as to whether or not the instruction is a simple instruction. Simple instructions are executed within the decoder/execution units, while complex instructions are forwarded to full-fledged functional units. A computer system and method for predecoding instructions are also disclosed.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: June 11, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul K. Miller, Gerald D. Zuraski, Jr.
  • Patent number: 6401144
    Abstract: A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the information is described. The method includes identifying lines of data to be written, determining a unique start code to be used for that data, and embedding that start code into that data. When the proper number of lines of data have arrived in peripheral device memory, the pending operation is executed.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: June 4, 2002
    Assignee: Intel Corporation
    Inventor: Morris Jones
  • Patent number: 6401130
    Abstract: A method, apparatus and article of manufacture for aggregating a sorted list of IP prefix pairs. A prefix pair in the list is compared to a lowest IP length subnet boundary. The prefix pair is added to a final list if the prefix pair is not on the lowest IP length subnet boundary and the prefix pair is not a first in pair. The prefix pair is moved to a next lower length list if the prefix pair is on the lowest IP length subnet boundary and the prefix pair is a next expected pair. A next higher list is selected, and the method is repeated until there are no more lists.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: June 4, 2002
    Assignee: Nortel Networks Limited
    Inventor: Brad Cain
  • Patent number: 6401194
    Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: June 4, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Le Trong Nguyen, Heonchul Park, Roney S. Wong, Ted Nguyen, Edward H. Yu
  • Patent number: 6397323
    Abstract: In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: May 28, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toyohiko Yoshida
  • Patent number: 6397319
    Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: May 28, 2002
    Assignee: Matsushita Electric Ind. Co., Ltd.
    Inventors: Shuichi Takayama, Nobuo Higaki
  • Publication number: 20020062436
    Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.
    Type: Application
    Filed: December 30, 1998
    Publication date: May 23, 2002
    Inventors: TIMOTHY J. VAN HOOK, PETER HSU, WILLIAM A. HUFFMAN, HENRY P. MORETON, EARL A. KILLIAN
  • Patent number: 6393552
    Abstract: A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: May 21, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard James Eickemeyer, Nadeem Malik, Alan Vicha Pita, Avijit Saha
  • Patent number: 6393501
    Abstract: A microprocessor circuit having an external memory interface includes a transmission element for the transmission of binary data packets between the microprocessor and the interface. The interface includes a buffer with a determined capacity for storing the transmitted data elements. The circuit also includes a controller capable of computing the capacity of the buffer that is available or unavailable owing to the storage of the data elements and capable of reporting the status of availability of the buffer to receive an additional packet. A method is also provided for the control of the interface of such a circuit. The interface comprises a decoder for decoding format data of a packet. The format data of a packet being contained in the data packet and each format data decoding operation being given to the controller in order to optimize the use of the storage capacity of the buffer and the transmission between the microprocessor and the external memory.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: May 21, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Francois Agon, Mark Vos
  • Patent number: 6369723
    Abstract: In rows (1) of data elements (11, 12), there may occur special data elements, such as control characters. By replacing each special data element (12) by a replacement data element (14), which contains a positional indication of a next special data element (12′) and which does not correspond to a special data element (12), it is possible to reproducibly remove all special data-elements from the row (1) without the length of the row increasing essentially. only one single supplementary data element (13) is required for transmitting the positional indication of the first special data element.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: April 9, 2002
    Assignee: Koninklijke KPN N.V.
    Inventors: Rob Pieterse, Leonard Antonius Roos Van Raadshooven
  • Patent number: 6370636
    Abstract: A data access circuit for a CPU that individually extracts and processes variable length data or commands from a memory in one clock period provides high speed processing. The circuit includes a program counter for increasing a previous address by a currently decoded command length to compute the next address. The program counter outputs the next address to a data storing unit and a data alignment unit. The data storing unit can include two memories with two decoders and outputs a prescribed length of data corresponding to the next address from the program counter. The data alignment unit aligns the prescribed amount of data output from the data storing unit using the next address. A command decoding unit decodes the aligned data in order to determine a next command and its variable command length, which is used to reset the currently extracted command length used by the program counter. A command execution unit executes the next command received from the command decoding unit.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: April 9, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Soung-Hwi Park
  • Patent number: 6367003
    Abstract: A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are not using the MAC circuitry. During the idle times, the DSP processor gives control of the MAC to the fixed function circuit. The fixed functions provided by the fixed function circuit can include digital filters, including a Finite Impulse Response filters (FIR), an Infinite Impulse Response (IIR) filter, or an oversampling filter associated with a sigma-delta converter. The DSP may, under program control, set up specific parameters for the fixed function, provide parameters to the fixed function parameter memory, or obtain results from the fixed function. Parameters for the fixed function circuit include the type of filter, the number of taps and the filter coefficients. For a decimation filter, the fixed function parameters can also include the decimation factor.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: April 2, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Henry A. Davis
  • Patent number: 6360317
    Abstract: A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: March 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rupaka Mahalingaiah, Paul K. Miller
  • Patent number: 6360312
    Abstract: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: March 19, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenichi Kawaguchi
  • Patent number: 6356994
    Abstract: An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: March 12, 2002
    Assignee: BOPS, Incorporated
    Inventors: Edwin F. Barry, Gerald G. Pechanek
  • Patent number: 6349379
    Abstract: The present invention discloses an image processor (224) for executing a computer instruction set (280, 290) in the form of an opcode (281), at least one operand (283-285) which is, or indicates the location of data to be processed. The data to be processed consists of a variable length stream of data and each instruction includes a length field (297) containing data specifying the number of items of data to be processed or, if that number exceeds the size of the length field, a predetermined location of a previously allocated storage area at which that number is stored.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: February 19, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ian Gibson, Timothy Merrick Long, Christopher Amies
  • Publication number: 20020016906
    Abstract: The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two size instruction from power of two size instruction data, and control logic for controlling the selection logic.
    Type: Application
    Filed: May 31, 2001
    Publication date: February 7, 2002
    Inventors: Marc Tremblay, Graham R. Murphy, Frank C. Chiu
  • Patent number: 6343356
    Abstract: A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: January 29, 2002
    Assignee: BOPS, Inc.
    Inventors: Gerald G. Pechanek, Edwin F. Barry
  • Patent number: 6343357
    Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: January 29, 2002
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6339821
    Abstract: A data processor is provided to increase the number of instructions it can handle, even with a large number of operands required for the instructions. The data processor comprises a decoding circuit (1) extracting bits (a1, a2) of an instruction as first operand fields and decoding an operation code, using the remaining bits (a4); an operand-field storage portion (3) including a first operand-field storage portion (3a) storing bits (a1, a2) obtained from the decoding circuit (1) via a selector (2), and a second operand-field storage portion (3b) storing a second operand field obtained on the basis of those bits (a2); and a data processing portion (5) receiving the first and the second operand fields from the operand-field storage portion (3) and processing data in registers designated by the first and the second operand fields.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: January 15, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiromi Maeda, Akihiko Ishida, Yukihiko Shimazu
  • Patent number: 6338136
    Abstract: An apparatus and method are provided for executing a compare-and-jump operation in a pipeline microprocessor. Typically, the compare-and-jump operation is specified by two micro instructions. The first micro instruction, an ALU micro instruction, directs the microprocessor to perform an ALU operation, resulting in update of a flags register. The second micro instruction, a conditional jump micro instruction, directs the microprocessor to examine the flags register and to branch program control to a target address if a prescribed condition is met. The apparatus has a jump combiner that detects the ALU micro instruction and the conditional jump micro instruction in a micro instruction queue. The jump combiner indicates the prescribed condition for the conditional branch in a field of the ALU micro instruction, and then deletes the conditional jump micro instruction from the queue. The apparatus also has execution logic that performs the ALU operation, generates the result, and updates the flags register.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: January 8, 2002
    Assignee: IP-First, LLC
    Inventors: Gerard M. Col, Rodney E. Hooker
  • Publication number: 20010049780
    Abstract: A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.
    Type: Application
    Filed: March 27, 1998
    Publication date: December 6, 2001
    Inventors: SHREEKANT THAKKAR, WAYNE H SCOTT, PATRICE ROUSSEL
  • Patent number: 6317822
    Abstract: Code and instruction encoding extensions to a microcontroller architecture provide backward compatibility with an existing microcontroller while allowing significant performance enhancements as a result to the new architecture. An extension to provide additional instruction codes has been implemented while retaining backwards compatibility so that the instructions for the prior processor retain their functionality by utilizing one unused opcode in the prior processor's opcode map. In this connection, two modes of operation are provided, namely binary and source modes. The entire instruction set is available in both modes, but the encoding is different. In the binary mode, all of the instructions of the prior processor keep their encoding. The additional instructions have an ASH prefix, ASH being the single unused opcode. In source mode, some of the instructions from the prior processor known as register instructions have the AS prefix, thereby freeing up 160 opcodes for more important instructions.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: November 13, 2001
    Assignee: Intel Corporation
    Inventor: Kiran A. Padwekar
  • Patent number: 6317825
    Abstract: The invention relates to a microprocessor (MP) comprising means to decode (DEC1) a compact instruction (BMV) for the concatenation of at least one bit (bi) of a first binary word (W1) with at least one bit of a second binary word (W2), and means (REGBANK, MUX, BSHIFT) to process this instruction in one clock cycle. Advantages: fast processing of a concatenation operation. Application especially to chip cards.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: November 13, 2001
    Assignee: Inside Technologies
    Inventor: Sean Commercial
  • Patent number: 6313766
    Abstract: A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs a fixed length value corresponding to a variable length code received as part of the bit stream of the variable length encoded information. The system also includes a processor to receive the fixed length value. The processor to performs a write of a coefficient to a system memory device, the coefficient corresponding to the fixed length value received from the logic device.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: November 6, 2001
    Assignee: Intel Corporation
    Inventors: Brian K. Langendorf, Brian Tucker
  • Patent number: 6314510
    Abstract: A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: November 6, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Ashley Saulsbury, Daniel S. Rice
  • Patent number: 6308258
    Abstract: A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyses the thus-input instruction code and performs the processing necessary for the execution of that instruction. The data processing circuit comprises an instruction decoder section, a register file, and an instruction execution section that executes the instruction based on operational details of the instruction analyzed by the instruction decoder section. The instruction decoder section comprises an ext instruction processing section that processed the expansion of immediate data from the prefix instruction.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: October 23, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Kubota, Makoto Kudo, Yoshiyuki Miyayama
  • Patent number: 6308257
    Abstract: A method of generating boundary markers, for an instruction stream including variable-length instructions, includes generating a number of sets of potential boundary markers for a predetermined set of bytes within the instruction stream. Each set of potential boundary markers is generated based on a respective assumption regarding a boundary byte position within the predetermined set of bytes. For example, a number of sets of potential boundary markers may be generated based on assumptions that respective byte positions within the predetermined set of bytes include the start byte of an instruction. A further set of potential boundary markers may be generated based on an assumption that none of the byte positions within the predetermined set of bytes includes a start byte of instruction.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: October 23, 2001
    Assignee: Intel Corporation
    Inventors: Luke S. K. Theogarajan, James W. Dukes, Ken V. Diep