Abstract: A system-on-chip (SoC) includes: a plurality of processors configured to store respective debugging information in response to respective information extraction commands received in a deadlock state, the plurality of processors having different architectures; a system bus connected to the plurality of processors; and an SoC manager configured to generate the respective information extraction commands differently according to an architecture of each of the plurality of processors in response to detecting occurrence of the deadlock state, and transmit the respective information extraction commands to the plurality of processors through a bus separate from the system bus.

Abstract: Methods, apparatus, and articles of manufacture are disclosed to trigger a scaling action for scaling an application having a set of one or more virtual machines (VMs). Virtualized Network Functions (VNF) are scaled by adding or removing resources to/from existing VMs. In an example method for triggering a scaling action for scaling an application having a set of one or more VMs, a threshold value is adapted based on an evaluation of a monitored system key performance indicator and a monitored external key performance indicator. The threshold value is used for triggering the scaling action. The scaling action is validated based on the monitored external key performance indicator.

Abstract: A controller includes one or more hardware components for performing operations, an interconnect, and a plurality of processors connected to the one or more hardware components through the interconnect. Each processor of the plurality of processors is configured to perform multithreading to concurrently handle multiple threads of execution, and assign a different thread identifier or master ID value to each concurrently handled thread of execution. An instruction is generated for a hardware component by executing a thread of the concurrently handled threads of execution. The instruction includes the thread identifier or indicates the master ID value assigned to the thread. The generated instruction is sent to the hardware component through the interconnect.

Abstract: A method and device for the synchronization of processes, a first signal being sent by a clock-giving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, a temporal distance between at least one of the first edges and at least one of the second edges being determined as a function of a state of a counter in the clock-giving processor. A method for the synchronization of processes, a first signal being received by a clock-receiving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, a state of a counter in the clock-receiving processor being determined as a function of a temporal distance between at least one of the first edges and at least one of the second edges.

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Abstract: A solution providing for the dynamic design, use, and modification of models is provided. The solution can receive an electronic communication identifying a request or event and process the electronic communication in a runtime environment by binding a model of the collection of models to dynamically construct an implementation of the model. Collective properties of the set of related models can emerge dynamically. The binding can comprise late-binding of an application associated with the collection of models to enable at least one user to perform at least one interaction using the environment without disrupting any of the environment or the application.

Abstract: A cloud-based hardware accelerator is selected by deploying an accelerator image to first and second clouds to generate first and second cloud-based hardware accelerators, executing a first request on the first and second cloud-based hardware accelerators, monitoring characteristics of the first and second cloud-based hardware accelerators executing the first request, which may include execution time and monetary cost, and selecting one of the first and second hardware accelerators according to defined selection criteria. Subsequent requests are then routed to the selected cloud-based accelerator.

Abstract: Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.

Abstract: A method and system for partial wavefront merger is described. Vector processing machines employ the partial wavefront merger to merge partial wavefronts into one or more wavefronts. The system includes a partial wavefront manager and unified registers. The partial wavefront manager detects wavefronts in different single-instruction-multiple-data (“SIMD”) units which contain inactive work items and active work items (hereinafter referred to as “partial wavefronts”), moves the partial wavefronts into one or more SIMD unit(s) and merges the partial wavefronts into one or more wavefront(s). The unified register allows each active work item in the one or more merged wavefront(s) to access the previously allocated registers in the originating SIMD units. Consequently, the contents of the unified registers do not have to be copied to the SIMD unit(s) executing the one or merged wavefront(s).

Abstract: Techniques for identifying permitted illegal access operations in a module system are disclosed. An operation, expressed in a first module, that attempts to access a module element of a second module is identified. Based on a module declaration associated with the second module, the module element is determined inaccessible to the first module. Additionally or alternatively, based on an access modifier associated with the module element, the module element is determined inaccessible to the operation. The operation is determined as an illegal access operation. The illegal access operation is permitted to access the module element. A warning corresponding to the illegal access operation is generated.

Abstract: A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.

Abstract: Provided are an apparatus and a method for effectively managing threads diverged by a conditional branch based on Single Instruction Multiple-based Data (SIMD). The apparatus includes: a plurality of Front End Units (FEUs) configured to fetch, for execution by SIMD lanes, instructions of thread groups of a program flow; and a controller configured to schedule a thread group based on SIMD lane availability information, activate an FEU of the plurality of FEUs, and control the activated FEU to fetch an instruction for processing the scheduled thread group.

Abstract: A single workload scheduler schedules sessions and tasks having a tree structure to resources, wherein the single workload scheduler has scheduling control of the resources and the tasks of the parent-child workload sessions and tasks. The single workload scheduler receives a request to schedule a child session created by a scheduled parent task that when executed results in a child task; the scheduled parent task is dependent on a result of the child task. The single workload scheduler receives a message from the scheduled parent task yielding a resource based on the resource not being used by the scheduled parent task, schedules tasks to backfill the resource, and returns the resource yielded by the scheduled parent task to the scheduled parent task based on receiving a resume request from the scheduled parent task or determining dependencies of the scheduled parent task have been met.

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

Abstract: A system and method of managing and prioritizing tasks amongst resources and, more particularly, to a system and method for providing automatic task assignment and notification amongst globally dispersed human resources. The system includes a change of management application configured to store a list of tasks and a task notifier configured to retrieve a list of geographically-dispersed resources and notify selected ones of the geographically-dispersed resources of a priority of completion of one or more tasks retrieved from the change of management application. The system further includes a message application configured to be polled by the task notifier to determine which of the geographically dispersed resources is online or currently working.

Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

Abstract: An apparatus and method are provided for executing thread groups. The apparatus comprises scheduling circuitry for selecting for execution a first thread group from a plurality of thread groups, and thread processing circuitry that is responsive to the scheduling circuitry to execute active threads of the first thread group in dependence on a common program counter shared between the active threads. In response to an exit event occurring for the first thread group, the thread processing circuitry determines whether a program counter check condition is present, and this can be used to trigger program counter checking circuitry to perform a program counter check operation to update the common program counter and an active thread indication for the first thread group.

Abstract: In one example, a system for a system management mode (SMM) privilege architecture includes a computing device comprising: a first portion of SMM instructions to set up a number of resources and implement a privilege architecture for the SMM of a computing device and a second portion of SMM instructions to execute a number of functions during the SMM of the computing device, wherein the privilege architecture assigns the first portion of SMM instructions to a first privilege level and assigns the second portion of SMM instructions to a second privilege level.

Abstract: A warp processing unit controls, in dependence on a warp program counter shared between a plurality of threads processing respective graphics fragments, fetching of a next instruction to be executed for at least some of the plurality of threads. In response to a determination that a given subset of threads is to be discarded when at least one other subset of threads is to continue, the warp processing unit processes the given subset of threads in a discarded state. For a thread processed in the discarded state, execution of instructions continues for the discarded thread, and at least one of: generation of data access messages triggered by the discarded thread is suppressed; and at least one processing operation, which would be deferred until completion of the discarded thread had the thread not been discarded, is enabled to be commenced independently of an outcome of the discarded thread.

Abstract: A data processing system has an execution pipeline with programmable execution stages which execute instructions to perform data processing operations provided by a host processor and in which execution threads are grouped together into groups in which the threads are executed in lockstep. The system also includes a compiler that compiles programs to generate instructions for the execution stages. The compiler is configured to, for an operation that comprises a memory transaction: issue to the execution stage instructions for executing the operation for the thread group to: perform the operation for the thread group as a whole; and provide the result of the operation to all the active threads of the group. At least one execution stage is configured to, in response to the instructions: perform the operation for the thread group as a whole; and provide the result of the operation to all the active threads of the group.

Abstract: A mobile device including a memory including computer-executable instructions for synchronizing a virtual machine and a processor executing the computer-executable instructions, the computer-executable instructions, when executed by the processor, cause the processor to perform operations including executing a virtual machine using a memory; executing a hypervisor providing a synchronization daemon, the synchronization daemon monitoring the memory, the synchronization daemon generating a checkpoint indicating a change in the memory; the hypervisor initiating transmission of the change in the memory over a wireless network for delivery to a standby mobile device to synchronize the virtual machine on the standby mobile device.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: The invention relates to a method for manufacturing a device with a secure integrated-circuit chip, said device having an insulating substrate, electrically conductive surfaces on the substrate, which surfaces are connected or coupled to said electronic chip, said electrically conductive surfaces being produced by a step of depositing or transferring conductive material; the method is characterised in that said step of depositing or transferring conductive material is carried out by a technique of directly depositing metal microparticles, which are free of polymer or solvent, onto the substrate, said deposit being obtained by coalescence of the microparticles forming at least one or more uniform cohesive layers that rest directly in contact with the substrate. The invention also relates to the device obtained.

Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Abstract: An information processing apparatus configured to control a parallel computer system, the information processing apparatus includes a processor configured to determine a plurality of power supply control domains by dividing a plurality of computation nodes, acquire scheduling information that indicates an allocation state of one or more first jobs to the plurality of computation nodes, for each of the plurality of power supply control domains, identify, based on the scheduling information, a first number of the computation nodes each of which does not execute the one or more first jobs, receive a request to execute a second job, identify a second number of computation nodes each of which is to be used for processing of the second job, and control to turn on power supply to a first power supply control domain of the plurality of power supply control domains based on the first and second numbers.

Abstract: Some embodiments described herein provide a method for transmitting an access request via a flexible register access bus. An access request may be received to access resource on an integrated circuit. The access request may be translated to a request packet having a data format compliant with the flexible register access bus. A routing path may be determined for the request packet based on a target register associated with the request packet. The request packet may be transmitted via the routing path to the target register. Information within the request packet may be translated to a local access protocol for the target register. Access to the resource may then be obtained via the target register based on the local access protocol.

Abstract: A system for monitoring job execution includes an interface and a processor. The interface is configured to receive an indication to start a cluster processing job. The processor is configured to determine whether processing a data instance associated with the cluster processing job satisfies a watchdog criterion; and in the event that processing the data instance satisfies the watchdog criterion, cause the processing of the data instance to be killed.

Abstract: A method of executing, by a processor, a multi-thread including threads of the processor, includes setting a mask value indicating execution of one of the threads of the processor based on an instruction, setting an inverted mask value based on the set mask value; and executing the thread of the processor based on the set mask value and the set inverted mask value.

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

Abstract: Techniques for implicit coscheduling of CPUs to improve corun performance of scheduled contexts are described. One technique minimizes skew by implementing corun migrations, and another technique minimizes skew by implementing a corun bonus mechanism. Skew between schedulable contexts may be calculated based on guest progress, where guest progress represents time spent executing guest operating system and guest application code. A non-linear skew catch-up algorithm is described that adjusts the progress of a context when the progress falls far behind its sibling contexts.

Abstract: Methods and apparatus relating to reducing memory latency in graphics operations are described. In an embodiment, uniform data is transferred from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table. The uniform data comprises data that is uniform across a plurality of primitives in a graphics operation. Other embodiments are also disclosed and claimed.

Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated.

Abstract: Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

Abstract: A data processing apparatus has processing circuitry for processing vector operands from a vector register store in response to vector micro-operations, some of which have control information identifying which data elements of the vector operands are selected for processing. Control circuitry detects vector micro-operations for which the control information specifies that a portion of the vector operand to be processed has no selected elements. If this is the case, then the control circuitry controls the processing circuitry to process a lower latency replacement micro-operation instead of the original micro-operation. This provides better performance than if a branch instruction is used to bypass the micro-operation if there are no selected elements.

Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

Abstract: The present application discloses an RSA decryption processor and a method for controlling an RSA decryption processor. A specific implementation of the processor includes a memory, a control component, and a parallel processor. The memory is configured to store decryption parameters comprising a private key. The control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor. The parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. This implementation improves the efficiency of RSA decryption.

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Abstract: Data processing apparatus comprises vector processing circuitry to apply a vector processing instruction to data vectors having a data vector length, each data vector comprising a plurality of data items equal in number to the data vector length, the vector processing circuitry having circuitry defining a plurality of processing lanes, there being at least as many processing lanes as a maximum data vector length; and control circuitry to selectively vary the data vector length used by the vector processing circuitry amongst a plurality of possible data vector length values up to the maximum data vector length and to disable operation of a subset of the processing lanes so that the disabled subset of processing lanes are unavailable for use by the vector processing circuitry and there remain at least as many enabled processing lanes as the data vector length set by the control circuitry.

Abstract: In an embodiment, an apparatus includes a first buffer, a second buffer, and a control circuit. The control circuit may be configured to receive a first plurality of instructions included in a program. The control circuit may also be configured to store each of the first plurality of instructions in an entry of a first number of entries in the first buffer, arranged in the first number of entries dependent upon a received order. The control circuit may be further configured to select a second plurality of instructions from the first buffer. The second plurality of instructions may be selected dependent upon a program order. The control circuit may be configured to store each of the second plurality of instructions in an entry of a second number of entries in the second buffer, arranged in the second number of entries dependent upon the program order.

Abstract: Systems, apparatuses, and methods for optimizing a load-store dependency predictor (LSDP). When a younger load instruction is issued before an older store instruction and the younger load is dependent on the older store, the LSDP is trained on this ordering violation. A replay/flush indicator is stored in a corresponding entry in the LSDP to indicate whether the ordering violation resulted in a flush or replay. On subsequent executions, a dependency may be enforced for the load-store pair if a confidence counter is above a threshold, with the threshold varying based on the status of the replay/flush indicator. If a given load matches on multiple entries in the LSDP, and if at least one of the entries has a flush indicator, then the given load may be marked as a multimatch case and forced to wait to issue until all older stores have issued.

Abstract: A synchronization instruction causes a processor to ensure that specified threads included within a warp concurrently execute a single subsequent instruction. The specified threads include at least a first thread and a second thread. In operation, the first thread arrives at the synchronization instruction. The processor determines that the second thread has not yet arrived at the synchronization instruction and configures the first thread to stop executing instructions. After issuing at least one instruction for the second thread, the processor determines that all the specified threads have arrived at the synchronization instruction. The processor then causes all the specified threads to execute the subsequent instruction. Advantageously, unlike conventional approaches to synchronizing threads, the synchronization instruction enables the processor to reliably and properly execute code that includes complex control flows and/or instructions that presuppose that threads are converged.

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Abstract: The execution or processing of an application can be adapted or modified based on a level of a cache in which a requested data block resides, by extracting level information from a cache hierarchy. When a request for a data block is made by a core to a cache memory system, the cache memory system extracts a level of a cache memory in which the data block resides from information stored in the cache memory system. The core is informed of the level of the cache memory in which the data block resides, and uses this information to adapt its processing of the application.

Abstract: The present invention relates to a system for rendering a three dimensional character and a method for processing thereof. The system for rendering a three dimensional character renders a three dimensional character model, for example, a skin having a multilayered structure such as a face of the person to enable realistic skin expressions according to reflection and scattering of light using a GPGPU. To this end, the system for rendering a three dimensional character includes a plurality of GPGPU modules corresponding to a render pass. According to the present invention, an irradiance texture of an image for each layer of the skin is created and processed using the GPGPU without passing through a render pass of a rendering library, thereby reducing a load of the system for rendering and enabling realistic skin expressions in real time.

Abstract: Systems and methods for assessing vehicle operation are provided. According to certain aspects, an electronic device may receive and analyze image data depicting an individual located within a vehicle. The electronic device may also access and compile certain data related to an environment of the vehicle, and specifically to the vehicle's position relative to the sun. According to embodiments, the electronic device may determine, based on the accessed data, whether the vehicle is traveling into a direction of the sun, and may generate and record an indication of the same.

Abstract: A pinned memory space for caching data can be provided in a data node. The data that is cached in the pinned memory space can be prevented from being swapped out. A virtual address can be assigned to the data. The virtual address can be mapped to a memory address of the data in the pinned memory space for accessing the data by an application. A first command can be received from the application for caching the data. The first command can indicate an attribute associated with the caching of the data. Responsive to receiving the first command from the application for caching the data, the data associated with the first command can be cached by storing the attribute in association with the data in the pinned memory space.

Abstract: Testing code. A method includes identifying in code being executed on a computing system a specification of a permission set. The method further includes dynamically, as the code is running changing a permission level of the computing system to match the permission set. The method further includes executing code at the computing system within the permissions in the permission set. The method further includes during execution, for actions performed in the execution, determining if the permission set includes sufficient permissions for the action to be performed.

Abstract: Systems and methods presented here allow recreation of prior scenes, even if assets used in the scenes have evolved over time. The systems and methods employ query of a database to obtain data for backup and retrieval, e.g., information about shots made at prior points in time, where a “shot” refers to a scene or associated set of sequential frames (a single image may also be considered a shot in some instances), rendered or not depending on context. In the VP-VCR systems and methods, information may be obtained about rendered scenes which allow knowledge and subsequent use of each asset employed in the scene, including its proper version and representation at the time of the rendering. Such may be employed not only to obtain prior versions of shots, but also to allow modification of assets in prior shots to obtain new effects.

Abstract: A system and method adjust instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more of the execution queues that indicates the corresponding execution queue is full. In response to the queue full signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.