Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a J-bit source string and an N-bit destination string. The source address points to the memory location of the J-bit source string. The destination address points to the memory location of the N-bit destination string. The shift number indicates the number of bits the J-bit source string is to be shifted to generate a shifted bit string. The combination of the shifted bit string with the N-bit destination string is conducted under the control of the K-bit mask string. The invention is useful for high speed digital data processing, such as that performed by devices operating under the IEEE 1394 protocol.

Abstract: A CAM cell array (100) that can provide a longest prefix matching operation without necessarily requiring data values to be stored in a particular order. A comparand value can be applied to a CAM cell array (100) to generate ternary match indications. The mask/prefix data values of ternary match indications can be combined to generate a longest prefix value. The longest prefix value can be compared with the mask/prefix data values of the ternary match indications to indicate a data value having a longest prefix match with the comparand value.

Abstract: A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging mask register selectably disable bits of the memory paging register to redefine the length and physical characteristics of pages in memory based on the needs of a software program. As a result, the paged partitions in memory may be of variable length and/or may comprise non-contiguous portions of the memory.

Abstract: Bit value transfer operation instructions are provided. The bit value transfer operation instructions themselves include four instructions, each for selecting a bit value contained in a source bit position of a data memory location and writes the bit value to a destination bit position of another data memory location. Moreover, the instructions specify a source bit position of a data memory location containing a bit value to select, a destination bit position of another data memory location to write the bit value, and the data memory location of an operand from which to read or write the bit value. Processing a bit value transfer operation instruction includes fetching and decoding a bit value transfer instruction. The method further includes executing the bit value transfer instruction on a source bit position of a first data memory location to select a bit value in the source bit position of the first data memory location.

Abstract: A method and apparatus for selectively writing data elements from packed data based upon a mask using predication. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in parallel processing units: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.

Abstract: A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint instruction does not need to be returned to its original location for single-step execution, executing a debugger nub for each target as part of the target task but using a nub task thread for the nub execution that is separate from the target task threads, providing immunity from breakpoints for specified threads such as the nub thread via specialized breakpoint handlers used by those threads, and virtualizing the debugger nub such that a shared root nub provides a uniform interface between the debugger and the target while specialized nubs provide differing functionality based on the type of target being debugged.

Abstract: A method for encoding a data mask that consists of a given total number of bits and includes a selected group of contiguous bits within the total number, the selected group having a left end and a right end. The method includes dividing the data mask into a plurality of segments, and representing the segments by respective segment codes, each code indicating whether the bits in the respective segment fall entirely outside the selected group, entirely within the selected group, or include the left end or the right end of the group. The segment codes are combined so as to generate a mask code, which can be decoded to reconstruct the data mask.

Abstract: An interrupt routing mechanism implemented in a host chipset to eliminate the need for the general purpose I/O pins, special software and external logic devices to steer particular interrupts from a non-legacy Peripheral Component Interconnect (PCI) bus to an external interrupt controller. Such an interrupt routing mechanism may be implemented by a series of logic gates such as OR gates and AND gates for combining all interrupts from a non-legacy PCI bus to produce an output boot interrupt to an external interrupt controller, and alternatively, implemented by a series of AND gates for combining all interrupts from a non-legacy PCI bus and a switch for forwarding an output boot interrupt to an external interrupt controller in accordance with a disable bit used for the steering function.

Abstract: A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction.

Abstract: A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1′), and a second data operand bit group corresponding to a second data operand (D2′). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.

Abstract: Embodiments of the present invention relate to systems and methods for partial merges for sub-register data operations. An instruction is examined before execution to determine which portion of a source register identified in the instruction should remain unchanged into a destination register. A portion of the source register determined to remain unchanged is moved into the destination register before instruction execution is complete.

Abstract: A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.

Abstract: The present invention provides for a method and an apparatus for reducing the effects of manufacturing environmental factors. At least one process run of semiconductor devices is processed. A manufacturing environmental data analysis is performed upon the process run of semiconductor devices. A control parameter modification sequence is implemented in response to the manufacturing environmental data analysis.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: The present invention is a method and apparatus for transferring data from at least two source operands to a destination operand based on a condition. The two source operands are stored in respective source registers. A condition register stores a condition operand from the condition. A masking circuit is coupled to the two source registers for masking the two source operands by the condition operand to generate a masking result. A selector is coupled to the masking circuit for selecting elements of the two source operands based of the masking result.

Abstract: An encoder capable of making a processing time shorter, wherein the position of a first “1” bit seen from the MSB of digital data is output as a first bit encoded data and the second “1” bit is output as the second bit encoded data. A predetermined calculation is performed in parallel on the upper 8 bits of the digital data in the valid detector, the priority encoder, and the first valid bit mask unit, while a predetermined calculation is performed in parallel on the lower 8 bits in another priority encoder and another first valid bit mask unit.

Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

Abstract: The invention relates to a microprocessor (MP) comprising means to decode (DEC1) a compact instruction (BMV) for the concatenation of at least one bit (bi) of a first binary word (W1) with at least one bit of a second binary word (W2), and means (REGBANK, MUX, BSHIFT) to process this instruction in one clock cycle. Advantages: fast processing of a concatenation operation. Application especially to chip cards.

Abstract: A size configurable data buffer includes a plurality of data cache memory registers and a variable number of prefetch memory registers. A computer controller determines the allocation of the data buffer which is data cache memory registers or prefetch memory registers. The size configurable data buffer may be included within a single size configurable data buffer SRAM circuit.

Abstract: Detection of a failure in a multi-system application, includes detecting a first message between a first system and a second system and creating a connection object representing a connection between the first system and the second system. Thereafter, connection status is monitored with the connection object to detect a connection or system failure. The same connection object is used for all subsequent messages between the first system and the second system. The multi-system application uses service objects on the first and the second system, and when a connection or system failure is detected, failure handling is initiated, including notifying all service objects of the failure.

Abstract: A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.

Abstract: A novel method and apparatus of performing data bit moving functions on a data word using two barrel shifters: a left shifter and a right shifter. The present invention is able to handle both shift and rotate functions using one shifter unit. Specifically, for shift functions, only one of the two shifters is used to perform the shifting function. On the other hand, for rotate functions, both shifters are needed for shifting the data word. The amounts of the right shift and left shift depend on the number defined by the count operand and the specific shift/rotate instruction requested.

Abstract: When one or more storage data are coincident with single search data (105), an associative memory with a shortest mask producing function carries out logical multiplication for all of mask information corresponding to the coincident storage data with a mask valid state as true. The result of logical multiplication is used as shortest mask information. In a primary searching operation, the associative memory with a shortest mask producing function is supplied with the search data (105) to provide the shortest mask information on shortest mask lines. Then, as a secondary searching operation, the shortest mask information thus extracted is used as the search data and supplied to the associative memory with a shortest mask producing function. Among the coincident storage data, only a mask match line connected to a particular word having mask information coincident with the shortest mask information is selected as the secondary search result.

Abstract: An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for providing fast searches and while reducing address table size used in the processing of communication system (e.g., Internet Protocol (IP), layer-3 switches and ATM switches using E.164 addressing) addresses for identifying the source and destination of each digital packet data.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: The present invention relates to a data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with said single memory. The register file at least two sets of registers whereby the first set of registers can be coupled with one of the word lines and the second set of registers can be coupled with the respective other word lines, a load and store control unit for transferring data from or to the memory.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A static branch predictor makes a prediction of the outcome of a conditional branch instruction based on the branch test type and the branch target address displacement sign. A branch history table stores a bit indicating whether the prediction of the static predictor agreed with the outcome of the last execution of the branch instruction. If the history table bit agrees, then the static prediction is used. Otherwise, the opposite of the static prediction is used.

Abstract: The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the microcode of floating-point instructions to detect special and exceptional cases of operand values for the floating-point instructions. A checking instruction is configured to set one or more flags in a flags register if it detects a special or exceptional case for an operand value. A checking instruction may also set the result or results of a floating-point instruction to a result value if a special or exceptional case is detected. In addition, a checking instruction may be configured to set one or more bits in status register if a special or exceptional case is detected. After a checking instruction completes execution, a subsequent microcode instruction can be executed to determine if one or more flags were set by the checking instruction.

Abstract: A packed data structure processor (25) is disclosed. The packed data structure processor (25) includes a register file (24) of multiple registers (REG0 through REG31), each of which is connected to an input of each of a plurality of operand multiplexers (26). Each operand multiplexer (26) is associated with a shift/mask circuit (28), which permits the selection of a particular portion (e.g., BYIE, WORD, DWORD) of the contents of a selected register file, for use as an operand. An arithmetic logic unit (ALU) (30) performs data processing operations upon the operands, and presents results on writeback bus (WBBUS), to external memory (18) over a memory interface (37), or to a register file (42) associated with other circuitry (44) over a coprocessor interface (41). A destination selector (40) is capable of writing to only a selected portion of a selected register, thus permitting a packed data structure to be present within the register file (24).

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array.

Abstract: A system and method for determining an age function by performing a logical function on each entry residing within a queue, determining when a particular one of the entries residing in the queue was stored in the queue relative to the other entries, and determining an oldest or youngest entry residing in the queue relative to the logical functions performed on each of the instructions. In one embodiment of the present invention, the entries are instructions temporarily stored within a queue in the processor. The logical function performed may determine which of the instructions is valid. The queue may be cyclical.

Abstract: A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status bits could be a negative status bit, a carry status bit, an overflow status bit and a zero status bit. These status bits are normally set dependent upon the condition of the result generated by the current arithmetic logic unit operation. A status bit protect instruction type permits selection of status bits protected from modification corresponding to the current arithmetic logic unit result. This status bit protect instruction preferably includes individual protect bit corresponding to each status bit. If a protect bit has a first digital state, then the corresponding status bit may be modified corresponding to the current arithmetic logic unit result.

Abstract: A processor comprising a decoder, an execution core and a bus controller. The decoder is operative to decode instructions received by the processor including a move instruction comprising a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks. The execution core, coupled to the decoder, is operative to receive the decoded move instruction and analyze each individual byte mask of the plurality of byte masks to identify corresponding bytes within the plurality of bytes of packed data that are write-enabled. The bus controller, coupled to the execution core, is operative to write select bytes of the plurality of bytes of packed data to an implicitly defined location based, at least in part, on the write enabled byte masks identified by the execution core.

Abstract: The present invention includes a method of transferring data when some of the data is masked. A mask table is provided to a storage device where it is duplicated and stored with the duplicate. The duplicate data is compared to the original data for a data protection function. A mask index counter and mask bit counter maintain provide values for specific data that are to be processed. The counters are programmable so that if a transfer error occurs, counter values for the next data after the previously transferred good data is calculated and loaded therein. The present invention also has the capability not to transfer the last requested sector if that sector is masked. The present invention evaluates whether a stop count value equals a stop threshold value when a sector is identified as being masked. The stop count value is incremented for each sector that is read from the first storage device, regardless of whether that sector is to be transferred or masked.

Abstract: Performing hazard detection using status and mask vectors. Predicate status and mask vectors are generated. From the predicate status vector it is determined if a predicate is pending, and from the predicate mask vector it is determined if the predicate is needed.

Abstract: A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer causes a two cycle non-interruptable instruction to be initiated. The first cycle is a 16-bit misaligned data fetch. The address pointer is incremented by 2 and stored in a temporary pointer register. The second cycle is a 32-bit double word fetch based on the temporary pointer with its least significant bit set to 0 (an aligned fetch). The low word from this fetch is used to satisfy the current misaligned double word fetch and the high word is stored in a temporary buffer register in case it proves useful in subsequent misaligned double fetch instructions. Finally, the temporary address pointer is incremented by 2 for possible use in subsequent misaligned fetches.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.

Abstract: A computer processor that allows the execution of the IBM ESA/390 STOSM and STNSM instructions, in an overlapped fashion, contains an apparatus that allows the STOSM and STNSM instructions to be executed without serializing the processor, or otherwise delaying subsequent instructions, after the STOSM or STNSM instruction, in most cases, thereby improving performance. It contains a mechanism that counts cycles after their execution and prohibits asynchronous interrupts during that time. The invention also contains an efficient mechanism for handling the execution of the STOSM and STNSM instructions when the processor is executing in the SIE environment.

Abstract: A method and apparatus allowing for the direct manipulation of bit fields contained in a memory source. Logic circuitry performs a process wherein bit segments and bit fields contained in respective data strings are manipulated or moved along respective data strings, wherein the bit fields may not be aligned in accordance with data bytes contained in a respective data string. Additionally, the logic circuitry may mask any bits not associated with either the bit segment and the bit field in the respective data strings. The logic circuitry performs an arithmetic operation, wherein the masked respective data strings are arithmetically coupled to each other providing a resultant data string, the resultant data string containing the arithmetic result of the bit segment and the bit field segment as a bit field result. The logic circuitry can pass forward masks of the bit field result and any partially modified byte(s) instead of an entire mask of the respective data strings.

Abstract: A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle of operation, and a correction circuit responsive to the arithmetic/shift function for modifying the standard results provided by the arithmetic/shift function to results required by a SIMD instruction being executed. The arithmetic/shift function is an instruction provided by either an Arithmetic Logic Unit (ALU) or by a shift instruction. The correction circuit passes data, unchanged for logical instructions but provides condition codes according to the SIMD instruction.

Abstract: A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer--an enabling pointer (tail <3:0> (218)) and a disabling pointer (head <3:0> (216))--and for generating a multiple-bit enable, ENA (722) in accordance with the pointer values. The pointers designate enable bit boundaries for isolating enable bits of one logic level from enable bits of an opposite logic level. The enable circuit includes several lookahead cells (702, 704, 706 and 708) arranged in an hierarchical array, each of the cells including bits that continue the hierarchical significance. Each cell receives an hierarchical portion of the enabling pointer 218 and the disabling pointer head <3:0> and a carry. From these pointers, the cell derives a generate, a propagate and the enable bits with a corresponding hierarchical significance.

Abstract: A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A mask decoder circuit is provided. The mask decoder circuit receives an input value indicative of one of a plurality of masks. The mask decoder circuit independently and in parallel processes portions of the input value to produce a submask (containing the portion of the output mask in which a transition from binary zeros to binary ones occurs) and to select either the submask, binary zeros, or binary ones for each of a plurality of regions within an output mask. The region receiving the submask is identified by the portion of the input value not processed to produce the submask. Other regions are filled with either binary zeros or binary ones according to the desired output mask.

Abstract: A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.