Abstract: A technique is disclosed for executing a compiled parallel application on a general purpose processor. The compiled parallel application comprises parallel thread execution code, which includes single-instruction multiple-data (SIMD) constructs, as well as references to intrinsic functions conventionally available in a graphics processing unit. The parallel thread execution code is transformed into an intermediate representation, which includes vector instruction constructs. The SIMD constructs are mapped to vector instructions available within the intermediate representation. Intrinsic functions are mapped to corresponding emulated runtime implementations. The technique advantageously enables parallel applications compiled for execution on a graphics processing unit to be executed on a general purpose central processing unit configured to support vector instructions.

Abstract: The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A compiler may be modified to identify operations that can be performed on either a main pipe or an alternative pipe, identify chains of related operations that can be performed on either the main pipe or the alternative pipe, identify points in the execution of code at which the number of live values will exceed the number of registers, and choosing a chain of operations as a candidate to be moved to the alternative pipe in order to reduce the number of live values at identified points in the execution of code. The entire chosen chain of operations may be moved to the alternative pipe. The alternative pipe may perform the computations and return the results to the main pipe for execution.

Abstract: Systems and methods of securely updating BIOS are disclosed. One such system comprises a reprogrammable memory, a first and a second register, and comparison logic. The reprogrammable memory comprises a first portion and a protect input. The protect input is configured to disallow writes to at least the first portion when the memory protect input is at a first level, and to allow writes to at least the first portion when the protect input is at a second level; The comparison logic is configured to drive a comparison output to a third level responsive to the first and second registers having equal values, and to drive the comparison output to a fourth level responsive to the first and second registers having different values. The comparison output is electrically coupled to the memory protect input.

Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.

Abstract: Hardware and software techniques for interrupt detection and response are provided in a scalable pipelined array processor environment. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.

Abstract: Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result.

Abstract: A system and method of storing a default function from among possible functions to be executed by a device, and executing the default function after a pre-defined interval, if during the interval a user does not respond to a notification of the upcoming execution of the default function, through the user's providing a signal of his desire not to execute the default function.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enveloping a thread of execution within an IDT-based secure sandbox. In one aspect, embodiments of the invention provide a method performed in a computer system, the method receiving an instruction from an execution thread where the computer system can be configured for redirection of instructions from the execution thread. The method can determine whether the instruction includes at least one of an interrupt instruction, a system call instruction and a system enter instruction. In response to determining that the instruction includes at least one of the interrupt instruction, the system call instruction and the system enter instruction, the method can further: (i) eliminate the redirection, (ii) modify a stack to specify return of control, and (iii) thereafter, pass the control to an operating system kernel.

Abstract: A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.

Abstract: A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and two address fields. The two operation fields indicate the type of operation in accessing the memory. One of the address fields includes a first upper address corresponding to the first memory block and a first lower address corresponding to a first memory unit of the first memory block. The other one of the two address fields includes a second upper address corresponding to the second memory block and a second lower address corresponding to a second memory unit of the second memory block. Then, whether two instructions are performing the same type of operation on the same memory block is determined. If yes, the type of operation indicated by the two operation fields is performed on the corresponding memory block parallelly.

Abstract: A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values stored in a floating point register file, to decompress compressed values stored in a register file, to decrypt encrypted values stored in a register file, or to otherwise preprocess data that is stored in an unprocessed form in a register file.

Abstract: The method of compressing and decompressing an executable program, can be executed by a microprocessor or interpreted by an interpreter of an integrated circuit device: instructions are reformatted into the format of an initial set of instructions of said program for obtaining instructions in the format of an intermediate set of instructions; repetition templates in the program are determined and, for each repetition template, a pair is defined, formed of said repetition template and of an instruction in the format of a set of instructions; intermediate instructions are replaced by compressed instructions and the links of the compressed program are modified; the compressed program is stored in a memory of the device; and the compressed program is decompressed and the initial instructions are executed by said microprocessor or interpreted by said interpreter. The invention applies, in particular, to the integrated circuits of embedded devices.

Abstract: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.

Abstract: The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in instructions, the impact of the updates is not limited by the limited memory capacity local to a processor. Also, there is no conflict between hardware and software hints, as they can share a common encoding in the program instructions.

Abstract: A reconfigurable instruction encoding method includes the followings. An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are accordingly found. Multiple instructions of the instruction pairs are duplicately encoded according to multiple reserved sections of an original instruction table, so that the instructions have corresponding reconfigured codes and a reconfigured instruction table extended from the original instruction table and including the reconfigured codes is obtained. A compiler is utilized to generate multiple machine codes according to the reconfigured instruction table and consecutive execution instructions. Hamming distance of the machine codes corresponding to the reconfigured instruction table and the execution instructions are not longer than Hamming distance of the machine codes generated according to the original instruction table and the execution instructions.

Abstract: One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction.

Abstract: In the described embodiments, a processor generates a result vector when executing a RunningShiftForDivide1P or RunningShiftForDivide2P instruction. In these embodiments, upon executing a RunningShiftForDivide1P/2P instruction, the processor receives a first input vector and a second input vector. The processor then records a base value from an element at a key element position in the first input vector. Next, when generating the result vector, for each active element in the result vector to the right of the key element position, the processor generates a shifted base value using shift values from the second input vector. The processor then corrects the shifted base value when a predetermined condition is met. Next, the processor sets the element of the result vector equal to the shifted base value.

Abstract: A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the hardware facility is absent from the data processing system, the candidate instruction is substituted with a second set of instructions.

Abstract: A register control circuit that controls a register specified by an inputted address includes a signal output that outputs a first control signal and a second control signal based on the inputted address, a selector that selects data of a register specified by the first control signal outputted from the signal output, a logical operator that performs a logical operation of write data outputted from a processor and the data selected by the selector to output an operation result, and a storage that stores data in the register specified by the first control signal by selecting one of the write data and the operation results as the data based on the second control signal outputted from the signal output.

Abstract: Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified as a last-use register, where a last-use register has a value that is not to be accessed by later instructions, whereby the two computer machine instructions are replaced by a single optimized internal instruction for execution, the single optimized instruction not including the last-use register.

Abstract: Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Abstract: A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an original source code by an input device into the computing apparatus; finding a critical path in the original source code by a critical path cut module; cutting the critical path in the original source code into a plurality of process block groups by the critical path cut module; and dividing the plurality of process block groups among a plurality of processors in the multiprocessor system by a CPU assignment code generation module to produce the divided source code. The system includes an input device; a critical path cut module; and a CPU assignment code generation unit to produce the divided source code. The computer readable article of manufacture includes instructions to implement the method.

Abstract: A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.

Abstract: A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that outputs a first address for specifying a first execution circuit for the first calculation and a second execution circuit for the second calculation, to the first circuit and the second circuit, and controls input of data into the first circuit, and a bus that transfers a result of the first calculation executed by the first circuit to the second circuit, wherein the result of the first calculation can be conditionally used as an address for specifying the second execution circuit.

Abstract: The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an instruction of each instruction code type other than a prefix on the basis of a determination result of decoders for determining an instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant to instruction executing means. When an instruction of a target instruction code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target instruction code type as prefix code candidates. When an instruction of a target instruction code type cannot be detected at the rear end of the instruction units to be searched, the circuit outputs the instruction at the rear end as a prefix code candidate.

Abstract: Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.

Abstract: Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

Abstract: A relocatable interrupt handler for use in test generation and execution. A method for executing test code includes executing a test code block that includes a plurality of test instructions. The executing includes, for one or more of the test instructions: executing the test instruction; determining that the executing the test instruction caused an exception condition to occur; executing first exception handling logic associated with the exception condition based on determining that the executing the test instruction caused the exception condition to occur, the first exception handling logic located at an entry address consisting of a first memory address value, the executing the first exception handling logic including: clearing the exception condition; and changing the entry address to a second memory address value that is an address of a second exception handling logic. A return code that indicates a result of executing the test code block is then generated.

Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.

Abstract: An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a larger scope for transformation (e.g. optimization) than traces. Hardware samples are used to identify SRs that contain the hot code of a client process without requiring any static program information.

Abstract: An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms.

Abstract: A dynamically reconfigurable processor which executes a series of processes on an instruction basis for respective instructions, comprises: a dynamically configurable computing unit; and a clock generating circuit, wherein start timing for processes in the series of processes is determined based on the main clock except for an instruction execution process of executing the instruction with the dynamically configurable computing unit, the instruction execution process of executing the instruction with the dynamically configurable computing unit includes a computing element generating sub-process of dynamically configuring, with dynamically configurable computing unit, a computing element corresponding to the instruction, and an operation sub-process of performing an operation according to the instruction with the computing element configured in the computing element generating sub-process, start timing for the computing element generating sub-process and the operation sub-process is determined based on the sub

Abstract: A method of encapsulating a long instruction in a set of short instructions for execution on a processor, the long instruction having k bits and each short instruction having l bits where l<k, includes assembling a first portion of the long instruction and a first identifier to form a first instruction of the set of short instructions; and assembling a second portion of the long instruction and a second identifier to form a second instruction of the set of short instructions; wherein at least one of the first and second identifiers is for identifying to the processor that the set of short instructions encapsulates the long instruction.

Abstract: A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed.

Abstract: The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a hybrid computing system. To this extent, a hybrid system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications on a hybrid image processing system referred to herein as an image co-processor that comprises (among other things) a plurality of special purpose engines (SPEs) that work to process multiple images in an accelerated fashion.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.

Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Abstract: A data processing apparatus includes a reconfigurable circuit capable of reconfigurating partially a circuit configuration: and a reconfiguration controlling unit that controls a reconfiguration of the circuit configuration of the reconfigurable circuit. The reconfiguration controlling unit reconfigurates a plurality of partial circuits, which constitute one pipeline and are reconfigurated simultaneously on the reconfigurable circuit, on the reconfigurable circuit in sequence from a head partial circuit of the pipeline, and starts sequentially the reconfigurated partial circuits from a head.

Abstract: A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information processing apparatus that includes an output device and a computer readable storage medium storing the program code. At least one transformation is performed on the target program to generate a transformed target subprogram in which dependencies among the instructions included in the target subprogram are matched with dependencies in the pattern to be replaced. The transformed target subprogram is replaced, with a post-replacement instruction stream determined to correspond to the pattern to be replaced, to generate a replaced target subprogram. An optimized target program that includes the replaced target subprogram is outputted to the output device. The at least one transformation includes a first transformation, a loop transformation, or both the first transformation and the loop transformation.

Abstract: Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S1), b) initializing a set of removed instructions as empty (S3), c) determining the most compact representation of the first set of instructions (S4) d) comparing the size of said most compact representation with a threshold value (S5), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S6), e2) removing said instruction having the highest coding cost from the first set of instructions and (S7), e3) adding said instruction to the set of removed instructions (S8), f) repeating steps b-f, wherein the first set of instructions

Abstract: A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language specification includes memory read actions and modification actions. Each memory read action reads a stored value from a memory of the network packet processor. Each modification action modifies a field of the network packets. An availability is determined for each field read from the network packets for the memory read and modification actions. An availability is determined for each stored value read from the memory for the memory read actions. A look-ahead interval is determined from the availabilities. A respective storage class is determined for the fields for the memory read and modification actions. The respective storage class is one of a bus, a register, and a register with bypass.

Abstract: A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

Abstract: An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

Abstract: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.

Abstract: An instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a first storage unit and removing part or all of the translated code block from the first storage unit at a given timing, wherein the generating reduces the threshold with respect to the number of executions over a given period of time after the part or all of the translated code block is removed.

Abstract: Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.

Abstract: It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output from the outputs of each stage of the pipeline. When a branch instruction is issued and subsequent inputs of the pipeline are in the order of CD?1, CD?2, . . . , the decryptor module outputs a first decrypted code by performing a one-stage pipeline process to CD?1. Next, the decryptor module outputs a second decrypted code by performing a two-stage pipeline process to CD?2, and the decryptor module outputs a third decrypted code by performing a three-stage pipeline process to CD?3 (and subsequent codes). Therefore, in particular, the overhead to CD?1 can be reduced.

Abstract: A method, according to one aspect, may include estimating costs associated with translating a multi-format instruction of a source instruction set architecture to instructions of a target instruction set architecture by using a different format of the multi-format instruction for each of the costs, and selecting a format for the multiformat instruction based at least in part on the estimated costs. Methods of organizing or grouping multi-format instructions based on register use relationships. Software, hardware, and computer systems to implement the methods are also disclosed.

Abstract: A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction is decoded as a store instruction. This allows a redundant operation in an instruction set architecture to be redefined as a store instruction, freeing up opcodes normally used for store instructions to be used for other instructions.