Abstract: Machine-based filtering of a pattern history table includes identifying a matching previous occurrence of a current branch instruction in an address history vector (AHV), the AHV storing addresses, or partial addresses, of most recently occurring branch instructions. In response to determining a direction history of the previous occurrence matches a direction history of the current branch, the machine-based filtering includes comparing the outcome of the previous occurrence with the outcome of the current branch instruction, and preventing the pattern history table from being updated with the outcome of the current branch instruction when the outcome of the previous occurrence does not match the outcome of the current branch instruction.

Abstract: An electronic device includes a memory, a processor coupled to the memory, and one or more policies stored in the memory. The policies include a resource availability policy determining whether the processor should continue evaluating the software, and a job availability policy determining whether new jobs will be created for unexplored branches. The processor is configured to receive a job to be executed, evaluate the software, select a branch to explore and store an initialization sequence of one or more unexplored branches if a branch in the software is encountered, evaluate the job availability policy, decide whether to create a job for each of the unexplored branches based on the job availability policy, evaluate the resource availability policy, and decide whether to continue evaluating the software at the branch selected to explore based on the resource availability policy. The job indicates of a portion of software to be evaluated.

Abstract: A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.

Abstract: Systems and methods for history based pipelined branch prediction. In one example, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

Abstract: A system and method for efficient branch prediction. A processor includes two branch predictors. A first branch predictor generates branch prediction data, such as a branch direction and a branch target address. The second branch predictor generates branch prediction data at a later time and with higher prediction accuracy. Control logic may determine whether the branch prediction data from each of the first and the second branch predictors match. If a mismatch occurs, the first predictor may be trained with the branch prediction data generated by the second branch predictor. A stored indication of hysteresis may indicate a given branch instruction exhibits a frequently alternating pattern regarding its branch direction. Such behavior may lead to consistent branch mispredictions due to the training is unable to keep up with the changing branch direction. When such a condition is determined to occur, the control logic may prevent training of the first predictor.

Abstract: A processor includes: first selectors that select instruction addresses of instructions of a plurality of threads or a branch target address of a branch instruction to be predicted and that output addresses of the plurality of threads; a second selector that selects one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit that predicts and outputs a branch direction, which indicates whether the branch instruction of the address selected by the second selector is branched, based on the selected address in a first cycle stage and that predicts and outputs the branch target address of the branch instruction to be predicted based on the selected address in a second cycle stage later than the first cycle stage; and a thread arbitration circuit that controls selection of the addresses of the threads by the first selectors and the second selector.

Abstract: A processor includes: first selectors that select instruction addresses of instructions of a plurality of threads or a branch target address of a branch instruction to be predicted and that output addresses of the plurality of threads; a second selector that selects one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit that predicts and outputs a branch direction, which indicates whether the branch instruction of the address selected by the second selector is branched, based on the selected address in a first cycle stage and that predicts and outputs the branch target address of the branch instruction to be predicted based on the selected address in a second cycle stage later than the first cycle stage; and a thread arbitration circuit that controls selection of the addresses of the threads by the first selectors and the second selector.

Abstract: The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of target instructions created beforehand collectively, thereby processing those instructions collectively according to the coding when those target instructions are combined so as to be processed collectively and a memory for storing the collective emulation coding.

Abstract: Embodiments include a computer processor-error controller, a computerized device, a device, an apparatus, and a method. A computer processor-error controller includes a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction. The computer processor-error controller includes an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

Abstract: Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

Abstract: Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.

Abstract: A method, data processing system, and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

Abstract: Techniques and structures are disclosed relating to a branch target cache (BTC) in a processor. In one embodiment, the BTC is usable to predict whether a control transfer instruction is to be taken, and, if applicable, a target address for the instruction. The BTC may operate in conjunction with a delayed branch predictor (DBP) that is more accurate but slower than the BTC. If the BTC indicates that a control transfer instruction is predicted to be taken, the processor begins to fetch instructions at the target address indicated by the BTC, but may discard those instructions if the DBP subsequently determines that the control transfer instruction was predicted incorrectly. Branch prediction information output from the BTC and the DBP may be used to update the branch target cache for subsequent predictions. In various embodiments, the BTC may simultaneously store entries for multiple processor threads, and may be fully associative.

Abstract: A system is disclosed for providing branch misprediction prediction in a microprocessor. The system includes a mispredicted branch table that includes address, distance, and true/not true fields, and an index to the mispredicted branch table that is formed responsive to 1) a current mispredicted branch, 2) a global history, 3) a global misprediction history, and 4) a branch misprediction distance.

Abstract: A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.

Abstract: Upon start of a program, a plurality of flags, each corresponding to an instruction of the program, are initialized to a disabled state and an initial state of a BHT is stored. Upon execution of a branch instruction, if a branch has not been taken, a value of history information of a corresponding entry of the BHT is decremented. If the branch has been taken, the value of the history information of the corresponding entry is incremented and whether a corresponding flag is enabled or disabled is determined. If the corresponding flag is disabled, the flag is enabled. Upon termination of the program, a differential history information value of each entry is obtained from the stored initial state and a final state of the BHT. A final state of each flag is obtained.

Abstract: A method, system and computer product for purging pattern history tables as a function of global accuracy in a state machine-based filter gshare branch predictor. An exemplary embodiment includes a method including storing a plurality of encountered branch instructions in the branch history table, indexing the branch history table by a branch instruction address, modifying an entry of the branch history table, indexing the pattern history table, selecting at least one of a branch history entry and a pattern history table entry as a prediction for the branch instruction, wherein the pattern history table entry is selected as the prediction for the branch instruction in response to the branch history entry being in a state specifying to use the pattern history table entry, comparing a pattern history table accuracy to an accuracy threshold, and in response to the pattern history table accuracy falling below the accuracy threshold, purging the PHT.

Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.

Abstract: A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value.

Abstract: A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed.

Abstract: A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache.

Abstract: An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming apparatus. A log corresponding to the usage of the service is set in job log information with a synchronization flag set off. The log in the job log information, for which the synchronization flag is set off, is set on. The counter information and the job log information are output after the synchronization flag for the log having the synchronization flag set off has been set on.

Abstract: Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a program address circuit, a branch target buffer, a branch prediction replacement circuit, and an execution pipeline. The branch target buffer includes a plurality of entries each associated with a respective change of flow instruction. Each entry includes an indication of an entry source and a next program address corresponding to the respective change of flow instruction. The branch prediction replacement circuit is operable to determine replacement priorities of the plurality of entries based at least in part on the entry source for each of the plurality of entries. The execution pipeline receives an executable instruction corresponding to one of the next program addresses.

Abstract: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome.

Abstract: When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control device are separately used in a strand 0 group and a strand 1 group. The data of the strand 0 and the data of the strand 1 are allocated to the respective entries by switching a select circuit. When an entry is released from the branch reservation station, the select circuit switches the strands so that a branch instruction in one strand can be released in order, thereby releasing the entry.

Abstract: An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions.

Abstract: Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

Abstract: A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured to provide improved performance based upon the current workload.

Abstract: A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location, and saving the data in a branch prediction memory, or receiving an unload instruction including the first data location in the first memory area, retrieving data including a branch address and a target address from the branch prediction memory, and saving the data in the first data location.

Abstract: The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.

Abstract: The disclosure provides a method, data processing system, and computer program product for managing a branch trace environment. In response to a branch being taken for a first branch instruction that is conditional and direct in the branch instructions, a performance monitoring unit stores an effective address of the first branch instruction into a first entry in a set of entries in a memory. The performance monitoring unit counts each branch not taken in processing the branch instructions occurring after the first branch instruction to form a branch count. In response to a branch being taken during processing of subsequent branch instructions in the branch instructions after the first branch instruction, the performance monitoring unit determines whether to create a second entry in the set of entries in the memory using the branch count with a set of rules identifying when the second entry is to be made.

Abstract: A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines.

Abstract: Machine-based filtering of a pattern history table includes identifying a matching previous occurrence of a current branch instruction in an address history vector (AHV), the AHV storing addresses, or partial addresses, of most recently occurring branch instructions. In response to determining a direction history of the previous occurrence matches a direction history of the current branch, the machine-based filtering includes comparing the outcome of the previous occurrence with the outcome of the current branch instruction, and preventing the pattern history table from being updated with the outcome of the current branch instruction when the outcome of the previous occurrence does not match the outcome of the current branch instruction.

Abstract: A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.

Abstract: In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.

Abstract: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.

Abstract: Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.

Abstract: An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine.

Abstract: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.

Abstract: In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect branch target predictor may also store a validation tag corresponding to each stored target address. The validation tag may be compared to similar data corresponding to the current indirect branch being predicted. If the validation tag does not match, the indirect branch is presumed to be mispredicted (since the branch target address actually belongs to a different instruction). The indirect branch target predictor may inhibit speculative execution subsequent to the mispredicted indirect branch until the redirect is signalled for the mispredicted indirect branch.

Abstract: A method for preventing a return address from being falsified due to a buffer overflow during the program execution, and for detecting the buffer-overflow beforehand. When the return address is re-written during program execution, the debug function of the central processing unit is used to output an error. The falsification of the return address is detected through the error output. Then the falsified return address is re-written to a value stored in advance to enable the program to return to normal operation. When the falsification of the return address is detected, the executing program is terminated.

Abstract: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.

Abstract: A method and system for power conservation in a hierarchical branch predictor system are provided. The method includes addressing multiple branch predictors, each of the branch predictors having various sizes of hierarchical storage and storing information about previously encountered branch instructions. In response to receiving a first branch prediction from one of the branch predictors, the method includes comparing the first branch prediction with previously stored branch predictions to determine the existence of a branch prediction loop, the branch prediction loop including a sequence of branch predictions that repeat as long as constituent predictions of the branches remain unchanged. Upon determining that a branch prediction loop exists, the method includes associating the branch prediction loop with the branch predictors that provided each branch prediction, and activating power saving to the branch predictors that are not associated with the branch prediction loop.

Abstract: A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.

Abstract: A branch target buffer (BTB) system and method for storing target address is provided. The BTB system is applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When the target address of the branch instruction is stored, the BTB stores the variation range, carry bit and sub/add bit of the target address without having to store all the bits of the target address. Because the BTB does not need to store the identical part of the branch instruction address and the target address, the number of bits of the target address field for the BTB of the processor needs to be stored is reduced. Although less number of bits are stored for the target address field, the BTB system is able to generate a complete target address without affecting the computation performance.

Abstract: An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.

Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.

Abstract: A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register. The method further loads the branch history information into the second register during the second pipeline stage.

Abstract: A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item.

Abstract: A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program instruction; tracing circuitry for tracing operation of the data processing apparatus for outputting a prediction indicator indicating whether or not the predicted response is correct; a data store configured to store information relating to the predicted response of said data processing circuitry at the given execution point for use by at least one of said prediction logic and said tracing circuitry a later execution point; and a history buffer configured to store historical information with regard to one or more entries of the data store at a corresponding execution point previous to the given execution point to enable restoration of said data store to a state corresponding to said previous execution point.