Exeception Processing (e.g., Interrupts And Traps) Patents (Class 712/244)
  • Patent number: 8572357
    Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Greiner, James H. Mulder, Robert R. Rogers, Robert W. StJohn
  • Patent number: 8572355
    Abstract: One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: October 29, 2013
    Assignee: Nvidia Corporation
    Inventors: Guillermo Juan Rozas, Brett W. Coon
  • Patent number: 8572573
    Abstract: Systems and methods are disclosed for performing interactive debugging of shader programs using a non-preemptible graphics processing unit (GPU). An iterative process is employed to repeatedly re-launch a workload for processing by the shader program on the GPU. When the GPU encounters a hardware stop event, such as by reaching a breakpoint in any thread of the shader program, encountering a hardware exception, or failing a software assertion in the shader program, the state of any executing threads is saved, graphics memory is copied to system memory, and any currently executing threads are killed to enable the GPU to process graphics data for updating a display device. Each pass of the workload may result in incrementally more data being processed. In effect, the changing state and variable data resulting from each pass of the workload has the effect that the debugger is incrementally stepping through the shader program.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 29, 2013
    Assignee: Nvidia Corporation
    Inventors: Avinash Bantval Baliga, Gregory Paul Smith
  • Publication number: 20130283024
    Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
    Type: Application
    Filed: June 21, 2013
    Publication date: October 24, 2013
    Inventors: Hidemi OYAMA, Masanobu KAWAMURA, Takuya IKEGUCHI, Masanori MATSUMOTO, Hiroyuki KAWAJIRI
  • Publication number: 20130275735
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    Type: Application
    Filed: June 11, 2013
    Publication date: October 17, 2013
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
  • Patent number: 8549269
    Abstract: A method, apparatus and software is disclosed in which original exceptions issued by an application program are encoded as substitute exceptions with associated metadata identifying the original exception so as to enable to enable a first application program receiving the exception but not arranged to process the original exception to process the substitute exception and to enable a second application program receiving the exception and arranged to process the original exception to extract and process that original exception.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventor: Timothy John Baldwin
  • Patent number: 8539209
    Abstract: A microprocessor breakpoint-checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: September 17, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: Bryan Wayne Pogor, Colin Eddy
  • Patent number: 8539203
    Abstract: In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Toshiyuki Matsunaga
  • Patent number: 8527743
    Abstract: A microprogrammable electronic device comprises a code memory storing a plurality of instructions. At least one instruction, when executed by the device, causes the device to enter into a wait state associated with a plurality of predefined wait state exit conditions. The device is configured to load into an electronic table each condition together with a corresponding code memory address of an instruction to be executed when the condition occurs; to execute, when is in the wait state, a wait instruction stored in the code memory and which, when executed, is such as to cause the device to check simultaneously the conditions loaded into said electronic table to detect if condition occurs; and, if a condition occurs, to exit from said wait state and to execute the instruction stored in the code memory at the code memory address loaded into the electronic table together with the condition that occurred.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: September 3, 2013
    Assignee: C.R.F. Societa Consortile per Azioni
    Inventors: Claudio Genta, Alberto Manzone
  • Patent number: 8528000
    Abstract: The execution environment provides for scalability where components will execute in parallel and exploit various patterns of parallelism. Dataflow applications are represented by reusable dataflow graphs called map components, while the executable version is called a prepared map. Using runtime properties the prepared map is executed in parallel with a thread allocated to each map process. The execution environment not only monitors threads, detects and corrects deadlocks, logs and controls program exceptions, but also data input and output ports of the map components are processed in parallel to take advantage of data partitioning schemes. Port implementation supports multi-state null value tokens to more accurately report exceptions. Data tokens are batched to minimize synchronization and transportation overhead and thread contention.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: September 3, 2013
    Assignee: Pervasive Software, Inc.
    Inventors: Larry Lee Schumacher, Agustin Gonzales-Tuchmann, Laurence Tobin Yogman, Paul C. Dingman
  • Publication number: 20130227256
    Abstract: A method for setting one or more breakpoints within executable program code of an embedded device is described. The method comprises copying at least one area of non-volatile memory (NVM) of the embedded device, comprising at least one instruction at which a breakpoint is to be set, into at least one area of overlay memory replacing within the overlay memory the at least one instruction at which a breakpoint is to be set with a breakpoint operation code, and enabling a mapping of the at least one area of NVM, comprising the at least one instruction at which a breakpoint is to be set, to the at least one area of overlay memory during execution of the program code within the embedded device.
    Type: Application
    Filed: November 22, 2010
    Publication date: August 29, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Alistair Robertson, Mark Maiolani
  • Patent number: 8522000
    Abstract: A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 27, 2013
    Assignee: Nvidia Corporation
    Inventors: Michael C. Shebanow, Jack Choquette, Brett W. Coon, Steven J. Heinrich, Aravind Kalaiah, John R. Nickolls, Daniel Salinas, Ming Y. Siu, Tommy Thorn, Nicholas Wang
  • Patent number: 8521995
    Abstract: A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Gad Sheaffer, Jan Gray, Landy Wang, Martin Taillefer, Arun Kishan, Ali-Reza Adl-Tabatabai, David Callahan
  • Patent number: 8516224
    Abstract: Instructions asserted in the instruction pipeline of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units, to interpret that control information and take appropriate action.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: August 20, 2013
    Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
  • Patent number: 8516229
    Abstract: A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allon Adir, Brad Lee Herold, John Martin Ludden, Pedro Martin-de-Nicolas, Charles Leverett Meissner, Gil Eliezer Shurek
  • Patent number: 8516231
    Abstract: An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-hyun Park, Soo-jung Ryu, Dong-hoon Yoo, Yeon-gon Cho, Bernhard Egger
  • Patent number: 8508782
    Abstract: A method for securing a computer device against malicious code, the method including the steps of: executing a computer program on the computer device, the computer device having a central processing unit, which carries out instructions of the computer program, and wherein at least a portion of the computer program is executed by one or more tasks, each of the one or more tasks having a task stack associated therewith; and managing the central processing unit such that the central processing unit does not execute machine code from the task stacks associated with each of the one or more task so as to secure the computer device against malicious code from the task stack.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: August 13, 2013
    Assignee: Konica Minolta Laboratory U.S.A., Inc.
    Inventor: Shaun Pinney
  • Publication number: 20130205125
    Abstract: Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.
    Type: Application
    Filed: November 19, 2012
    Publication date: August 8, 2013
    Applicant: ARM LIMITED
    Inventor: Arm Limited
  • Patent number: 8499140
    Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Lichtensteiger, Pascal A. Nsame, Sebastian T. Ventrone
  • Patent number: 8495606
    Abstract: A system performs operations comprising creating a call graph for a program translated from source code, identifying redundant exception handling code in the program utilizing the call graph, and removing the redundant exception handling code. The operation of identifying redundant exception handling code may comprise identifying at least one function or callsite by determining that a first function in the at least one function's or callsite's callee chain throws an exception and that the exception is handled by a second function in the function's or callsite's callee chain or by determining that an exception is not thrown in the at least one function's or callsite's callee chain. The operation of removing the redundant exception handling code may comprise removing redundant exception handling code included in at least one function or callsite and/or removing at least one entry for the at least one function or callsite from an exception lookup table.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: July 23, 2013
    Assignee: Oracle America, Inc.
    Inventors: Sheldon M. Lobo, Fu-Hwa Wang
  • Patent number: 8493395
    Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 23, 2013
    Assignee: Nvidia Corporation
    Inventors: Jerome F. Duluk, Jr., Henry P. Moreton, Steven E. Molnar, John S. Montrym
  • Patent number: 8489867
    Abstract: A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Greiner, James H. Mulder, Robert R. Rogers, Robert W. Stjohn
  • Publication number: 20130173895
    Abstract: Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information.
    Type: Application
    Filed: October 23, 2012
    Publication date: July 4, 2013
    Inventors: Yadong Li, Sujoy Sen
  • Patent number: 8473728
    Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 25, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
  • Publication number: 20130159685
    Abstract: A function in source code is processed by a compiler for execution on a graphics processing unit, wherein the function includes an exception handling structure. An exception raising block is converted into a first control flow and an exception handler block is converted into a second control flow. The first control flow includes setting an exception raised indicator and finding an exception handler to process the raised exception. The exception raised indicator remains set until an appropriate exception handler is found. The second control flow includes clearing the exception raised indicator and processing the exception.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Dz-ching Ju, Norman Rubin, Gang Chen
  • Publication number: 20130151824
    Abstract: A source computer system with one instruction set architecture (ISA) configured to run on a target hardware system that has its own ISA. During execution from binary translation, synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system, and asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The system also includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream. The binary translation and exception-handling subsystems are included as components of a virtual machine monitor which is installed between the target hardware system and the source system.
    Type: Application
    Filed: October 22, 2012
    Publication date: June 13, 2013
    Applicant: VMWARE, INC.
    Inventor: VMware, Inc.
  • Publication number: 20130151819
    Abstract: A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: ARM LIMITED
    Inventors: Frederic Claude Marie PIRY, Luca SCALABRINO, Guillaume SCHON, Melanie Emanuelle Lucie TEYSSIER
  • Patent number: 8464033
    Abstract: Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 11, 2013
    Inventors: Guillermo J. Rozas, Alexander Klaiber
  • Publication number: 20130145136
    Abstract: A method of handling exceptions in a data parallel system includes forwarding exceptions thrown by concurrent worker tasks to a coordination task. The thrown exceptions are aggregated into an aggregation exception structure. It is determined whether the aggregation exception structure will be handled by an exception handler. The concurrent worker tasks are unwound when it is determined that the aggregation exception structure will be handled.
    Type: Application
    Filed: January 29, 2013
    Publication date: June 6, 2013
    Applicant: MICROSOFT CORPORATION
    Inventor: MICROSOFT CORPORATION
  • Patent number: 8447962
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: May 21, 2013
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 8424013
    Abstract: Methods and systems are disclosed that relate to handling interrupts across multiple software instances. An exemplary method includes receiving an interrupt at a current CPU. An instance includes a set of independent threads of execution each with its own code context, interrupt service routines, drivers, and operating system services. The method further includes storing context information relating to the first instance, identifying the second instance associated with the interrupt, running at least one interrupt service routine, and restoring the context information relating to the first instance.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 16, 2013
    Assignee: EMC Corporation
    Inventors: Steven R. Chalmer, Steven T. McClure, David L. Reese
  • Patent number: 8424021
    Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: April 16, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Jack Kang, Yu-Chi Chuang
  • Patent number: 8417924
    Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 9, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • Patent number: 8417918
    Abstract: An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: April 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Dong-hoon Yoo, Soo-jung Ryu, Il-hyun Park
  • Patent number: 8417925
    Abstract: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventor: Dung Quoc Nguyen
  • Patent number: 8407492
    Abstract: Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with minimal power consumption. A plurality of completion signals is received from a processing circuit. Each of the plurality of completion signals identifies an associated operation has been completed by the processing circuit. A plurality of phase signals is generated where the plurality of phase signals includes a respective phase signal generated at a time when each of the plurality of completion signals is expected to be received. A plurality of time differences is determined where each of the time differences is based on a difference between receipt of a completion signal and the respective phase signal generated at the time when the completion signal is expected to be received. A composite difference of the time differences is totaled.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: March 26, 2013
    Assignee: The Boeing Company
    Inventor: Thomas H. Friddell
  • Patent number: 8407454
    Abstract: There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time.
    Type: Grant
    Filed: June 3, 2012
    Date of Patent: March 26, 2013
    Assignee: Imagination Technologies, Ltd.
    Inventors: Morrie Berglas, Yoong Chert Foo
  • Patent number: 8397186
    Abstract: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: March 12, 2013
    Assignee: Synopsys, Inc.
    Inventor: Jeffrey T. Brubaker
  • Patent number: 8392644
    Abstract: A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 5, 2013
    Assignee: MIPS Technologies, Inc.
    Inventors: Erik K. Norden, David Yiu-Man Lau, James H. Robinson
  • Patent number: 8386704
    Abstract: A host operating system (OS) can function as a task under a disk drive operating system. The host OS and the disk drive operating system can be run on a single processor. The processor is able to maintain the real-time response characteristics of a disk drive controller. A shared memory subsystem can be accessed by both operating systems. A disk drive storage device can access and respond to metadata about an underlying file system maintained by a host operating system (OS) to optimize data transfers between the disk drive and the host OS. The disk drive can identify the nature of read/write accesses, allowing it to prioritize and performance optimize the accesses. The disk drive can perform these functions without any changes to the block interface.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: February 26, 2013
    Assignee: HGST Netherlands B.V.
    Inventor: David Robison Hall
  • Patent number: 8381040
    Abstract: A relocatable interrupt handler for use in test generation and execution. A method for executing test code includes executing a test code block that includes a plurality of test instructions. The executing includes, for one or more of the test instructions: executing the test instruction; determining that the executing the test instruction caused an exception condition to occur; executing first exception handling logic associated with the exception condition based on determining that the executing the test instruction caused the exception condition to occur, the first exception handling logic located at an entry address consisting of a first memory address value, the executing the first exception handling logic including: clearing the exception condition; and changing the entry address to a second memory address value that is an address of a second exception handling logic. A return code that indicates a result of executing the test code block is then generated.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eli Almog, Timothy J. Slegel
  • Patent number: 8379644
    Abstract: A system and method of processing management frames implement a switching strategy that supports an interface between a generic device and a distributed switching architecture enabled switch. Control or management frames may be identified and processed independent of ordinary network traffic.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: February 19, 2013
    Assignee: Marvell International Ltd.
    Inventor: Donald Pannell
  • Publication number: 20130024676
    Abstract: In at least some embodiments, a processor in accordance with the present disclosure is operable to enforce control flow integrity. For examiner, a processor may comprise logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Inventors: Andrew F. Glew, Daniel A. Gerrity, Clarence T. Tegreene
  • Patent number: 8359602
    Abstract: The present disclosure is directed to a method and system for task switching with inline execution. In accordance with a particular embodiment of the present disclosure, a first state and a second state are identified for a function executing in the first state. A switch routine is invoked at a particular execution point in the function. A work element is generated in the switch routine. The work element includes status information for the function. The work element is transmitted to at least one alternate state task. The first state is altered to the second state according to the work element. Execution of the function in the second state is resumed at the particular execution point.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: January 22, 2013
    Assignee: CA, Inc.
    Inventor: Howard Israel Nayberg
  • Publication number: 20120317403
    Abstract: A multi-core processor system has a first core executing an OS and multiple applications, and a second core to which a first thread of the applications is assigned. The multi-core processor system includes a processor configured to receive from the first core, an interrupt signal specifying an event that has occurred with an application among the applications, determine whether the event specified by the received interrupt signal is any one among a start event for exclusion and a start event for synchronization for the first thread currently under execution by the second core, save from the second core, the first thread currently under execution, upon determining the specified event to be a start event, and assign a second thread different from the saved first thread and among a group of execution-awaiting threads of the applications, as a thread to be executed by the second core.
    Type: Application
    Filed: August 22, 2012
    Publication date: December 13, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Koichiro YAMASHITA, Hiromasa YAMAUCHI, Kiyoshi MIYAZAKI
  • Patent number: 8316220
    Abstract: Processors, data structures and methods for operating two or more processors over a network are disclosed. A processor can load, store and save information relating to the operation of one or more of its secondary processors in a unit of migration that includes either contents of exclusively associated memories of two or more secondary processors related to the execution state of a suspended process or contents of exclusively associated memories of one or more secondary processors related to the execution state of a suspended process and shared initialized data for the process. Such a unit of migration may be embodied in a processor readable medium.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: November 20, 2012
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Tatsuya Iwamoto
  • Patent number: 8296552
    Abstract: In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventors: Gautham Chinya, Robert Geva, Robert Knight, Hong Wang, Xiang Zou
  • Patent number: 8296551
    Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: October 23, 2012
    Assignee: VMware, Inc.
    Inventor: Edouard Bugnion
  • Patent number: 8291202
    Abstract: Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 16, 2012
    Inventors: Daren Eugene Streett, Brian Michael Stempel
  • Patent number: 8286192
    Abstract: A system for handling performance counters and events includes an operating system that receives a request of a first application for performance data associated with a type of event to be performed by a second application, causes a hardware counter pertaining to the event type to be activated, and provides a file descriptor corresponding to the hardware counter to the first application. The operating system then receives a second request of the first application for a value of the hardware counter, where the second request includes the file descriptor, and provides the value of the hardware counter to the first application.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: October 9, 2012
    Assignee: Red Hat, Inc.
    Inventors: Ingo Molnar, Thomas Gleixner