Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

Abstract: An input/output control device includes: a bus connected to an input interface; a plurality of circuit selectors which are connected to the bus and to which validity or invalidity of an operation is set, each circuit selector outputting a signal of the bus when the validity is set; a plurality of logical circuits which are respectively provided to each of the circuit selectors, each logical circuit performing a logical operation when a signal is inputted from the circuit selector; an output selector which is connected to the bus and to which validity or invalidity of an operation is set, the output selector outputting a signal of the bus to an output interface when the validity is set; and an operation part which validates or invalidates the plurality of circuit selectors or the output selector based on an operation order of the plurality of circuit selectors and the output selector.

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract: In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the internal combustion engine, the control unit includes a selecting unit, that selects at least one core used in the computation from among the plurality of cores, a computing unit that distributes the tasks to the at least one core selected by the selecting unit to perform computation, and an acquisition unit that acquires an engine, rotational speed of the internal combustion engine, and, when the engine rotational speed acquired by the acquisition unit is higher than or equal to a predetermined threshold, the selecting unit increases the number of the cores selected as compared with when the acquired engine rotational speed is lower than the predetermined threshold.

Abstract: A nested hierarchical plurality of microcoded compute engines where each successive compute engine is coupled to a source bus and a sink bus of another microcoded computed engine at a different hierarchical level, where one microcoded compute engine may be a replacement of a scratchpad memory or FIFO from a pre-existing design. A communication scheme for communicating between and within various hierarchical layers of microcoded compute engines and a piano roll of bitmapped barrier objects for synchronizing activities of various microcomputer engines.

Abstract: Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and combined for the TSC region. Binary optimization operations may be performed on the TSC region to enable the code to run more efficiently by, for example, reordering load and store instructions. In the first stage, load operations in the region may be committed atomically and in the second stage, store operations in the region may be committed atomically.

Abstract: A method and apparatus for utilizing scheduling resources in a processor are disclosed. A complex operation is assigned for execution as two micro-operations; a first micro-operation and a second micro-operation. The first micro-operation, which may be an address-generation operation, is executed using at least one of a first processing unit or a load and store unit and the second micro-operation, which may be an execution operation, is executed using a second processing unit, where at least one operand of the second micro-operation is an outcome of the first micro-operation.

Abstract: An integrated circuit is disclosed wherein microinstructions are selectively queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a selected subset of a set of supported microinstructions. The execution unit receives microinstruction data including an operation code OpCode and an operation type OpType. The OpType data being at least one bit less that a minimum binary size of an OpCode required to uniquely identify the microinstruction. The OpType data selected to indicate a category of microinstructions having common execution requirement characteristics. The microinstructions are selectively queued for pipeline processing by the execution unit pipelines based on the OpType without decoding the OpCode of the microinstruction.

Abstract: Apparatus, systems and methods for speculative scheduling of uops after allocation are disclosed including an apparatus having logic to schedule a micro-operation (uop) for execution before source data of the uop is ready. The apparatus further includes logic to cancel dispatching of the uop for execution if the source data is invalid. Other implementations are disclosed.

Abstract: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.

Abstract: A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware engine performs operations and computations on data as the data traverses paths through the functional units under control of software. The functional units include logic resources, examples of which are flip-flops, latches, arithmetic logic units, random access memory, and the like. The routing units are responsive to the software control signals that are turned on or off to steer the data through these resources. Operations and computations are accomplished according to the steering of the data through the functional units that control the functions performed.

Abstract: In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a processor. This sequence of operations, including instructions from the plurality of sets of operations, ensures that there is another operation in the pipeline if a cache miss on any given lookup operation in the mapping array results in a slower main memory access. In this way, the processor utilization is improved. While the sets of operations in the sequence of operations are independent of another other, there will be an overlap of a plurality of the main memory access operations due to the long time required for main memory access.

Abstract: A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcontroller also has a control circuit that, by storing the next few program instructions internally before placing the memory in standby, or by delaying the interrupt signal, provides extra time for memory operation to stabilize on exit from the standby mode. Malfunctions on recovery from standby are thereby prevented, and the microcontroller can conserve power by placing the memory in a deep standby mode with a comparatively long recovery time.

Abstract: A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices of the corresponding consecutive areas, and checks whether or not devices of consecutive areas are within a range of devices stored in the storage unit. The device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices of the corresponding consecutive areas, and checks whether or not devices of consecutive areas are within a range of devices stored in the storage unit.

Abstract: A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices of the corresponding consecutive areas, and checks whether or not devices of consecutive areas are within a range of devices stored in the storage unit. The device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices of the corresponding consecutive areas, and checks whether or not devices of consecutive areas are within a range of devices stored in the storage unit.

Abstract: In a computer processor, a low-order portion of a virtual address for a pipelined operation is compared directly with the corresponding low-order portions of addresses of operations below it in the pipeline to detect an address conflict, without first translating the address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and a translation lookaside buffer (TLB) for determining the high-order portion of a real address. The comparison of low-order address portions provides conflict detection before the TLB can translate a real address of an instruction.

Abstract: A programmable controller for controlling a multi-channel sequential processing of states based on a prescribed state transitions. The microcontroller has a state register for each of the channels for holding the state data to be processed in the channel in the next processing period, and upon receipt of a sampling clock and a channel processing request, executes a program to process the states in each of the channels based on the states data held in the associated state register. The microcontroller may execute a program having a complex sequence in a reduced number of steps.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: A device, method and computer program for communicating between a device controller and an industry standard bus. This device method and computer program requires no modification of the core logic of the device driver even though the data and commands transmitted between the device controller and the bus require a different format and different length commands. This device utilizes a convert and store logic unit to convert commands from the core unit to a reduced bit format suitable for the industry standard bus.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.

Abstract: A computer instruction includes a command instruction to issue a memory reference to an address in a memory shared among threads executing in microprocessors while a context of a thread is inactive.

Abstract: A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description language (HDL) based designs into a set of logic equations and single bit arithmetic-logic operations executed by a set of parallel operating sequencers. The system includes software for converting netlists and HDL designs into Boolean logic equations, and a compiler for distributing these logic equations between multiple sequencers. Each sequencer is comprised of a logic processor and the associated program memory for storing the executable code of the assigned Boolean logic equations and data memory for storing the results of processing of logic equations. To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register.

Abstract: An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes multiple data elements at the same time, and yet is programmed with readable assembly language and requires neither vector registers nor a lot of extra registers to implement.

Abstract: A CODEC has a DSP which can consecutively execute a plurality of algorithms without restriction of a memory capacity. The DSP performs an encoding/decoding operation on a digital signal. A program memory stores a program divided into a plurality of block programs, the program being stored on an individual block program basis. A data memory stores a set of data used for executing each block program stored in the program memory, the set of data being divided into a plurality of data blocks and stored on an individual data block basis. A program executing unit executes each block program stored in the program memory by using a corresponding data block stored in the data memory. A program changing unit obtains a new block program from an external device each time execution of one of the block programs by the program executing unit is completed so as to store the obtained new block program in the program memory.

Abstract: A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit.

Abstract: A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space.

Abstract: One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.

Abstract: A signal processor stores at least one microprogram having m steps in total smaller in number than n steps which are to be executed within one sampling repetition period. A count corresponding to each of the n steps are generated. M steps of the at least one microprogram stored is executed a plurality of times within the one sampling repetition period to thereby execute the n steps.

Abstract: A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Abstract: A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The pre-verification function, contained within CPU execution unit microcode, sets a return value in a program status word to indicate one of four conditions:1. The target instruction is present and operable;2. The target instruction is present in the computer system, but unavailable on this central processor (e.g. an asymmetric feature).3. The target instruction is not present in this computer system.4. The TSTOP op-code is recognized, but the target instruction presence cannot be determined.The return value is testable by the program issuing the TSTOP instruction to determine whether the target instruction should be issued.