Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module prefixes non-data bits to the frame header to shift the IP payload into a position in the memory regions such that the IP payload is aligned with the memory boundaries. The number x of non-data bits is determined according to x=m*c+p, where m is the bit depth of memory regions, n is the length of a header, p is the non-zero remainder of the ratio n/m, and c is an integer.

Abstract: An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post processor to transfer a shift carry operand stored in the register to the shift post processor, and coupled to the shifter to store the shifted operand after any transfer of the shift carry operand. The shift post processor is coupled to the shifter and the register to process the shifted operand to generate an output based on at least a control signal and a mask field. The shift post processor comprises a decoder to decode the offset parameter into the mask field, the mask field having a plurality of mask bits, each of the mask bits corresponding to a bit position of the shifted operand.

Abstract: A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruction. Only a limited number of bits are required to index into the table during the execution of this instruction. The remaining bits of each index are used as masks into a series of select instructions. The select instruction chooses between two vector components, based on the mask, and places the selected components into a new vector. The mask is generated by shifting one of the higher order bits of the index to the most significant position, and then propagating that bit throughout a byte, for example by means of an arithmetic shift. This procedure is carried out for all of the index bytes in the vector, to generate a select mask.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a coprocessor targetted by the coprocessor instructions. After determining whether to alternatively load source values into a respective one of two source registers, new source values are transferred to one or more of the source registers. The coprocessor executes the coprocessor instruction, which includes an offset information, to extract values from the source registers based on the offset information and places the values in a destination register.

Abstract: A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. In an ESET function, data fields in respective source packets are copied to adjacent data fields in a result packet governed by a field locator packet. In an EXTRACT function, data fields in a source packet are copied to adjacent data fields in a result packet governed by a field locator packet. In a SCATTER function, adjacent data fields in a source packet are copied to data fields in respective result packets governed by a field locator packet.

Abstract: A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits within that destination value being unaltered.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting device are analyzed, and dividing device for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting device to the corresponding channels is provided based on the analysis result.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.

Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.

Abstract: A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instruction. The bit extraction instruction includes copying the size value number of bits from the accumulator beginning at the position value into a target register, setting any remaining bits of the target register to zero, and decrementing the position value by an amount based on the size value. The method may include loading bits from a bit stream into a register and moving the contents of the register into the accumulator to replenish the accumulator. The method may include determining, based on the position value, whether the accumulator needs to be replenished, and if not, branching to bypass replenishing functions.

Abstract: This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane form. This enables downstream algorithms to read only the data for the bit plane of interest. This greatly reduces the memory bandwidth bottleneck and opens many new optimization pathways.

Abstract: A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.

Abstract: Methods and systems for feature selection are described. In particular, methods and systems for feature selection for data classification, retrieval, and segmentation are described. Certain embodiments of the invention are directed to methods and systems for complement sort-merge tree (CSMT), fast-converging sort-merge tree (FSMT), and multi-level (ML) feature selection. Accurate and fast results may be obtained by the feature selection methods and systems described herein.

Abstract: Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and a second subset of data of less than n bits are selected, by logical shifting, from the two registers, respectively, based solely upon the shift value. Then, the subsets are concatenated, preferably by a logical OR, to obtain an output of n bits. The output may be aligned data or packed data, particularly useful for performing a single operation on multiple sets of the data through parallel processing with a SIMD processor.

Abstract: An image transmission device and methods a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting device are analyzed, and dividing device for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting device to the corresponding channels is provided based on the analysis result.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting are analyzed, and dividing for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting to the corresponding channels is provided based on the analysis result.

Abstract: A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing data from a data source into a data unit, and changing a sequence of the data unit for outputting data selected by a byte-operation, a sign extender controlled by the control signals for outputting the selected data and converting any non-selected data to a sign value, and a bus selection circuit controlled by the bus selection signals to select a bus among a plurality of buses and to load the selected bus with data outputted from the sign extender.

Abstract: A data processing system is provided with an instruction (PKH) that combines a packing operation of respective portions of input operand data words (Rn, Rm) into an output data word (Rd) together with the ability to select one of the portions to be combined from a variable position (k) within its respective input operand data word in a manner that allows additional processing to be carried out together with the packing operation. The instruction conveniently combines either the top or bottom half of one of the input operand data words with a half data word portion selected from a variable position within the other input operand data word.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, including a step of loading a first part of the unaligned data into a first storage location and rotating the first part from a first position to a second position in the first memory location. Next a second part of the unaligned data is loaded into a second storage location and rotated from one position to another position. Then the first storage location is combined with the second storage location using a logical operation into a result storage location. The storage locations may be, for example, 64-bit registers. The logical operation may be a bit-wise OR operation.

Abstract: A storage server uses a semantic processor to parse and respond to client requests. A direct execution parser in the semantic processor parses an input stream, comprising client storage server requests, according to a defined grammar. A semantic processor execution engine capable of manipulating data (e.g., data movement, mathematical, and logical operations) executes microcode segments in response to requests from the direct execution parser in order to perform the client-requested operations. The resulting operational efficiency allows an entire storage server to be collapsed in some embodiments into a few relatively small integrated circuits that can be placed on a media device's printed circuit board, with the semantic processor itself drawing perhaps a few Watts of power.

Abstract: Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier.

Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Inernet Protocol) packets as payloads. The alignment module prefixes dummy bytes to the frame header to shift the IP payload into an aligned position in the memory regions of the memory.

Abstract: The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values.

Abstract: A given software process is composed on one or more threads of execution. Each thread possesses its own stack, a region of memory set aside by the operating system for that thread to store data. Popular programming languages rely heavily on stack-based data (frequently referred to as “local” or “automatic” data). It is a characteristic of deterministic machines like computers that, given the same problem to process with the same data, the same results, both intermediate and final, will result. This even extends to the sequence the software running on the computer will take to process the problem or data. This in turn means that for each thread making up the program, the data layout in the thread's stack will be relatively consistent each time the program gets to a similar point in the processing of the problem and/or data. This represents a potential “point of repeatability” that a hacker can take advantage of.

Abstract: A computer system and object-oriented method and class for use with the computer system to convert data in Unicode format back and forth to data having a fixed-length format, such as EBCDIC, and to allow editing of the data and return the edited data back to its original format without loss of bytes. Conversely, the method, class, and computer system also allow the downloading of data in a fixed-length format into a Unicode environment, the fixed-length format is converted into an editable form and then reconverted back into the fixed-length format without loss of bytes. The method accommodates UTF-8, UTF-16, and UTF-32. Once the fixed-length of the data has been determined, a byte array is created and an attribute indicating whether a character is a single byte character or a double-byte character is assigned to each byte in the array.

Abstract: An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is shuffled into the upper half of a destination register. In another embodiment, one of the data elements in the lower half of the data operand is shuffled into the lower half of a destination register.

Abstract: A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array.

Abstract: A data byte insertion circuit includes circuitry to generate derivative intermediate data words from input data words of a current and a preceding cycle, repositioning data bytes of the input data words before and after data byte insertion points of the current and preceding cycles, and circuitry to generate re-aligned variants of insertion data bytes of the current cycle. The data byte insertion circuit further includes circuitry to generate a number of multi-bit data bit selection masks, and circuitry to generate an output data word by conditionally using selected parts of the derivate intermediate data words and the re-aligned variants of the insertion data bytes, in accordance with the multi-bit data bit selection masks.

Abstract: The dynamic switching of a bi-endian processor between endian modes is described. A device having the bi-endian processor may also have an endian select circuit. The endian select circuit may receive a signal from the processor that determines what the endian-ness should be after the processor resets. Special instruction code may be executed by the processor in both little and big endian modes. The special instruction code may, for instance, cause a processor in a first endian mode to output a signal and reset, while the same instruction code may cause a processor in a second endian mode to neither output the signal nor reset. Instead, the processor in the second endian mode may jump to a new instruction address and proceed with normal processing.

Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.

Abstract: A method and system of configuring an array of data is disclosed. The method and system comprise generating an array of data an order and reconfiguring the array of data into a plurality sub arrays of data, the plurality of sub arrays of data being in a desired order. By utilizing the method and system in accordance with the present invention, a converted data array can be processed in a parallel fashion thereby increasing the overall processing speed of the computer system. The present invention has particular utility when converting data either from a bit reverse order to a natural order or from a natural order to a bit reverse order. In accordance with the present invention, the array of data is reconfigured utilizing a swap operation to allow for conversion of the data array from either a bit reverse order to a natural order or from a natural order to a bit reversed order.

Abstract: A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting device are analyzed, and dividing device for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting device to the corresponding channels is provided based on the analysis result.

Abstract: Performing repeat string operations can include aligning a source data location or a destination data location to a location divisible by a predetermined integer, the aligning including performing a string operation using data having a size equal to the operand size. After aligning, a string operation can be performed using data having a size larger than the operand size. Performing repeat string operations can include issuing a first predetermined number of iterations if an operand size is a predetermined size, and issuing a second predetermined number of iterations otherwise. Performing repeat string operations can include determining that a requested number of iterations in a repeat string operation is within a predetermined multi-number range and issuing exactly the requested number of iterations for any value of the requested number within that range.

Abstract: A chipset is initialized in a secure environment for an isolated execution mode by an initialization storage. The secure environment has a plurality of executive entities and is associated with an isolated memory area accessible by at least one processor. The at least one processor has a plurality of threads and operates in one of a normal execution mode and the isolated execution mode. The executive entities include a processor executive (PE) handler. PE handler data corresponding to the PE handler are stored in a PE handler storage. The PE handler data include a PE handler image to be loaded into the isolated memory area after the chipset is initialized. The loaded PE handler image corresponds to the PE handler.

Abstract: Executing digital signal processing (DSP) instructions in a digital signal processor integrated circuit comprising receiving a DSP instruction in digital signal processor integrated circuit to process one or more complex number operands; fetching a first operand with a first data type, the first operand having real and imaginary values with a complex data type; fetching a second operand with a second data type; prior to executing a DSP operation, determining a permutation of the first operand, the second operand, or both the first operand and the second operand, and permuting instances of the first operand, the second operand, or both the first operand and the second operand to execute the DSP operation; and executing the DSP operation in the digital signal processor integrated circuit using the first operand and the second operand to obtain a result, the result having real and imaginary values with a complex data type.

Abstract: A system and a method for transcoding multiple media channels are provided. The system includes a first processor to parse a media data stream having one or more media data channels and a vector processor to decompress, scale, and then compress the parsed media channel. A parsed media data channel, in one embodiment, is accessed using a bit manipulator and packetized into decoder instruction packets and transmitted to the vector processor using a sequencer. The vector processor decompresses the decoder instruction pacets, scales a macroblock generated from the packets, and then compresses the scaled macroblock. As a result, the scaled and compressed output has less data associated with the media channel, allowing for faster and/or more efficient storage or transmission. A reduced sized scale buffer is associated with another disclosed embodiment.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting means are analyzed, and dividing means for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting means to the corresponding channels is provided based on the analysis result.

Abstract: In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is made, based on the conditions, as to whether or not to process the request. To facilitate the invention, certain bit fields within the instruction are encoded to identify the request as speculative or not. Additional bit fields may define a priority of a speculative request to influence the decision to process as based on the conditions. CPU architectures incorporating prefetch logic may be modified to recognize instructions encoded with speculation and priority identification fields to implement the invention in existing systems. Other logic, e.g., bus controllers and switches, may similarly process speculative requests to enhance system performance.

Abstract: There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.

Abstract: A method for a byte swap operation on a 64 bit operand. The method of one embodiment comprises accessing an operand stored in a register. The operand is comprised of a plurality of bytes of data. A first set of bytes located in an upper half of said register is reordered. A second set of bytes located in a lower half of said register is reordered. The first set of bytes is swapped with the second set of bytes, wherein the first set of bytes is relocated to the lower half of the register and the second set of bytes is relocated to the upper half of the register.

Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.

Abstract: A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.

Abstract: A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple mapping elements. Each of the multiple mapping elements is applied to the inputs of a different one of multiple digital multiplexers. The bitmask returned by the SIMD compare instruction is applied to the selects or all of the multiple digital multiplexers. Each multiplexer outputs one bit, as selected by the bitmask, from the respective mapping element applied to each multiplexer. The one bit outputs are accumulated in a mapped output variable as a mapped bitmask.

Abstract: A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruction. Only a limited number of bits are required to index into the table during the execution of this instruction. The remaining bits of each index are used as masks into a series of select instructions. The select instruction chooses between two vector components, based on the mask, and places the selected components into a new vector. The mask is generated by shifting one of the higher order bits of the index to the most significant position, and then propagating that bit throughout a byte, for example by means of an arithmetic shift. This procedure is carried out for all of the index bytes in the vector, to generate a select mask.

Abstract: A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.