Abstract: The present disclosure is directed to a processing system with a virtualized graphics processor for highly parallel processing of graphics tasks as well as other computing tasks. The processing system includes a central processing unit (CPU) configured with a virtualization stack which includes a graphics processing unit (GPU) having hundreds to thousands of GPU cores virtualized into virtual machines (VMs). The GPU cores are loaded with low-level programming routines for graphics tasks. Different GPUs are loaded with different types of programming routines based on their respective dedicated graphics tasks. The cores are segmented into VMs based on the graphics task. By utilizing virtualized GPUs, highly parallel processing of graphics tasks can be achieved.

Abstract: Provided are a method and apparatus for operating a blockchain system, a device and a storage medium. The method is described below. To-be-processed blockchain data is acquired through a kernel engine of a blockchain system. The to-be-processed blockchain data is processed through the kernel engine, and a kernel component interface provided by a component adaptor is called during the processing process of the to-be-processed blockchain data to call a kernel component.

Abstract: An information providing method of an electronic apparatus is disclosed. The information providing method may include receiving a counter information request, identifying cache counter information corresponding to the counter information request from a cache database related to a counter, and transmitting response information corresponding to the counter information request based on the identified cache counter information.

Abstract: An information handling system, method, and processor that detects a store instruction for data in a processor where the store instruction is a reliable indicator of a future load for the data; in response to detecting the store instruction, sends a prefetch request to memory for an entire cache line containing the data referenced in the store instruction, and preferably only the single cache line containing the data; and receives, in response to the prefetch request, the entire cache line containing the data referenced in the store instruction.

Abstract: A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder circuitry 24 which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.

Abstract: A microcontroller includes a plurality of primary registers, a secondary register and a central processing unit (CPU). The primary registers store a plurality of primary data respectively. Each primary data has a first width. The secondary register includes the plurality of primary registers and stores a secondary data having a second width. The secondary data includes a combination of the plurality of primary data. The CPU executes a first instruction in a first mode in which a primary data is fetched for operation and executes a second instruction in a second mode in which the secondary data is fetched for operation.

Abstract: An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory.

Abstract: A design structure for performing cacheline polling utilizing store and reserve and load when reservation lost instructions is disclosed. In one embodiment a method is provided which comprises storing a buffer flag busy indicator data value within a first cacheable memory location and setting a load/store operation reservation on said first cacheable memory location via a store and reserve instruction. In the described embodiment, a data value stored within the first cacheable memory location is accessed via a conditional load instruction in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset. Conversely, execution of the conditional load instruction is stalled in response to a determination that the load/store operation reservation on the first cacheable memory location has not been reset.

Abstract: A method and system for processing data. In one embodiment, the method includes receiving a plurality of stores into a store queue, where each store is a result from a processor, and where the plurality of stores are destined for at least one memory address. The method also includes marking a most recent store of the plurality of stores for each unique memory address, comparing a load request against the store queue, and identifying only the most recent store for each unique memory address for the purpose of handling load-hit-store ordering hazards.