Abstract: A power feed system includes a computer that evaluates benefit obtained when a power feed mat is placed, for each of a plurality of locations within a subject region where the power feed mat can be placed, the power feed mat being configured to wirelessly feed power to a movable body. In a power feed method using such a computer, a display shows a result of evaluation of the benefit for each location within the subject region evaluated by the computer.

Abstract: A power and data connectivity micro grid includes a first power sourcing equipment device having first and second power ports and first and second data ports, and configured to deliver DC power signals to the first and second power ports. The micro grid further includes first and second remote distribution nodes, and first and second splice enclosures, each splice enclosure having a power input port, a data input port, a power tap port, a data tap port, a power output port and a data output port. A first composite power-data cable is coupled between the first power port and the first data port of the first power sourcing equipment device and the power input port and the data input port of the first splice enclosure. A second composite power-data cable is coupled between the second power port and the second data port of the first power sourcing equipment device and the power input port and the data input port of the second splice enclosure.

Abstract: Aspects of the disclosure include a non-transitory computer-readable medium storing computer-executable instructions for controlling at least one uninterruptible power supply (UPS) configured to provide power to at least one server executing one or more services, the instructions instructing at least one processor to receive an indication of the services initiating a shutdown procedure, determine that a predicted shutdown time (PST) of the shutdown procedure exceeds a baseline shutdown time (BST) to perform the shutdown procedure, the BST being less than an available runtime of the UPS, control the UPS to continue providing power to the server responsive to determining that the PST is less than the available runtime and that the PST exceeds the BST, receive an indication that the shutdown procedure is successfully executed over an actual shutdown time (AST), and update the BST responsive to determining that the AST is different than the BST.

Abstract: A sensor assembly includes a housing that defines an interior space. The sensor assembly includes a sensor connected to the housing at the aperture. The sensor assembly includes a wireless power source disposed within the interior space. The sensor assembly includes electronics disposed within the interior space and configured to receive power from the wireless power source. The electronics include a communication board and a sensor connector, and the sensor is configured to transmit data to the communication board via the sensor connector.

Abstract: An example single-board computer cartridge is provided that includes a housing, a single-board computer, a Power-over-Ethernet receptacle, and a power conversion circuit board. The housing includes a front surface and a rear surface on opposing sides of the housing. The single-board computer is disposed within the housing and includes at least one data output port, the at least one data output port oriented to face the front surface of the housing. The Power-over-Ethernet receptacle is disposed within the housing and is oriented to face the rear surface of the housing. The power conversion circuit board is disposed within the housing. The power conversion circuit board is electrically connected to the single-board computer and the Power-over-Ethernet receptacle such that power and data input are provided to the single-board computer from the Power-over-Ethernet receptacle.

Abstract: A power conversion module is disclosed. The power conversion module includes a power conversion module includes a circuit board and a first basic power unit. The first basic power unit is disposed on the circuit board and includes a magnetic device, a primary switch circuit, a first secondary rectifying circuit and a first positive output terminal pin. The primary switch circuit, the first secondary rectifying circuit, the magnetic device and the first positive output terminal pin are sequentially arranged on the circuit board along a first direction.

Abstract: A power distribution system is provided in this application, which includes a plurality of power distribution equipments, and the plurality of power distribution equipments are configured to supply power to a plurality of powered devices respectively. First power distribution equipment in the plurality of power distribution equipments includes: a first power module, configured to perform voltage conversion on an input voltage to obtain an output voltage, where the output voltage is a supply voltage of the first power distribution equipment; and a first cascading circuit, configured to connect an output of the first power module to an output of a power module in power distribution equipment in the power distribution system other than the first power distribution equipment, where the first power distribution equipment is any power distribution equipment in the power distribution system. A server system which includes the power distribution system is also disclosed in this application.

Abstract: A high-reliability multiphase power supply system and method. A second processing unit is configured with a first field-effect transistor, a drain electrode of the first field-effect transistor is connected to a power supply, a source electrode of the first field-effect transistor is connected to the drain electrode of a second field-effect transistor, the source electrode of the second field-effect transistor is connected to ground, and the gate electrodes of the first field-effect transistor and the second field-effect transistor are connected to a first processing unit; the second processing unit is configured with a first current detection module and a second current detection module, the first current detection module and the second current detection module are electrically connected to a bus unit, and the bus unit is electrically connected to a substrate management controller.

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Abstract: A system of at least two units that transmit and/or receive a signal at a first or a second frequency, respectively, each of the units being individually connected to the antenna, which is common to a first branch and to a second branch, respectively. The first branch or the antenna includes first passive electronics preventing passage of the signal at the second frequency to the first unit and allowing passage of the signal at the first frequency to the antenna. The second branch or the antenna includes second passive electronics preventing passage of the signal at the first frequency to the second unit and allowing passage of the signal at the second frequency to the antenna.

Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

Abstract: The present disclosure provides a power management method, a multi-processing unit system, and a power management module thereof. The multi-processing unit system comprises a plurality of local power management units and a global power management unit, each of the local power management units corresponds to a processing unit of the multi-processing unit system. The power management method comprises: obtaining, using the global power management unit, a global power budget for the multi-processing unit system; allocating, using the global power management unit, local power budget for each of the local power management units according to the global power budget and power management parameters of the processing units; managing, using the local power management unit, local power resources of corresponding processing unit based on the allocated local power budget; reporting, using the local power management unit, the power management parameters of the processing unit to the global power management unit.

Abstract: Methods and apparatus for thermal management in data storage devices are provided. One such data storage device includes a non-volatile memory (NVM), at least one ambient temperature sensor configured to detect an ambient temperature of the data storage device, at least one component temperature sensor configured to detect one or more component temperatures of one or more components of the data storage device, and a processor coupled to the NVM, the at least one ambient temperature sensor, and the at least one component temperature sensor. The processor is configured to determine a composite temperature of the data storage device based on the one or more component temperatures and the ambient temperature. The processor is further configured to determine whether the composite temperature exceeds a threshold and perform a thermal management operation if the composite temperature exceeds the threshold.

Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.

Abstract: A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element.

Abstract: A system and/or method can include power of Ethernet (PoE) controller including a PoE interface, a device interface and a controller, communicatively coupled to the PoE interface and the device interface. The controller can be configured to receive device control information via the PoE interface and to generate control instructions in response to the device control information for the device interface.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: According to one embodiment, a memory system includes first, second, and third controllers. The first/second controller sets a first/second link to an operating or low power consumption state. The third controller sends a busy signal to the first and second controllers when transfer of a packet via the first or second link is predicted. When the first link is in the low power consumption state and a packet has not been received via the first link, the first link is maintained in the low power consumption state by disabling the busy signal. When the first link is in the operating state and a packet has not been received via the first link, the first link is transitioned to the low power consumption state upon absence of packets transferred via the first link for a first period of time, by disabling the busy signal.

Abstract: A facility implementing systems and/or methods for achieving energy consumption/production and cost goals is described. The facility identifies various components of an energy system and assesses the environment in which those components operate. Based on the identified components and assessments, the facility generates a model to simulate different series/schedules of adjustments to the system and how those adjustments will effect energy consumption or production. Using the model, and based on identified patterns, preferences, and forecasted weather conditions, the facility can identify an optimal series or schedule of adjustments to achieve the user's goals and provide the schedule to the system for implementation. The model may be constructed using a time-series of energy consumption and thermostat states to estimate parameters and algorithms of the system.

Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.

Abstract: A method and system for intelligent power distribution management. Specifically, the disclosed method and system propose allocating (and deallocating) reserve or supplemental electrical power to host devices dynamically based on intelligent analyses of host device telemetry including, but not limited to, workload criticality, workload computing resource utilization, hardware configuration metadata, various operational parameters describing host device state, and measurements (as well as other information) pertinent to electrical power usage.

Abstract: A multi-port power supply device and an operation method thereof are provided. The multi-port power supply device includes a power converter, a power switch, a current detection circuit, a voltage detection circuit, a control circuit, and multiple USB ports. The power converter supplies power to a USB port via a current path. The control circuit determines whether the USB port is connected to a USB device according to an actual voltage of the current path. When the USB port is not connected to the USB device, the control circuit turns off the current path. When the USB port is connected to the USB device, after a part of a power of other USB ports is dynamically transferred to the USB port, the control circuit determines whether to turn on the current path according to an actual current of the current path.

Abstract: One or more external connectors of a conformal wearable battery (CWB) may be controlled to reduce a voltage potential supplied to the connectors when exposed to a conductive liquid. The connectors may be uniform serial bus (USB) connectors or other connectors. One or more unused terminals of the one or more connectors may be pulled to a voltage potential and then monitored for a change in voltage. When the change in voltage satisfies a voltage threshold, the voltage potential supplied to the one or more connectors may be reduced and/or interrupted. The change in voltage may be evaluated against the voltage threshold alone or may be evaluated against the voltage threshold and a time threshold relating to a time after the voltage satisfied the voltage threshold. The voltage of the monitored terminal may be evaluated against one or more voltage thresholds and/or one or more time thresholds. Based on the voltage threshold having been met, the voltage supplied to the connector may be reduced or stopped.

Abstract: A system, topology, and methods for testing a POE signal downstream from a POE source and configuring a POE device remotely including wired and wireless system for providing signals from remote POE device while providing power to the POE device.

Abstract: An information processing method is provided to reduce an amount of data to be monitored in an onboard system of a vehicle. In the method, detection results that indicate whether an abnormality is included in communication data on an onboard network are obtained, and a first log transmission instruction is generated to cause periodic transmission of a first log from the onboard system to a server device. The first log is a log of some of the communication data. A second log transmission instruction is generated to cause transmission of a second log from the onboard system to the server device in a case of the detection results indicating the abnormality is included in the communication data. The second log is a log of more of the communication data than the first log.

Abstract: Power management device and method for a consumer product are provided. The power management device includes a memory, a configuration channel interface circuit and a control circuit. When a power supply device is electrically connected to a connector of the consumer product, the control circuit performs a power delivery protocol conforming to a USB specification on the power supply device through the configuration channel interface circuit and a configuration channel pin of the connector, so as to determine a power mode in which the power supply device supplies power to the consumer product. After the power delivery protocol is performed successfully, based on at least one protocol profile stored in the memory, the control circuit performs a vendor-defined messaging protocol on the power supply device through the configuration channel interface circuit and the configuration channel pin, so as to determine whether to change the power mode.

Abstract: A method is provided for dynamically controlling fan speed of a computing system during boot and reboot. The method may include receiving an ambient temperature from a sensor by a controller. The method may also include controlling speed for one or more fans dynamically based upon the ambient temperature using a dynamic algorithm during boot and reboot of the computing system. The dynamic algorithm may include a function for the fan speed of the one or more fans based upon the ambient temperature.

Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

Abstract: A rendering device signals a display device to capture and replay a current frame to maintain a static image while switching between multiple graphics processing units (GPUs) at a multiplexer (MUX). Replaying the current frame while the MUX switch is in progress smooths the user experience such that no screen blanking or artifacts are observable.

Abstract: The present disclosure provides a circuit including a coaxial cable interface, a data module, a power module, a power signal transmission branch, and a data signal transmission branch. The data module may receive or output a data signal. The power module may receive or output a power signal. The power signal transmission branch may be electrically coupled between the coaxial cable interface and the power module, and may include an inductor that allows the power signal to pass. The data signal transmission branch may be electrically coupled between the coaxial cable interface and the data module, and may include a capacitor that allows the data signal to pass and a first electrical surge protection circuit. The first electrical surge protection circuit may release a surge current on the data signal transmission branch.

Abstract: A system comprising a meter and a circuit breaker, the electricity meter comprising: a primary processing component designed to acquire a primary power supply parameter and to produce, from the primary power supply parameter, a primary command intended to control the opening or closure of a line; a primary transceiver designed to transmit the primary command; the circuit breaker comprising: a disconnection unit; a bistable relay designed to open or close the disconnection unit; a secondary receiver designed to receive the primary command; a secondary processing component designed to acquire the primary command and to control the bistable relay so as to open or close the disconnection unit on the basis of the primary command.

Abstract: Systems and methods for managing flow batteries utilize a battery management controller (BMC) coupled between a flow battery and a DC/DC converter, which is coupled to an electrical grid or a photovoltaic device via an inverter. The inverter converts an AC voltage to a first DC voltage and the DC/DC converter steps down the first DC voltage to a second DC voltage. The BMC includes a first power route, a second power route, and a current source converter coupled to the second power route. The BMC initializes the flow battery with a third DC voltage using the current source converter until a sensing circuit senses that the voltage of the flow battery has reached a predetermined voltage. The sensing circuit may include a capacitor, which has a small capacitance and is coupled across each cell of the flow battery, coupled in series between two resistors having very large resistances.

Abstract: A power/workload management system includes a power system that is coupled to a first computing device that is configured to perform a first workload, as well as to a second computing device. A management subsystem is coupled to the first computing device and the second computing device, and operates to identify a reduced power event associated with the power system and, in response, determine that the first computing device is associated with a higher power consumption than the second computing device. In response to determining that the first computing device is associated with the higher power consumption than the second computing device, the management subsystem moves the first workload to the second computing device such that the second computing device performs the first workload, and configures the first computing device in a reduced power consumption state.

Abstract: Various implementations described herein are directed to a device having a housing configured for mounting to a watercraft. The device may include a power interface configured to receive power from a power source. The device may include a network interface configured to receive marine data from a plurality of different data sources. The device may include a sonar interface configured to receive sonar data from a sonar device. The device may include a display interface coupled to the power interface, the network interface, and the sonar interface. The display interface may be configured to receive power from the power interface, receive marine data from the network interface, receive sonar data from the sonar interface, and provide power, marine data, and sonar data to a remote marine display that is separate from the device.

Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A coolant management unit for providing liquid cooling for backup battery unit (BBU) modules of an electronic rack includes a BBU return manifold, a BBU supply manifold, a balance loop, and a power bus. For example, a BBU supply manifold having a rack supply connector to receive cooling fluid from a rack supply manifold and a BBU supply connector to be connected to one of the BBU modules to distribute the cooling fluid. A BBU return manifold to be coupled to a rack return manifold, wherein the BBU return manifold is to receive vapor from the BBU modules. A balance loop connected to each of the BBU modules to establish a fluid connection amongst the BBU modules, such that a level of the cooling fluid in each of the BBU modules remains similar.

Abstract: A networked system includes a computing device having a central processing system and accelerator system(s). A central processor/accelerator power management system coupled to the computing device via a network operates to deploy workload(s) on the computing device and receive workload performance information from the computing device that identifies a central processing system utilization of the central processing system in performing the workload(s) and an accelerator system utilization of each accelerator system in performing the workload(s). Based on the workload performance information, the computing device determines a first power consumption ratio of the central processing system and the accelerator system(s) in performing the workload(s), and modifies operation of at least one of the central processing system and the accelerator system(s) to change the first power consumption ratio to a second power consumption ratio that is more power efficient than the first power consumption ratio.

Abstract: Systems and methods for intelligent data center power management and energy market disaster recovery comprised of data collection layer, infrastructure elements, application elements, power elements, virtual machine elements, analytics/automation/actions layer, analytics or predictive analytics engine, automation software, actions software, energy markets analysis layer and software and intelligent energy market analysis elements or software. Plurality of data centers employ the systems and methods comprised of a plurality of Tier 2 data centers that may be running applications, virtual machines and physical computer systems to enable data center and application disaster recovery from utility energy market outages.

Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.

Abstract: A power switching circuitry and ethernet apparatus using the same is provided. The power switching circuitry comprises an external power socket for receiving external power, an ethernet power supply pin for receiving power over ethernet, a sensing circuitry, and a power output decision module, and determines whether the power over ethernet is applied to an internal circuit in accordance with position variations of the socket pins of the external power socket.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory that includes multiple memory groups having independent power modes. The random access memory is configured to store data representative of parameters of an Artificial Neural Network and representative of instructions executable by the Deep Learning Accelerator to perform matrix computation to generate an output of the Artificial Neural Network. During execution of the instructions, a power manager may adjust grouping of memory addresses mapped into the memory groups and adjust power modes of the memory groups to reduce power consumption and to avoid performance impact.

Abstract: A device capable of self-detecting and self-allocating additional power and associated method are disclosed. The device includes a first module to route current from first power pins to a voltage rail having the first voltage level. The device includes a second module coupled to second power pins associated with a second voltage level. The second module routes current from the second power pins to the voltage rail having the first voltage level via a connecting voltage rail. The method includes determining, by the device, whether or not a presence of unused power pins is detected. Based on the detection, the method includes calculating a total amount of available additional power, repurposing the unused power pins as actively used power pins, and updating a power budget value based on the total amount of available additional power. The device may dynamically allocate power to accelerators based on a power allocation table and the power budget value.

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

Abstract: An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

Abstract: A method for analyzing power quality events in an electrical system includes processing electrical measurement data from or derived from energy-related signals captured by at least one of a plurality of metering devices in the electrical system to generate or update a plurality of dynamic tolerance curves. Each of the plurality of dynamic tolerance curves characterizes a response characteristic of the electrical system at a respective metering point of a plurality of metering points in the electrical system. Power quality data from the plurality of dynamic tolerance curves is selectively aggregated to analyze power quality events in the electrical system.

Abstract: Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.

Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.