Synchronization Of Clock Or Timing Signals, Data, Or Pulses Patents (Class 713/400)
  • Patent number: 11637955
    Abstract: An image capturing device includes an image capturing unit capturing an image at a timing based on a first frame rate and outputs data corresponding to the image after a first period, an image data generation unit generating image data based on the output data and outputting the image data after a second period, a display unit displaying a display image based on the image data after the second period and at a timing based on a second frame rate, and a mode selecting unit selecting a first or second mode. The first mode prioritizes reduction in a display delay time. The second mode prioritizes image quality of the display image over reduction in the display delay time. A total period of the first and second periods is less than or equal to a first vertical synchronization period based on the first frame rate when the first mode is selected.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 25, 2023
    Assignee: Seiko Epson Corporation
    Inventor: Ryuichi Shiohara
  • Patent number: 11606427
    Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 14, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Avraham Ganor, Arnon Sattinger, Natan Manevich, Reuven Kogan, Artiom Tsur, Ariel Almog, Bar Shapira
  • Patent number: 11601698
    Abstract: Systems and methods for intelligent synchronization of media streams are provided. A server may receive streams corresponding to an interactive session and sent over a communication network from user devices in the interactive session. A predetermined attribute may be identified as present in each of the streams, but received at different times by the server. The server may determine a time difference between a time that a predetermined attribute in a first stream of the streams was received and a time that the predetermined attribute in a second stream of the streams was received. The first stream and the second stream may then be synchronized using the time difference and provided to a recipient device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 7, 2023
    Assignee: SUPER LEAGUE GAMING, INC.
    Inventors: Brian Gramo, Arthur Kmbikyan, David Steigelfest
  • Patent number: 11595137
    Abstract: an orthogonal frequency division multiplexed (OFDM) output signal produced by a device in response to an OFDM input signal is accessed. The OFDM input signal includes OFDM input symbols in the time domain and the OFDM output signal includes OFDM output symbols in the time domain. The OFDM output symbols are time-aligned to the OFDM input symbols and a phase of the OFDM output signal is de-rotated with respect to the OFDM input signal. A complex equalization filter is applied to the OFDM output symbols in the time domain to obtain an estimate of the OFDM input symbols A distortion signal of the OFDM output signal is determined by subtracting the estimate of the OFDM input symbols. An error vector magnitude (EVM) is determined by dividing a root mean square of the distortion, by a root mean square of the OFDM input signal.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: February 28, 2023
    Assignee: Keysight Technologies, Inc.
    Inventor: Rishi Mohindra
  • Patent number: 11587670
    Abstract: A medical operation system includes an information processing apparatus, including processing circuitry configured to cause a map of an operating room to be displayed on a display, the map including an icon representing a device located in the operating room or accessible from the operating room, receive, via a user operation on the displayed map, designation information representing a designation of a change in at least one of an input source, an output destination, or an internal setting for the device, generate a control signal to control the device based on the designation information, and transmit the generated control signal to the device.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: February 21, 2023
    Assignee: SONY CORPORATION
    Inventors: Takahito Nakano, Takeshi Miyai, Keisuke Uyama, Daisuke Tsuru
  • Patent number: 11586483
    Abstract: A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 21, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Daniel John Pelham Wilkinson, Simon Christian Knowles, Matthew David Fyles, Alan Graham Alexander, Stephen Felix
  • Patent number: 11588697
    Abstract: In one embodiment, at least one processing device is configured to assign a plurality of devices of a cluster to a logical host group where at least one of the devices assigned to the logical host group has a network time parameter that is different than another of the devices assigned to the logical host group. The at least one processing device is further configured to determine a target network time parameter for the logical host group based at least in part on network time parameter related information about a given device of the plurality of devices assigned to the logical host group and to cause the plurality of devices to configure their respective network time parameters to the target network time parameter based at least in part on the assignment of the plurality of devices to the logical host group.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 21, 2023
    Assignee: Dell Products L.P.
    Inventors: Parminder Singh Sethi, Suren Kumar, Vinod Durairaj
  • Patent number: 11581881
    Abstract: An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: February 14, 2023
    Assignee: XILINX, INC.
    Inventors: Sarosh I. Azad, Benson Chau, Tomai Knopp
  • Patent number: 11579650
    Abstract: A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: February 14, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amitabh Mehra, David M. Dahle, Richard M. Born
  • Patent number: 11581877
    Abstract: A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: February 14, 2023
    Assignee: NXP B.V.
    Inventors: Mark Stoopman, Erik Olieman, Peter van der Cammen
  • Patent number: 11581968
    Abstract: A system (1000) is disclosed including a resource allocation optimization (RAO) platform (1002) for optimizing the allocation of resources in network (1004) for delivery of assets to user equipment devices (UEDs) (1012). The RAO platform (1002) determines probabilities that certain asset delivery opportunities (ADOs) will occur within a selected time window and uses these probabilities together with information concerning values of asset delivery to determine an optimal use of asset deliveries. In this regard, the RAO platform (1004) received historical data from repository (1014) that facilitates calculation of probabilities that ADOs will occur. Such information may be compiled based on asset delivery records for similar network environments in the recent past or over time.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: February 14, 2023
    Assignee: INVIDI Technologies Corporation
    Inventors: Samira Sadeghi, Ivan Mizera, David Ballantyne, Daniel C. Wilson
  • Patent number: 11575405
    Abstract: The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 7, 2023
    Assignee: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Yu Chih Wang
  • Patent number: 11575539
    Abstract: The present invention discloses an identification number numbering method and a multipoint communication system. The identification number numbering method includes the following steps: sending an identification number packet to a multipoint communication bus by a master device; receiving the identification number packet via the multipoint communication bus, and temporarily storing an identification number according to the identification number packet by a first slave device; changing a voltage level of a master device control output pin of the master device; and when the first slave device determines that a voltage level of a first control input pin coupled to the master device control output pin is correspondingly changed, updating a first slave device identification number of the first slave device according to the identification number.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 7, 2023
    Assignee: E Ink Holdings Inc.
    Inventors: Yi-Jhou Shen, Zhone-Yang Wu
  • Patent number: 11575364
    Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 7, 2023
    Assignee: Apple Inc.
    Inventors: Thomas Bauernfeind, Andreas Menkhoff, Michael Bruennert
  • Patent number: 11568779
    Abstract: A method for operating a visual display apparatus is specified. The apparatus comprises a first optoelectronic semiconductor component configured to emit electromagnetic radiation of a first wavelength and comprising a first intrinsic switch-on delay. The apparatus comprises a second optoelectronic semiconductor component configured to emit electromagnetic radiation of a second wavelength and comprising a second intrinsic switch-on delay. The second wavelength is different from the first wavelength. The first semiconductor component is operated with a first operating current according to a first actuation signal. The second semiconductor component is operated with a second operating current according to a second actuation signal.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: January 31, 2023
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Daniel Richter, Sven Weber-Rabsilber, Marcel Severin
  • Patent number: 11551743
    Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: January 10, 2023
    Assignee: Rambus, Inc.
    Inventor: Scott C. Best
  • Patent number: 11539799
    Abstract: Embodiments of the disclosure provided herein generally include a system and a method of configuring and/or controlling the transfer of information between two or more electronic devices due to the interaction of an electronic device and a host identifier signal generating system. Embodiments of the disclosure may include a system and a method of distributing useful information received by or contained within a memory of the electronic device based on the receipt of a host identifier signal. The electronic device may then perform one or more desirable functions or processes based the portable electronic device's interaction with the host identifier signal generating system.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 27, 2022
    Assignee: LOGITECH EUROPE S.A.
    Inventors: Olivier Gay, Mathieu Meisser, Thomas Luc Rouvinez, Nicolas Sasselli, Remy Zimmermann
  • Patent number: 11499945
    Abstract: Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: November 15, 2022
    Assignee: Vibrant Corporation
    Inventors: Leanne Jauriqui, Thomas Kohler, Alexander J. Mayes, Julieanne Heffernan, Richard Livings, Eric Biedermann
  • Patent number: 11487605
    Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Roberts, Dean E. Gonzales
  • Patent number: 11487436
    Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. McNeil, Jr., Niccolo' Righetti, Kishore K. Muchherla, Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11480994
    Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 25, 2022
    Assignee: STMicroelectronics Application GMBH
    Inventor: Rolf Nandlinger
  • Patent number: 11474945
    Abstract: Methods, systems, apparatuses, and computer program products are provided for prefetching data. A workload analyzer may identify job characteristics for a plurality of previously executed jobs in a workload executing on a cluster of one or more compute resources. For each job, identified job characteristics may include identification of an input dataset and an input bandwidth characteristic for the input dataset. A future workload predictor may identify future jobs expected to execute on the cluster based at least on the identified job characteristics. A cache assignment determiner may determine a cache assignment that identifies a prefetch dataset for at least one of the future jobs. A network bandwidth allocator may determine a network bandwidth assignment for the prefetch dataset. A plan instructor may instruct a compute resource of the cluster to load data to a cache local to the cluster according to the cache assignment and the network bandwidth assignment.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 18, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Virajith Jalaparti, Sriram S. Rao, Christopher W. Douglas, Ashvin Agrawal, Avrilia Floratou, Ishai Menache, Srikanth Kandula, Mainak Ghosh, Joseph Naor
  • Patent number: 11474557
    Abstract: In one embodiment, the present disclosure includes multichip timing synchronization circuits and methods. In one embodiment, hardware counters in different systems are synchronized. Programs on the systems may include synchronization instructions. A second system executes synchronization instruction, and in response thereto, synchronizes a local software counter to a local hardware counter. The software counter on the second system may be delayed a fixed period of time corresponding to a program delay on the first system. The software counter on the second system may further be delayed by an offset to bring software counters on the two systems into sync.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 18, 2022
    Assignee: GROQ, INC.
    Inventors: Gregory Michael Thorson, Srivathsa Dhruvanarayan
  • Patent number: 11476947
    Abstract: A low-power coherent receiver is enabled with enhanced performance for intra-datacenter reach optical interconnection applications using several techniques. The first is a coherent skew adjustment technique which enables lower-power baud-rate ADC sampling and baud-rate-spaced coherent equalization. The second is a real-valued or mixed-valued low-power coherent equalization technique, where a single-tap real-valued 4×4 MIMO equalizer plus four real-valued or two mixed-valued single-input single-out (SISO) equalizers are used for simultaneous polarization recovery, in-phase and quadrature (I/Q) phase error correction, and bandwidth equalization. The third is a power-efficient dual-DSP architecture to enhance coherent receiver performance, in which a complementary low-speed coherent DSP is introduced for optimal I/Q phase error correction and constellation decision parameters determination through more sophisticated algorithms that are too power hungry to be implemented in the primary high-speed DSP.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 18, 2022
    Assignee: Google LLC
    Inventors: Xiang Zhou, Hong Liu
  • Patent number: 11470567
    Abstract: In an aspect, a UE may perform clock synchronization in accordance with a first network timing reference, such as a unicast network timing reference (UNTR) or a broadcast networking timing reference (BNTR). The UE may detect event(s) associated with a connection to a BS, which may trigger a switch between the UNTR and the BNTR for clock synchronization. In a further aspect, a communications device (e.g., UE or BS) may determine to transition a UE between the BNTR and UNTR for clock synchronization, and may perform one or more actions to facilitate the network timing reference transition.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: October 11, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Vinay Joseph, Rajat Prakash, Prashanth Haridas Hande
  • Patent number: 11461196
    Abstract: The present invention provides a System and method for multi-tiered data synchronization. Data is synchronized between a master synchronization server, one or more proxy synchronization servers, and client devices. Client devices establish synchronization sessions with either a proxy synchronization server or a master synchronization server, depending on which server provides the “best” available connection to that client device. Each proxy synchronization server synchronizes data with client devices that have established a synchronization session with such proxy synchronization server. The master synchronization server synchronizes data with client devices that have established a synchronization session with the master synchronization server. Each proxy synchronization server synchronizes data with the master synchronization server. Metadata associated with synchronized files is synchronized throughout the system in real-time. Files may be synchronized in real-time or of a delayed time.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: October 4, 2022
    Assignee: Dropbox, Inc.
    Inventors: Kiren R. Sekar, Jack B. Strong
  • Patent number: 11463187
    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 4, 2022
    Assignee: Google LLC
    Inventors: Yuliang Li, Gautam Kumar, Nandita Dukkipati, Hassan Wassel, Prashant Chandra, Amin Vahdat
  • Patent number: 11455140
    Abstract: Provided are an electronic device and a method of controlling an external device by the electronic device. According to various embodiments of the present disclosure, a method of controlling an external device by an electronic device includes displaying, on a screen, a first user interface (UI) corresponding to first UI data received from an external server, transmitting, to the external device, second UI data corresponding to the first UI, receiving, from the external device, coordinates selected by a user using the external device, obtaining additional information related to the first UI when the coordinates correspond to a position of the first UI displayed on the screen, and transmitting, to the external device, the additional information and an execution command of an application using the additional information.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 27, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doochan Hwang, Minho Kim, Jinjoo Chung, Namhyun Kim, Sunho Park, Joonyoung Lee
  • Patent number: 11455023
    Abstract: A power module according to the first embodiment incorporates a power device, and drives the power device by using a control signal acquired from a microcomputer being a control circuit. The power module includes: a plurality of first terminals that receive input of the control signal from the microcomputer; a main circuit that drives the power device based on the control signal, and detects an abnormality of the power module; an error output circuit that outputs an error signal from a second terminal to the microcomputer when the abnormality is detected by the main circuit; and a switching circuit that causes the first terminal to operate as an output terminal for the microcomputer when the error signal is output. Information of the power device is output from the first terminal operating as the output terminal to the microcomputer.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 27, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masaki Sakai
  • Patent number: 11455950
    Abstract: A method for adjusting the signal frequency includes: acquiring a first number of times of outputting a reference signal at an active level within a reference duration, wherein a correlation between a frequency of the reference signal and temperature is less than a reference correlation threshold, the reference duration is negatively correlated with a frequency of a clock signal, a correlation between a frequency of a clock signal and temperature is greater than the reference correlation threshold, and a drive signal for driving a display device to display an image is generated based on the clock signal; acquiring a target adjustment value based on the first number of times if the first number of times is different from a reference number of times; and controlling and adjusting the frequency of the output clock signal based on the target adjustment value.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 27, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Xiao Ma, Qianqian Liu, Chang Wang
  • Patent number: 11456024
    Abstract: Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yutaka Uemura
  • Patent number: 11443783
    Abstract: A semiconductor device includes a memory device configured to have a first buffer and a second buffer, the first buffer storing a plurality of requests sent to a plurality of destinations, the second buffer storing identification information of the entry associated with a first destination of a first request written to first buffer; and an entry selector configured to identify the first destination from the plurality of destinations when the identification information of the entry is stored in the second buffer, and to read the first request from the plurality of requests stored in the first buffer by using the first destination.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 13, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Kohei Michibata
  • Patent number: 11443467
    Abstract: Automated correlation of process attribute value changes with events related to the changes. A managed historian utilizes a namespace property to correlate process tag values with corresponding events. The managed historian generates and provides to remote user devices a graphical user interface that includes a plot of data values of the process tag and a visual icon representing the event overlaid atop the plot of data values.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: September 13, 2022
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Brian Kenneth Erickson, Sripraneeth Kumar Nara, Ravi Kumar Herunde Prakash, Vinay T. Kamath, Abhijit Manushree
  • Patent number: 11443191
    Abstract: A parameter synchronization method is implemented in a computing device. The parameter synchronization method includes importing a deep learning training task of a preset model into a server communicatively coupled to the computing device, recording a preset number of iterative processes during the deep learning training, dividing each iterative process into a number of phases according to time, determining whether a time ratio of an H2D phase, a D2H phase, and a CPU phase in each iterative process is greater than a preset value, and confirming the server to use a copy mode for performing parameter synchronization when the time ratio of the H2D, D2H, and CPU phases is determined to be greater than the preset value.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 13, 2022
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Cheng-Yueh Liu
  • Patent number: 11431599
    Abstract: Techniques for network latency estimation in a computer network are disclosed herein. One example technique includes instructing first and second nodes in the computer network to individually perform traceroute operations along a first round-trip route and a second round-trip route between the first and second nodes. The first round-trip route includes an inbound network path of an existing round-trip route between the first and second nodes and an outbound network path that is a reverse of the inbound network path. The second round-trip route has an outbound network path of the existing round-trip route and an inbound network path that is a reverse of the outbound network path. The example technique further includes upon receiving traceroute information from the additional traceroute operations, determine a latency difference between the inbound and outbound network paths of the existing round-trip route based on the received additional traceroute information.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: August 30, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Shachar Raindel
  • Patent number: 11429135
    Abstract: One example includes a clock distribution system. The system includes a resonator feed network comprising a plurality of resonant transmission lines that each propagate a clock signal. The system also includes at least one resonator spine. Each of the at least one resonator spine can be conductively coupled to at least one of the resonant transmission lines, such that each of the at least one resonator spine propagates the clock signal. The system further includes at least one resonator rib conductively coupled to at least one of the at least one resonator spine. Each of the at least one resonator rib can be arranged as a standing wave resonator to propagate the clock signal.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 30, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Max E. Nielsen, Phillip Henry Fischer
  • Patent number: 11424751
    Abstract: Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 11418173
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Patent number: 11412470
    Abstract: According to certain embodiments, a method in a network node for delivering a time synchronization service comprises obtaining a timing accuracy threshold for a time synchronization service provided to a wireless device; determining, based on a first timing accuracy error at the network node and a second timing accuracy error between the network node and the wireless device, that a timing accuracy of the time synchronization service is equal or superior to the timing accuracy threshold, and transmitting the time synchronization service to the wireless device with a timing accuracy equal or superior to the timing accuracy threshold. The method further comprises, in response to determining that the timing accuracy of the time synchronization service is inferior to the timing accuracy threshold, reconfiguring the network node to improve the timing accuracy of the time synchronization service.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 9, 2022
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Angelo Centonza, Stefano Ruffini, Joachim Sachs, Magnus Sandgren, Mårten Wahlström
  • Patent number: 11399300
    Abstract: The disclosure pertains to a method for operating a user equipment in a radio access network. The method includes measuring first synchronisation signaling associated to a first cell of the radio access network, wherein for measuring a set of parametrisations of the first synchronisation signaling is utilised, in which the set of parametrisations is determined based on a signaling parametrisation of second synchronisation signaling associated to a second cell of the radio access network, and further based on a mapping of the signaling parametrization to the first set of parametrisations. The disclosure also pertains to related methods and devices.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 26, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Shaohua Li, Jianfeng Wang
  • Patent number: 11392168
    Abstract: In one embodiment, a method for managing clock synchronization for a baseboard management controller includes identifying, by a management unit of the information handling system, a real-time clock of the information handling system based on a real-time clock time value; receiving, by the management unit, a request for the real-time clock time value from the baseboard management controller; retrieving, by the management unit, the real-time clock time value from the real-time clock; sending, by the management unit, the real-time clock time value to a logic device of the information handling system; sending, by the logic device, an interrupt signal to the baseboard management controller indicating that the real-time clock time value is stored; retrieving, by the baseboard management controller, the real-time clock time value from the logic device; and updating, by the baseboard management controller, a baseboard management controller time value based on the real-time clock time value.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: July 19, 2022
    Assignee: Dell Products L.P.
    Inventor: Timothy M. Lambert
  • Patent number: 11386203
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Shay Benisty, Ariel Navon
  • Patent number: 11379526
    Abstract: Certain aspects provide techniques for disambiguating graph data. In one example, a method includes receiving entity data from a data source in a first format; converting the entity data in the first format to a second format, wherein the second format is a standardized input format for a disambiguation pipeline; determining a blocked data set from the entity data in the second format based on a blocking parameter, wherein: the blocked data set comprises data regarding a first plurality of entities, and the first plurality of entities is a subset of a second plurality of entities represented in the entity data from the data source; matching at least two entities in the first plurality of entities in the blocked data set; merging the at least two entities into a single entity; generating a unique ID for the single entity; and importing the single entity into a graph database.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 5, 2022
    Assignee: INTUIT INC.
    Inventors: Sudhir Srinivas, Kevin Geraghty
  • Patent number: 11378999
    Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Yu-Shan Wang, Martin Clara, Daniel Gruber, Hundo Shin, Kameran Azadet
  • Patent number: 11371965
    Abstract: Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Vibrant Corporation
    Inventors: Leanne Jauriqui, Thomas Köhler, Alexander J. Mayes, Julieanne Heffernan, Richard Livings, Eric Biedermann
  • Patent number: 11356189
    Abstract: A method of virtualizing a clock is executed by a network controller comprising a processor and computer-readable instructions for creating one or more virtual network elements comprising one or more virtual clocks. The method comprises retrieving, at a first virtual network element of the one or more virtual network elements, a first time of day value and a second time of day value. The method further comprises adjusting the amount of time elapsed based, in part, on a frequency adjustment value and incrementing a clock value based on the amount of time elapsed.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: June 7, 2022
    Assignee: Accedian Networks Inc.
    Inventor: Thierry DeCorte
  • Patent number: 11353918
    Abstract: The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 7, 2022
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Eric Karl Mautner, Brianna Klingensmith
  • Patent number: 11340596
    Abstract: To optimize an operation of a manufacturing facility by presenting a countermeasure for improving quality, even in a manufacturing process where the product quality changes even under constant manufacturing conditions. A countermeasure recommendation device includes a data acquisition unit for collecting a plurality of pieces of facility data, and assigning a label for each process to each piece of the facility data; a countermeasure detection unit for creating countermeasure record data; a countermeasure recommendation unit for calculating the characteristic amount, extracting the characteristic amount, and selecting the countermeasure related to the extracted characteristic amount; and a countermeasure presentation unit for presenting the countermeasure in a visualized state.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 24, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masakazu Takahashi, Keiro Muro
  • Patent number: 11334110
    Abstract: In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: May 17, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Xiaobin Yuan, Aida Varzaghani, Irina Gavshina, Mouna Safi-Harab
  • Patent number: 11314236
    Abstract: An objective of the present invention is to achieve optimal operating guidance on day-to-day operations in a plant while also achieving, for example, soundness and reduced operating costs for a plant equipment piece without increasing the load on the central operation room, by determining the optimal configuration value for the operating value of the plant equipment piece. To this end, there is provided an equipment state monitoring device 331 for analyzing an operating state of a first plant equipment piece 303 during a prescribed period. The equipment state monitoring device 331 analyzes the operating state of the first plant equipment piece 303, and depending on a result of the analysis, carries out determination of an optimal operating value.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 26, 2022
    Assignee: MITSUBISHI HEAVY INDUSTRIES POWER ENVIRONMENTAL SOLUTIONS, LTD.
    Inventor: Yuji Otani