Abstract: A method for online monitoring of a physical environment using a variable data sampling rate is implemented by a computing device. The method includes sampling, at the computing device, at least one data set using at least one sampling rate. The method also includes processing the at least one data set with condition assessment rules. The method further includes determining whether the at least one data set indicates a change in state of the physical environment. The method additionally includes updating the at least one sampling rate.

Abstract: A method is provided for noise distribution shaping of signals, particularly for the application in receivers for CDMA signals. The method includes the acts of generating a blanking control signal by comparing a received signal with at least one blanking threshold, adapting the at least one blanking threshold or the received signal according to an offset value depending on the amplitude of the received signal, and modifying the noise distribution of the received signal by applying blanking of the received signal under control of the blanking control signal.

Abstract: Apparatuses, systems, and methods are disclosed for an output data path for non-volatile memory. A buffer may include a plurality of buffer stages. A buffer stage width may be a width of an internal bus for a non-volatile memory element. A buffer may include two or more read pointers, updated by an internal controller at different times in response to different portions of a clock signal. A parallel-in serial-out (PISO) component may receive data via an internal data path having a data path width equal to an internal bus width, and may output the data in a series of transfers controlled according to a clock signal, via an output bus having an output bus width narrower than an internal bus width. A PISO component may receive data from a portion of a buffer stage in response to an internal controller updating a read pointer to point to the buffer stage.

Abstract: A redundant computer system utilizing comparison diagnostics and voting techniques includes a plurality of redundant channels. Each pair of the processors receives/obtains process information from I/O modules via dual redundant sensors (DRS). The processors execute an application program, whereby output module is utilized for comparing output data of the two processors. Output module receives output data from neighboring modules, if there is a deviation or other disparity in the output data. Each pair of processors, a voter and an improper sequence detector component disables the output module, if a majority of signals vote that output module fails. In addition, the system uses 2-of-3 voting, the system remains operational in the presence of up two transient or hard failures.

Abstract: A method can be used for managing a power supply voltage on an output power supply pin of a USB Type-C source device coupled to a USB Type-C receiver device via a USB Type-C cable. A first measurement of a first voltage on a channel configuration pin of the cable is performed when the receiver device is not powered and a second measurement of a second voltage on the channel configuration pin is performed when the receiver device is powered. A difference between the first and second voltages is calculated and the power supply voltage is modified as a function of a value of the difference.

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Abstract: An apparatus includes control circuitry configured to receive a first N-bit count value in a first domain, and to determine an M-bit increment indicating value based on the first N-bit count value and a reference value, where M<N. Boundary circuitry is configured to provide the M-bit increment indicating value to a second domain. In the second domain, updating circuitry configured to update a second N-bit count value based on an increment represented by the M-bit increment indicating value provided by the boundary circuitry.

Abstract: Compressible shock absorber (100), characterized in that it includes at least one pair of shock absorbing elements (110) co-axial and telescopic reciprocally sliding along a longitudinal sliding axis (X); said shock absorbing elements (110) co-axially include a cavity (115) and include therein a compressible air volume during their axial sliding reciprocal between a first position of maximum axial extension and a second position of lower axial extension; said at least one pair of shock absorbing elements (110) includes air extractors (140) susceptible of allowing an extraction of the air from said internal volume progressive with the reduction of the axial extension following the impact of a vehicle against said shock absorber.

Abstract: An information handling system includes a processor complex and a microcontroller unit (MCU). The processor complex includes a Real-Time Clock (RTC) function associated with a port of the processor complex, and that can be invoked on the processor complex by a call to the port. The MCU includes RTC logic to maintain time base information for the information handling system. When the RTC function is invoked, the processor complex traps the call to the port and redirects the call to the MCU. When the MCU receives the redirected call, the MCU invokes the RTC logic to respond to the redirected call and to provide the time base information to the processor complex.

Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry.

Abstract: A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

Abstract: The present invention is related to an authentication system of synchronizing instant timestamp issued by a digital timestamp device and a method thereof. The digital timestamp device provides an instant machine time, and the provider end uses the digital timestamp device to stamp an instant digital timestamp on a digital content. Meanwhile, the provider end records the position of the digital content whereon the digital timestamp is stamped as a stamp position, and store the digital content, the instant digital timestamp, the stamp position, and the network location information together as a reliable digital content. The receiver end can retrieve the reliable digital content from a third party end or connect to the provider end to confirm whether the reliable digital content has the identical instant digital timestamp and stamp position to ensure the authenticity of the received reliable digital content.

Abstract: A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first code representing a first design including a first latch configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. The method further includes changing, using the computer, the first code into a second code representing a second design, the changing further including transforming, using the computer, the first latch into a second latch configured to be evaluated in accordance with a second signal different from the first signal after the first signal is received at the second latch, when the second code for the second design is compiled for programming into the hardware verification system.

Abstract: A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and includes a plurality of first resistors and a first selection unit. The first resistors are connected in series with one another and dividing a first operation voltage to generate a plurality of first divided voltages. The first selection unit selects one of the first divided voltages as the first reference voltage according to a first control signal.

Abstract: An electronic device includes a first processing unit and a second processing unit that has a power state control unit and executes a process corresponding to received data with which the first processing unit is not compatible. When the received data is present in a non-wake-up state, the power state control unit sets a power state of the electronic device to a temporary wake-up state regardless of a period set as a time period of the non-wake-up state to obtain an actual time period of the non-wake-up state as a basic value for calculating the time period of the non-wake-up state. The power state control unit sets average value of a plurality of obtained latest basic values as the time period of the non-wake-up state.

Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.

Abstract: A storage system and a data transferring method thereof are provided. The storage system includes at least one drawer storage device, a backplane board and a processing unit. Each of the drawer storage devices accommodates at least one storage device, and has a first connecting interface. The backplane board has a second connecting interface. The backplane board and each of the drawer storage devices are connected with each other through a transmission line. The first connecting interface and the second connecting interface are connected or isolated with each other. The processing unit detects a connection status between the first connecting interface and the second connecting interface, and determines to transfer data through at least one of the transmission line and a connection between the first connecting interface and the second connecting interface according to the connection status.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

Abstract: Described are methods and apparatuses for synchronizing two or more sensors of an UAV. In the implementations described, a synchronization event is performed such that identifiable signals of the synchronization event can be collected by each sensor of the UAV. The synchronization event may be generated by a synchronization event component that generates multiple output signals (e.g., audio, visual, and physical) at approximately the same time so that different sensors can each collect and store at least one of the output signals. The collected signals are then compared and the sensors are adjusted to align the signals.

Abstract: Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved.

Abstract: In accordance with one embodiment, an abnormality notification apparatus comprises a display device, a first drive circuit, at least one processor, a pulse generating circuit and a second drive circuit. The first drive circuit turns on the display device according to a control signal from a display control section. The processor operates according to separate programs. The pulse generating circuit outputs, during a period when a signal indicating an abnormality of any processor is input, a pulse signal corresponding to a blinking pattern for notifying the abnormality of the processor. The second drive circuit blinks the display device in response to the pulse signal output by the pulse generating circuit.

Abstract: In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock frequency that is lower than the first clock frequency. The processor also includes phase locked loop (PLL) logic to generate a first signal having a first frequency corresponding to the first clock frequency and to provide the first signal to the first domain. The processor also includes a first clock to produce a first squash signal that is determined based at least in part on the second clock frequency, and also first logic to generate a second signal having a second frequency corresponding to the second clock frequency by gating the first signal with the first squash signal and to provide the second signal to the second domain. Other embodiments are described and claimed.

Abstract: An apparatus for monitoring operation of a design under test (DUT) includes an incoming clock edge input; an outgoing clock edge input; an enable input; a protocol input; an upstream clocking input; and a downstream clocking input. The apparatus also includes a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine spurious and missing active clock edges sent from the monitored clock gate. The apparatus also includes a clock categorization output to output the determination of the active clock edges from the monitored clock gate as missing or spurious.

Abstract: An image capturing device includes an image capturing unit capturing an image at a timing based on a first frame rate and outputs data corresponding to the image after a first period, an image data generation unit generating image data based on the output data and outputting the image data after a second period, a display unit displaying a display image based on the image data after the second period and at a timing based on a second frame rate, and a mode selecting unit selecting a first or second mode. The first mode prioritizes reduction in a display delay time. The second mode prioritizes image quality of the display image over reduction in the display delay time. A total period of the first and second periods is less than or equal to a first vertical synchronization period based on the first frame rate when the first mode is selected.

Abstract: Avoiding long access latencies in redundant storage systems is disclosed, including: determining a first device associated with a request is in a slow access period based at least in part on a scheduled slow access period, wherein the first device is included in a plurality of devices associated with a redundant storage system; and reconstructing data associated with the request from one or more devices included in the plurality of devices other than the first device.

Abstract: A control network communication arrangement includes a second protocol embedded into a first protocol in a way that modules supporting the second protocol may be aware of and utilize the first protocol whereas modules supporting only the first protocol may not be aware of the second protocol. Operation of modules using the second protocol does not disturb operation of the modules not configured to use or understand the second protocol. By one approach, the messages sent using the second protocol will be seen as messages sent using the first protocol but not having a message necessary to understand or as needing a particular response. In another approach, modules using the second protocol can be configured to send messages within a CAN message frame without being compatible with CAN.

Abstract: An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.

Abstract: A method for managing jitter includes determining, by a processor of a master device, at least one of device capabilities of at least one satellite device, device capabilities of the master device, or channel conditions; determining, by the processor of the master device, a de-jitter buffer size based on the at least one of the device capabilities of the at least one satellite device, the device capabilities of the master device, or the channel conditions; and applying, by the processor of the master device, de-jitter buffer having the determined de-jitter buffer size.

Abstract: A system and method is provided for optimizing a SyncML slow sync between a proprietary client and server. When a slow sync is detected, the client and server can depart from the normal SyncML protocol and process summary data without having to compare all items on a field-by-field basis.

Abstract: Techniques related to encoding image content for transmission and display via a remote device with improved latency and efficiency are discussed. Such techniques may include skipping one or more of frame capture, encode, packetization, and transmission for a frame based on a skip indicator. One or more selective updates may be captured for the skipped frame and integrated into an encode of a subsequent non-skipped frame, which may be packetized and transmitted for to the remote device for presentment to a user.

Abstract: A data reading circuit including a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain.

Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

Abstract: In one embodiment, a multiplex control device includes three or more control modules to execute same operations for same input signals, and a majority decision module to output an output signal that matches majority of output signals outputted by the control modules. Each control module includes an input module to convert an input signal into an input value, a first determination module to obtain input values from input modules of respective control modules to determine whether majority of input values among the obtained input values match, an operation executing module to execute an operation using the matched input value to generate an output value, a second determination module to obtain output values from operation executing modules of respective control modules to determine whether majority of output values among the obtained output values match, and an output module to convert the matched output value to generate an output signal.

Abstract: An information processing system includes a relay device and first and second information processing devices. The relay device includes a reception unit that receives from a communication terminal a process request indicating first and second processes; and a terminal request transmission unit that sends the process request to the first information processing device in response to a first request, and sends an execution result of the first process and the process request to the second information processing device in response to a second request. The first information processing device includes a first process control unit that controls execution of the first process according to the process request; and a transmission unit that sends the execution result in response to the process request. The second information processing device includes a second process control unit that controls execution of the second process based on the execution result according to the process request.

Abstract: The present invention provides a method, a network device and a system for allowing for resuming a preceding incomplete synchronization session is provided, wherein the preceding incomplete synchronization session has been interrupted during its performing. In principle the resuming of the preceding incomplete synchronization session is based on the following operations according to the inventive concept. A communication connection for synchronization of data between a first and a second device is establishing. The first and the second device comprise each a predefined set of data records to be synchronized. A first and a second update identifier are communicated between the first and the second device. The first update identifier specifies a preceding complete synchronization session having been performed between them and the second update identifier specifies a preceding incomplete synchronization session having been performed between them.

Abstract: A method can include receiving, at a given node, a continuous stream of input media from a media source. A value can be computed as a function of each of a plurality of data blocks of the continuous stream of input media received by the given node. The method can also include receiving, at the given node, values computed for a plurality of data blocks of the continuous stream received by another node. A set of the received values from the other node can be correlated with a set of the computed values for the given node to determine an offset between the blocks of the continuous stream of input media that are received by the given node and the blocks of the continuous stream of input media that are received by the other node.

Abstract: A portable device includes: a first interface circuit configured to receive, from an information processing apparatus, device information of the information processing apparatus; a second interface circuit configured to receive, from outside device through wireless communication link, a start signal for the information processing apparatus; a memory configured to store a list of information processing apparatuses that are to be permitted to perform wireless communication with the portable device; and a processor configured to compare the device information received from the information processing apparatus with the list stored in the memory, enable wireless communication functionality of the second interface circuit when a result of the comparison indicates that the portable device is coupled to an information processing apparatus which is permitted to perform wireless communication, and transmit a start signal to the information processing apparatus when the start signal is received by using the enabled wire

Abstract: An application runs at a first operating frequency if the application is designed for a current version of a system and runs at a second operating frequency if the application is designed for a prior version of the system that operates at a lower frequency than the first operating frequency. The second operating frequency may be higher than the operating frequency of the prior version of the system to account for differences in latency, throughput or other processing characteristics between the two systems. Software readable cycle counters are based on a spoof clock running at the operating frequency of the prior version of the system, rather than the true operating frequency. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

Abstract: A radio control board exchanges data with a radio frequency (RF) front end using a messaging protocol over an interface that includes separate data and control channels. Training data can also be passed over the interface for tuning the clock phase.

Abstract: A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

Abstract: A method includes receiving a driver model for a device. The driver model includes a list of variables associated with the device and one or more characteristics of the variables. The method includes determining whether the driver model is format-compliant and validating syntax of the driver model based at least partially on a driver template that is accessible to a third party. In response to the driver model being format-compliant and the syntax being valid, the method includes generating a verified file that is representative of the driver model. The verified file is formatted to dynamically load into a device application module during operation and to dynamically support the device. The method includes communicating the verified file to a user apparatus and adding an integrity check value thereto. In response to the driver model being format-noncompliant or the syntax being invalid, the method includes communicating an error message.

Abstract: Systems and methods for providing trusted time service for the off-line mode of operation of a processing system. An example processing system comprises: a first processing device communicatively coupled to a real-time clock, the first processing device to modify an epoch value associated with the real-time clock responsive to detecting a reset of the real-time clock; and a second processing device to execute, in a first trusted execution environment, a first application to receive, from the first processing device, a first time value outputted by the real-time clock and a first epoch value associated with the real-time clock.

Abstract: A clock generator for use in an electronic system comprising an integrated circuit such as a microcontroller. A plurality of oscillators are selectively enabled to produce a respective plurality of oscillator signals. For each of a plurality of clock outputs, a mux selects a respective one of the oscillator signals in response to a respective select signal provided by a clocked facility. The selected oscillator signal is gated out as the respective clock signal in response to a respective gate signal also provided by the clocked facility.

Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.

Abstract: An automation device is provided, which comprises an operating system having a first system clock and a communication system having a second system clock. The first system clock is intended to control a system time cycle of the operating system, and the second system clock is intended to control a system time cycle of the communication system. Furthermore, the first system clock and the second system clock are synchronized in time.

Abstract: This invention relates to methods and systems for estimating and checking synchronization accuracy, in particular frequency synchronization accuracy. It is particularly applicable to synchronization methods and systems which involve a digital phase-locked loop (DPLL) and embodiments provide methods and systems for estimating and tracking how well the DPLL is frequency synchronized to a source frequency. In one embodiment, frequency synchronization accuracy is used as an additional quality metric for mobile call handover between base stations. Call handover is of major importance within any mobile network; without checking frequency synchronization before handover dropped calls and interrupted communication can result.