Abstract: A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the internal oscillator; the frequency multiplier processes frequency multiplication on the clock after frequency division and transmits the clock after frequency multiplication to the USB main structure; the receiving counter receives an SOF packet which is transmitted by a host according to the clock outputted by the frequency multiplier, and counts intervals of receiving the SOF packet; and the frequency division controller compares the difference between the counting result of the receiving counter and a standard interval, controls and regulates frequency division parameters of the controllable frequency divider according to a comparing result thereo

Abstract: In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.

Abstract: A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.

Abstract: A computing device includes a first BIOS chip and a second BIOS chip. Each of the first and second BIOS chips store a BIOS image and comprises a plurality of data blocks to store BIOS data of the BIOS image. During a booting process of the computing device, the BIOS data stored in odd data blocks of the first BIOS chip and the BIOS data stored in even data blocks of the second BIOS chip are respectively accessed and are stored in a cache of a middleware controller. A processor of the computing device accesses the BIOS data from the cache of the middleware controller during the booting process.

Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.

Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

Abstract: Method and system for a device having a processor module for maintaining a connection with another device are provided. The device includes a timer module having a plurality of timers, where the resolution for each timer is maintained by one or more processor modules; and a timer state module that stores an indicator value for indicating a timer state. A timer is assigned to the connection and the processor module manages the resolution of the timer. The processor module sends a request to the timer module for arming the timer and the timer module sets the timer state as active in a first storage location maintained by the timer state module; and responds to the processor module after the timer is activated. The processor module uses the information in the response for requesting a disarm operation.

Abstract: A timer unit having a first output mode and a second output mode, the timer unit includes a first register that stores a first value, a second register that stores a second value, a third register that stores a third value, a counter that generates a count signal based on the first value, and an output circuit that outputs a first output signal and a second output signal. When the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal and the second value, and outputs the second output signal having a pulse width determined by the count signal and the third value. When the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal, the second value and the third value.

Abstract: A method for reducing electromagnetic emissions by an image scanner comprises cyclically dithering a frequency of a clock signal of the image scanner by repeated dither cycles, determining a phase of the dither cycle when a scan pass of a page of a document commences; and commencing all subsequent scan passes of the page of the document at a particular phase shift from the determined phase of the dither cycle.

Abstract: A method, system, and computer program product to integrate functional analysis and common path pessimism removal (CPPR) in static timing analysis include determining initial path slack for a path for a given timing analysis test. The method also includes comparing the initial path slack with a threshold value to determine if the path passes or fails the given timing analysis test, and based on the path failing the given timing analysis test, performing the functional analysis on the path only based on performing the CPPR on the path, or performing the CPPR on the path only based on a result of performing the functional analysis on the path.

Abstract: A memory controller (40) is adaptable to scaling of a system clock frequency, to enable another device (10) to access a memory (20), and has a part for outputting control signals having some timing characteristics not entirely scalable with scaling of the system clock frequency. In response to an indication of a change in a frequency of the system clock, the memory controller adapts the part autonomously to enable it to output new digital memory control signals synchronized to the changed system clock and which also have the non scalable timing characteristics. This avoids the need for the processor to adapt the memory controller. Hence the adaptation can be carried out more quickly, leading to less disruption to other parts of the system and means the frequency scaling can be carried out more often.

Abstract: The present invention applies to the field of integrated-circuit control, and provides a temperature feedback control system and method for DVFS (Dynamic Voltage Frequency Scaling). In the present invention, a main processor sends a control data packet to a microprocessor according to a received temperature feedback trigger signal, and the microprocessor immediately triggers working of a temperature data acquiring module, and after the temperature data acquiring module acquires real-time temperature data of a chip, executes a temperature feedback algorithm on the real-time temperature data according to the control data packet to output a corresponding performance control parameter, so as to enable a DVFS circuit to adjust a working frequency and a working voltage of the chip, and further enable the chip to implement automatic frequency and voltage adjusting at a low voltage and a low temperature and at a high voltage and a high temperature.

Abstract: A system on chip includes a plurality of function blocks configured to perform predetermined functions, respectively, a clock control unit configured to generate a plurality of operating clock signals that are provided to the plurality of function blocks, respectively, a clock monitor configured to monitor frequencies of the operating clock signals to generate an interrupt signal, and a processor configured to control the frequencies of the operating clock signals based on the interrupt signal. The clock monitor includes a selector configured to select one of the operating clock signals to provide a selected clock signal, a frequency detector configured to detect a frequency of the selected clock signal to provide a detection frequency, and an interrupt generator configured to generate the interrupt signal based on the detection frequency, where the interrupt signal indicates a frequency abnormality of the operating clock signal corresponding to the selected clock signal.

Abstract: A method and virtualization software for providing at least two mutually independent time sources for at least one real-time operating system of a data processing device including virtual runtime environments, where a general-purpose operating system runs in one virtual runtime environment, and the virtual runtime environments are managed by virtualization software (hypervisor). A first time source is exclusively assigned to each real-time operating system, where the data processing device includes a second time source independent of the first time source, the second time source is configured to periodically generate an interrupt, the first processor core enters a routine of the virtualization software (hypervisor) with each interrupt triggered by the second time source, the content of at least one memory cell readable by the real-time operating system is updated and used as a time source, which is independent of the first time source, to control the first time source.

Abstract: A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Abstract: A digital/analog converter (30) with a first return-to-zero unit (311) which is connected to a first busbar (321), wherein the first busbar (321) is connected in each case to a first output of several differential units (351, 352, 35n). In this context, the first return-to-zero unit (311) provides at least one clock input which is directly or indirectly connected to a first photodiode, wherein the first photodiode is fed from a pulsed light source (5).

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: The present invention prevents performance degradation caused by a multiplication frequency of a memory clock in a wireless communication system by changing a frequency of the memory clock so that a multiplication frequency is not sufficiently close to a transmission/reception frequency that will cause noise or interference with a data transmission/reception. A communication apparatus according to the present invention includes a controller comprising at least one processor; and a memory for operating at a clock provided from the controller. The controller checks a communication frequency, determines whether the communication frequency is a value in a range of interference from a multiplication frequency of a memory clock frequency, and changes the memory clock frequency.

Abstract: A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.

Abstract: A method of generating a clock includes the steps of calculating a first frequency division number through dividing a frequency of an input clock by a target frequency and a specific integer k (k?2); calculating a second frequency division number according to the first frequency division number; dividing a period of time of one cycle of the target frequency by the specific integer k to obtain sections in a number of the specific integer k; dividing the frequency of the input clock with the second frequency division number within one of the sections; dividing the frequency of the input clock with the second frequency division number within each remaining one of the sections in a number of (k?1); and generating the clock having a frequency with one cycle equal to a period of time corresponding to each of the sections.

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

Abstract: A method includes receiving a first clock signal from a first clock source at a clock monitoring unit. The method also includes counting a first number of pulses in the first clock signal during a specified time period. The method further includes identifying a fault with the first clock source when the first number does not have an acceptable value. In addition, the method includes testing the clock monitoring unit by determining whether the clock monitoring unit identifies an artificial clock fault. The time period could be defined by receiving a second clock signal, counting a second number of pulses in the second clock signal, and signaling when the second number meets or exceeds a threshold value. In response to the identified fault with the first clock source, a second clock source could be used to provide a second clock signal.

Abstract: A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.

Abstract: An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.

Abstract: A network device including a plurality of queues configured to store respective frames of data having a priority level. The network device includes a shaper configured to transmit, during a first portion of a transmission interval, frames of data from a first one of the plurality of queues having a highest priority level, block frames of data from a second one of the plurality of queues during a blocking band extending from a first time prior to a start of the transmission interval to a second time indicating the start of the transmission interval, determine, based on the second time and a maximum frame size to be transmitted during the transmission interval, the first time, and selectively transmit, subsequent to the first time and prior to the second time, frames of data from the second one of the plurality of queues based on the second time.

Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.

Abstract: The present invention discloses a USB3.0 clock frequency generation device without crystal oscillator, that is, the crystal oscillator used in the USB3.0 device (or apparatus) is removed and replaced with an oscillator circuit module in the present invention, in which a simple circuit module is added to the controller circuit of the USB3.0 device to provide accurate and proper timing signals needed. The oscillator circuit module includes an oscillator block, a frequency divider block, a delta-sigma modulator block, and a preset number block.

Abstract: Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other.

Abstract: An integrated circuit device may have an internal oscillator for generating a system clock, a trimming logic with a trimming register for adjusting an oscillation frequency of the internal oscillator; a serial data receiver, wherein a serial data stream includes a synchronization signal. The synchronization signal is operable to indicate that the system clock correct, too fast or too slow. The device may further have a circuit for decoding the synchronization signal operable to re-adjust a value stored in the trimming register upon evaluation of the synchronization signal.

Abstract: In certain embodiments, a method includes receiving, using one or more processors, a trigger expression. The method may include processing, using the one or more processors, the trigger expression, the trigger expression comprising a first one or more terms comprising a first one or more fields, to generate a reduced trigger expression. The reduced trigger expression includes a second one or more terms comprising a second one or more fields and being logically equivalent to the trigger expression. The method may include generating, using the one or more processors, a dynamic state machine by generating a first data structure comprising each of the second one or more fields, generating, based on the first data structure, an expanded trigger expression by adding one or more additional terms for possible state transitions, and generating, based on the expanded trigger expression, a second data structure.

Abstract: Embodiments of the present invention analyze a plurality of parallel channels and identify specific channel(s) that have skew outside of an acceptable skew error margin. In certain embodiments, this skew is identified by determining the timing misalignment between a channel under test and a deskew channel. Other channels within the plurality of channels are masked by transmitting a repeating masked bit pattern. This timing misalignment may be measured by comparing a segment within the channel under test to a corresponding segment within the deskew channel and identifying a time differential between the two segments.

Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.

Abstract: A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.

Abstract: Generating monotonically increasing time-of-day values in a multiprocessor system is provided. Synchronization impulses are received by a processor of the multiprocessor system, and an execution of a read instruction of a time-of-day value within a processor of the processors is refused, if the execution of the read instruction of the time-of-day value is requested after a predefined time after a synchronization impulse of the synchronization impulses, and if a trigger signal, indicative of new data received by a related memory system, has been received after the predefined time, wherein the memory system is external to the processor.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

Abstract: A time reference system includes a master clock, generating a clock reference, interface logic and a CPU-based subsystem. The interface logic receives the clock reference and generates the clock, pulses, and timestamp signals. The CPU-based subsystem includes an internal counter, a CPU and a clock synthesizer, the CPU and receiving the pulses and timestamp signals. The clock synthesizer receives the clock signal and generates a CPU clock signal. Some examples include an FPGA-based subsystem having an FPGA-based card coupled to the interface logic for receipt of the clock, pulses and timestamp signals. In a method the timestamp value TO is generated by the CPU upon receipt of the timestamp signal. Upon receipt by the CPU of the next pulse signal, a timestamp counter baseline value TSCO is generated so the CPU internal counter is calibrated to the clock signal.

Abstract: A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.

Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.

Abstract: A timer device includes a RES input terminal (first external terminal), an input time determination circuit that determines the time length relationship between an input time of a predetermined signal input to the RES input terminal and a given determination time, and a pre-settable down counter (counting circuit) that counts a given set value. The pre-settable down counter changes a process according to a determination result of the input time determination circuit.

Abstract: A channel selection circuit in a serial audio communication device provides channel selection for insertion or extraction of data to or from a multiplexed serial data stream without the requirement of extra channel selection inputs. The channel selection circuit has multiple counters structured such that each counter represents a channel of the serial data stream. The input of each counter receives one of the multiple synchronizing timing signals. The input of the designated counter receives one timing signal that has the greatest frequency. The remaining counters receive the word select timing signals for determining which channel is being selected. A ready output of each counter is a channel indicator in communication with multiple signal selection circuits for selecting the multiple timing signals to be transferred to a data processing device for inserting or extracting data to or from the multiplexed serial data stream.

Abstract: A microprocessor has a plurality of debug modules, multiple sets of processor cores provided corresponding to the debug modules so that each set of the processor cores are debugged by the corresponding debug module, and a plurality of debug ring units provided corresponding to the debug modules, each debug ring unit generating a debug ring signal for instructing the corresponding processor cores to transit to a debug mode. The debug ring units are connected to generate a ring and sequentially transmit the debug ring signal, and when receiving the debug ring signal, each debug ring unit outputs, to the corresponding debug module, a debug transition signal for instructing the corresponding processor cores to transit to the debug mode.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed.

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract: A system utilizing time tracking is disclosed. The system includes a real time clock, a time component, and a controller. The real time clock is configured to track time. The time component is configured to measure a time value without an additional power source. The controller is configured to determine an elapsed time using the time value and calibration information and to update the real time clock using the elapsed time in a restart mode.

Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Abstract: Timing circuits including supervisor chip(s), capacitors, and latches. The supervisor chip(s) and capacitors cooperate to generate an electrical signal (window signal) having a high logic state when the window is open. The latches are used to determine whether an event of interest occurred while the window was open using the generated window signal and an electrical signal asserted upon occurrence of the event of interest.

Abstract: A system-on-chip includes a symmetric multi-processor including a plurality of cores, each configured to operate in a high performance operating mode and a low performance operating mode. The system-on-chip further includes a clock management unit configured to provide an operating clock signal to the symmetric multi-processor, a state management unit configured to monitor operating states of the cores, a temperature management unit configured to monitor a temperature of the symmetric multi-processor, and a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor. The symmetric multi-processor control unit is further configured to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores, which indicate a quantity of cores that are currently in operation.

Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.